malidp_hw.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. *
  4. * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
  5. *
  6. * ARM Mali DP hardware manipulation routines.
  7. */
  8. #ifndef __MALIDP_HW_H__
  9. #define __MALIDP_HW_H__
  10. #include <linux/bitops.h>
  11. #include "malidp_regs.h"
  12. struct videomode;
  13. struct clk;
  14. /* Mali DP IP blocks */
  15. enum {
  16. MALIDP_DE_BLOCK = 0,
  17. MALIDP_SE_BLOCK,
  18. MALIDP_DC_BLOCK
  19. };
  20. /* Mali DP layer IDs */
  21. enum {
  22. DE_VIDEO1 = BIT(0),
  23. DE_GRAPHICS1 = BIT(1),
  24. DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
  25. DE_VIDEO2 = BIT(3),
  26. DE_SMART = BIT(4),
  27. SE_MEMWRITE = BIT(5),
  28. };
  29. enum rotation_features {
  30. ROTATE_NONE, /* does not support rotation at all */
  31. ROTATE_ANY, /* supports rotation on any buffers */
  32. ROTATE_COMPRESSED, /* supports rotation only on compressed buffers */
  33. };
  34. struct malidp_format_id {
  35. u32 format; /* DRM fourcc */
  36. u8 layer; /* bitmask of layers supporting it */
  37. u8 id; /* used internally */
  38. };
  39. #define MALIDP_INVALID_FORMAT_ID 0xff
  40. /*
  41. * hide the differences between register maps
  42. * by using a common structure to hold the
  43. * base register offsets
  44. */
  45. struct malidp_irq_map {
  46. u32 irq_mask; /* mask of IRQs that can be enabled in the block */
  47. u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */
  48. u32 err_mask; /* mask of bits that represent errors */
  49. };
  50. struct malidp_layer {
  51. u16 id; /* layer ID */
  52. u16 base; /* address offset for the register bank */
  53. u16 ptr; /* address offset for the pointer register */
  54. u16 stride_offset; /* offset to the first stride register. */
  55. s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
  56. u16 mmu_ctrl_offset; /* offset to the MMU control register */
  57. enum rotation_features rot; /* type of rotation supported */
  58. /* address offset for the AFBC decoder registers */
  59. u16 afbc_decoder_offset;
  60. };
  61. enum malidp_scaling_coeff_set {
  62. MALIDP_UPSCALING_COEFFS = 1,
  63. MALIDP_DOWNSCALING_1_5_COEFFS = 2,
  64. MALIDP_DOWNSCALING_2_COEFFS = 3,
  65. MALIDP_DOWNSCALING_2_75_COEFFS = 4,
  66. MALIDP_DOWNSCALING_4_COEFFS = 5,
  67. };
  68. struct malidp_se_config {
  69. u8 scale_enable : 1;
  70. u8 enhancer_enable : 1;
  71. u8 hcoeff : 3;
  72. u8 vcoeff : 3;
  73. u8 plane_src_id;
  74. u16 input_w, input_h;
  75. u16 output_w, output_h;
  76. u32 h_init_phase, h_delta_phase;
  77. u32 v_init_phase, v_delta_phase;
  78. };
  79. /* regmap features */
  80. #define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0)
  81. #define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1)
  82. #define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2)
  83. #define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3)
  84. struct malidp_hw_regmap {
  85. /* address offset of the DE register bank */
  86. /* is always 0x0000 */
  87. /* address offset of the DE coefficients registers */
  88. const u16 coeffs_base;
  89. /* address offset of the SE registers bank */
  90. const u16 se_base;
  91. /* address offset of the DC registers bank */
  92. const u16 dc_base;
  93. /* address offset for the output depth register */
  94. const u16 out_depth_base;
  95. /* bitmap with register map features */
  96. const u8 features;
  97. /* list of supported layers */
  98. const u8 n_layers;
  99. const struct malidp_layer *layers;
  100. const struct malidp_irq_map de_irq_map;
  101. const struct malidp_irq_map se_irq_map;
  102. const struct malidp_irq_map dc_irq_map;
  103. /* list of supported pixel formats for each layer */
  104. const struct malidp_format_id *pixel_formats;
  105. const u8 n_pixel_formats;
  106. /* pitch alignment requirement in bytes */
  107. const u8 bus_align_bytes;
  108. };
  109. /* device features */
  110. /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */
  111. #define MALIDP_DEVICE_LV_HAS_3_STRIDES BIT(0)
  112. struct malidp_hw_device;
  113. /*
  114. * Static structure containing hardware specific data and pointers to
  115. * functions that behave differently between various versions of the IP.
  116. */
  117. struct malidp_hw {
  118. const struct malidp_hw_regmap map;
  119. /*
  120. * Validate the driver instance against the hardware bits
  121. */
  122. int (*query_hw)(struct malidp_hw_device *hwdev);
  123. /*
  124. * Set the hardware into config mode, ready to accept mode changes
  125. */
  126. void (*enter_config_mode)(struct malidp_hw_device *hwdev);
  127. /*
  128. * Tell hardware to exit configuration mode
  129. */
  130. void (*leave_config_mode)(struct malidp_hw_device *hwdev);
  131. /*
  132. * Query if hardware is in configuration mode
  133. */
  134. bool (*in_config_mode)(struct malidp_hw_device *hwdev);
  135. /*
  136. * Set/clear configuration valid flag for hardware parameters that can
  137. * be changed outside the configuration mode to the given value.
  138. * Hardware will use the new settings when config valid is set,
  139. * after the end of the current buffer scanout, and will ignore
  140. * any new values for those parameters if config valid flag is cleared
  141. */
  142. void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value);
  143. /*
  144. * Set a new mode in hardware. Requires the hardware to be in
  145. * configuration mode before this function is called.
  146. */
  147. void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m);
  148. /*
  149. * Calculate the required rotation memory given the active area
  150. * and the buffer format.
  151. */
  152. int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h,
  153. u32 fmt, bool has_modifier);
  154. int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev,
  155. struct malidp_se_config *se_config,
  156. struct malidp_se_config *old_config);
  157. long (*se_calc_mclk)(struct malidp_hw_device *hwdev,
  158. struct malidp_se_config *se_config,
  159. struct videomode *vm);
  160. /*
  161. * Enable writing to memory the content of the next frame
  162. * @param hwdev - malidp_hw_device structure containing the HW description
  163. * @param addrs - array of addresses for each plane
  164. * @param pitches - array of pitches for each plane
  165. * @param num_planes - number of planes to be written
  166. * @param w - width of the output frame
  167. * @param h - height of the output frame
  168. * @param fmt_id - internal format ID of output buffer
  169. */
  170. int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs,
  171. s32 *pitches, int num_planes, u16 w, u16 h, u32 fmt_id,
  172. const s16 *rgb2yuv_coeffs);
  173. /*
  174. * Disable the writing to memory of the next frame's content.
  175. */
  176. void (*disable_memwrite)(struct malidp_hw_device *hwdev);
  177. u8 features;
  178. };
  179. /* Supported variants of the hardware */
  180. enum {
  181. MALIDP_500 = 0,
  182. MALIDP_550,
  183. MALIDP_650,
  184. /* keep the next entry last */
  185. MALIDP_MAX_DEVICES
  186. };
  187. extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES];
  188. /*
  189. * Structure used by the driver during runtime operation.
  190. */
  191. struct malidp_hw_device {
  192. struct malidp_hw *hw;
  193. void __iomem *regs;
  194. /* APB clock */
  195. struct clk *pclk;
  196. /* AXI clock */
  197. struct clk *aclk;
  198. /* main clock for display core */
  199. struct clk *mclk;
  200. /* pixel clock for display core */
  201. struct clk *pxlclk;
  202. u8 min_line_size;
  203. u16 max_line_size;
  204. u32 output_color_depth;
  205. /* track the device PM state */
  206. bool pm_suspended;
  207. /* track the SE memory writeback state */
  208. u8 mw_state;
  209. /* size of memory used for rotating layers, up to two banks available */
  210. u32 rotation_memory[2];
  211. /* priority level of RQOS register used for driven the ARQOS signal */
  212. u32 arqos_value;
  213. };
  214. static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
  215. {
  216. WARN_ON(hwdev->pm_suspended);
  217. return readl(hwdev->regs + reg);
  218. }
  219. static inline void malidp_hw_write(struct malidp_hw_device *hwdev,
  220. u32 value, u32 reg)
  221. {
  222. WARN_ON(hwdev->pm_suspended);
  223. writel(value, hwdev->regs + reg);
  224. }
  225. static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev,
  226. u32 mask, u32 reg)
  227. {
  228. u32 data = malidp_hw_read(hwdev, reg);
  229. data |= mask;
  230. malidp_hw_write(hwdev, data, reg);
  231. }
  232. static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev,
  233. u32 mask, u32 reg)
  234. {
  235. u32 data = malidp_hw_read(hwdev, reg);
  236. data &= ~mask;
  237. malidp_hw_write(hwdev, data, reg);
  238. }
  239. static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev,
  240. u8 block)
  241. {
  242. switch (block) {
  243. case MALIDP_SE_BLOCK:
  244. return hwdev->hw->map.se_base;
  245. case MALIDP_DC_BLOCK:
  246. return hwdev->hw->map.dc_base;
  247. }
  248. return 0;
  249. }
  250. static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev,
  251. u8 block, u32 irq)
  252. {
  253. u32 base = malidp_get_block_base(hwdev, block);
  254. malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
  255. }
  256. static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev,
  257. u8 block, u32 irq)
  258. {
  259. u32 base = malidp_get_block_base(hwdev, block);
  260. malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
  261. }
  262. int malidp_de_irq_init(struct drm_device *drm, int irq);
  263. void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev);
  264. void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev);
  265. void malidp_de_irq_fini(struct malidp_hw_device *hwdev);
  266. int malidp_se_irq_init(struct drm_device *drm, int irq);
  267. void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
  268. u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
  269. u8 layer_id, u32 format, bool has_modifier);
  270. int malidp_format_get_bpp(u32 fmt);
  271. static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
  272. {
  273. /*
  274. * only hardware that cannot do 8 bytes bus alignments have further
  275. * constraints on rotated planes
  276. */
  277. if (hwdev->hw->map.bus_align_bytes == 8)
  278. return 8;
  279. else
  280. return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0);
  281. }
  282. /* U16.16 */
  283. #define FP_1_00000 0x00010000 /* 1.0 */
  284. #define FP_0_66667 0x0000AAAA /* 0.6667 = 1/1.5 */
  285. #define FP_0_50000 0x00008000 /* 0.5 = 1/2 */
  286. #define FP_0_36363 0x00005D17 /* 0.36363 = 1/2.75 */
  287. #define FP_0_25000 0x00004000 /* 0.25 = 1/4 */
  288. static inline enum malidp_scaling_coeff_set
  289. malidp_se_select_coeffs(u32 upscale_factor)
  290. {
  291. return (upscale_factor >= FP_1_00000) ? MALIDP_UPSCALING_COEFFS :
  292. (upscale_factor >= FP_0_66667) ? MALIDP_DOWNSCALING_1_5_COEFFS :
  293. (upscale_factor >= FP_0_50000) ? MALIDP_DOWNSCALING_2_COEFFS :
  294. (upscale_factor >= FP_0_36363) ? MALIDP_DOWNSCALING_2_75_COEFFS :
  295. MALIDP_DOWNSCALING_4_COEFFS;
  296. }
  297. #undef FP_0_25000
  298. #undef FP_0_36363
  299. #undef FP_0_50000
  300. #undef FP_0_66667
  301. #undef FP_1_00000
  302. static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
  303. {
  304. static const s32 enhancer_coeffs[] = {
  305. -8, -8, -8, -8, 128, -8, -8, -8, -8
  306. };
  307. u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) |
  308. MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL);
  309. u32 image_enh = hwdev->hw->map.se_base +
  310. ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
  311. 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH;
  312. u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0;
  313. int i;
  314. malidp_hw_write(hwdev, val, image_enh);
  315. for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i)
  316. malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4);
  317. }
  318. /*
  319. * background color components are defined as 12bits values,
  320. * they will be shifted right when stored on hardware that
  321. * supports only 8bits per channel
  322. */
  323. #define MALIDP_BGND_COLOR_R 0x000
  324. #define MALIDP_BGND_COLOR_G 0x000
  325. #define MALIDP_BGND_COLOR_B 0x000
  326. #define MALIDP_COLORADJ_NUM_COEFFS 12
  327. #define MALIDP_COEFFTAB_NUM_COEFFS 64
  328. #define MALIDP_GAMMA_LUT_SIZE 4096
  329. #define AFBC_SIZE_MASK AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
  330. #define AFBC_SIZE_16X16 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
  331. #define AFBC_YTR AFBC_FORMAT_MOD_YTR
  332. #define AFBC_SPARSE AFBC_FORMAT_MOD_SPARSE
  333. #define AFBC_CBR AFBC_FORMAT_MOD_CBR
  334. #define AFBC_SPLIT AFBC_FORMAT_MOD_SPLIT
  335. #define AFBC_TILED AFBC_FORMAT_MOD_TILED
  336. #define AFBC_SC AFBC_FORMAT_MOD_SC
  337. #define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \
  338. AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
  339. extern const u64 malidp_format_modifiers[];
  340. #endif /* __MALIDP_HW_H__ */