malidp_hw.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  4. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  5. *
  6. * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
  7. * the difference between various versions of the hardware is being dealt with
  8. * in an attempt to provide to the rest of the driver code a unified view
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/types.h>
  13. #include <linux/io.h>
  14. #include <video/videomode.h>
  15. #include <video/display_timing.h>
  16. #include <drm/drm_fourcc.h>
  17. #include <drm/drm_vblank.h>
  18. #include <drm/drm_print.h>
  19. #include "malidp_drv.h"
  20. #include "malidp_hw.h"
  21. #include "malidp_mw.h"
  22. enum {
  23. MW_NOT_ENABLED = 0, /* SE writeback not enabled */
  24. MW_ONESHOT, /* SE in one-shot mode for writeback */
  25. MW_START, /* SE started writeback */
  26. MW_RESTART, /* SE will start another writeback after this one */
  27. MW_STOP, /* SE needs to stop after this writeback */
  28. };
  29. static const struct malidp_format_id malidp500_de_formats[] = {
  30. /* fourcc, layers supporting the format, internal id */
  31. { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 0 },
  32. { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 1 },
  33. { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 },
  34. { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 },
  35. { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 4 },
  36. { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2 | SE_MEMWRITE, 5 },
  37. { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 },
  38. { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 },
  39. { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 },
  40. { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 },
  41. { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
  42. { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
  43. { DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
  44. { DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
  45. { DRM_FORMAT_NV12, DE_VIDEO1 | SE_MEMWRITE, 14 },
  46. { DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
  47. { DRM_FORMAT_XYUV8888, DE_VIDEO1, 16 },
  48. /* These are supported with AFBC only */
  49. { DRM_FORMAT_YUV420_8BIT, DE_VIDEO1, 14 },
  50. { DRM_FORMAT_VUY888, DE_VIDEO1, 16 },
  51. { DRM_FORMAT_VUY101010, DE_VIDEO1, 17 },
  52. { DRM_FORMAT_YUV420_10BIT, DE_VIDEO1, 18 }
  53. };
  54. #define MALIDP_ID(__group, __format) \
  55. ((((__group) & 0x7) << 3) | ((__format) & 0x7))
  56. #define AFBC_YUV_422_FORMAT_ID MALIDP_ID(5, 1)
  57. #define MALIDP_COMMON_FORMATS \
  58. /* fourcc, layers supporting the format, internal id */ \
  59. { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 0) }, \
  60. { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 1) }, \
  61. { DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 2) }, \
  62. { DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 3) }, \
  63. { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
  64. { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
  65. { DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
  66. { DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
  67. { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 0) }, \
  68. { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 1) }, \
  69. { DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 2) }, \
  70. { DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART | SE_MEMWRITE, MALIDP_ID(2, 3) }, \
  71. { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(3, 0) }, \
  72. { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(3, 1) }, \
  73. { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
  74. { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
  75. { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
  76. { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
  77. /* This is only supported with linear modifier */ \
  78. { DRM_FORMAT_XYUV8888, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 0) },\
  79. /* This is only supported with AFBC modifier */ \
  80. { DRM_FORMAT_VUY888, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 0) }, \
  81. { DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \
  82. /* This is only supported with linear modifier */ \
  83. { DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \
  84. { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(5, 6) }, \
  85. /* This is only supported with AFBC modifier */ \
  86. { DRM_FORMAT_YUV420_8BIT, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
  87. { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }, \
  88. /* This is only supported with linear modifier */ \
  89. { DRM_FORMAT_XVYU2101010, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 0)}, \
  90. /* This is only supported with AFBC modifier */ \
  91. { DRM_FORMAT_VUY101010, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 0)}, \
  92. { DRM_FORMAT_X0L2, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 6)}, \
  93. /* This is only supported with AFBC modifier */ \
  94. { DRM_FORMAT_YUV420_10BIT, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 7)}, \
  95. { DRM_FORMAT_P010, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 7)}
  96. static const struct malidp_format_id malidp550_de_formats[] = {
  97. MALIDP_COMMON_FORMATS,
  98. };
  99. static const struct malidp_format_id malidp650_de_formats[] = {
  100. MALIDP_COMMON_FORMATS,
  101. { DRM_FORMAT_X0L0, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 4)},
  102. };
  103. static const struct malidp_layer malidp500_layers[] = {
  104. /* id, base address, fb pointer address base, stride offset,
  105. * yuv2rgb matrix offset, mmu control register offset, rotation_features
  106. */
  107. { DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE,
  108. MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB, 0, ROTATE_ANY,
  109. MALIDP500_DE_LV_AD_CTRL },
  110. { DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE,
  111. MALIDP_DE_LG_STRIDE, 0, 0, ROTATE_ANY,
  112. MALIDP500_DE_LG1_AD_CTRL },
  113. { DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE,
  114. MALIDP_DE_LG_STRIDE, 0, 0, ROTATE_ANY,
  115. MALIDP500_DE_LG2_AD_CTRL },
  116. };
  117. static const struct malidp_layer malidp550_layers[] = {
  118. /* id, base address, fb pointer address base, stride offset,
  119. * yuv2rgb matrix offset, mmu control register offset, rotation_features
  120. */
  121. { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE,
  122. MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB, 0, ROTATE_ANY,
  123. MALIDP550_DE_LV1_AD_CTRL },
  124. { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE,
  125. MALIDP_DE_LG_STRIDE, 0, 0, ROTATE_ANY,
  126. MALIDP550_DE_LG_AD_CTRL },
  127. { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE,
  128. MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB, 0, ROTATE_ANY,
  129. MALIDP550_DE_LV2_AD_CTRL },
  130. { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE,
  131. MALIDP550_DE_LS_R1_STRIDE, 0, 0, ROTATE_NONE, 0 },
  132. };
  133. static const struct malidp_layer malidp650_layers[] = {
  134. /* id, base address, fb pointer address base, stride offset,
  135. * yuv2rgb matrix offset, mmu control register offset,
  136. * rotation_features
  137. */
  138. { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE,
  139. MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB,
  140. MALIDP650_DE_LV_MMU_CTRL, ROTATE_ANY,
  141. MALIDP550_DE_LV1_AD_CTRL },
  142. { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE,
  143. MALIDP_DE_LG_STRIDE, 0, MALIDP650_DE_LG_MMU_CTRL,
  144. ROTATE_COMPRESSED, MALIDP550_DE_LG_AD_CTRL },
  145. { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE,
  146. MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB,
  147. MALIDP650_DE_LV_MMU_CTRL, ROTATE_ANY,
  148. MALIDP550_DE_LV2_AD_CTRL },
  149. { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE,
  150. MALIDP550_DE_LS_R1_STRIDE, 0, MALIDP650_DE_LS_MMU_CTRL,
  151. ROTATE_NONE, 0 },
  152. };
  153. const u64 malidp_format_modifiers[] = {
  154. /* All RGB formats (except XRGB, RGBX, XBGR, BGRX) */
  155. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE),
  156. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR),
  157. /* All RGB formats > 16bpp (except XRGB, RGBX, XBGR, BGRX) */
  158. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE | AFBC_SPLIT),
  159. /* All 8 or 10 bit YUV 444 formats. */
  160. /* In DP550, 10 bit YUV 420 format also supported */
  161. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE | AFBC_SPLIT),
  162. /* YUV 420, 422 P1 8 bit and YUV 444 8 bit/10 bit formats */
  163. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE),
  164. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16),
  165. /* YUV 420, 422 P1 8, 10 bit formats */
  166. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR | AFBC_SPARSE),
  167. DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR),
  168. /* All formats */
  169. DRM_FORMAT_MOD_LINEAR,
  170. DRM_FORMAT_MOD_INVALID
  171. };
  172. #define SE_N_SCALING_COEFFS 96
  173. static const u16 dp500_se_scaling_coeffs[][SE_N_SCALING_COEFFS] = {
  174. [MALIDP_UPSCALING_COEFFS - 1] = {
  175. 0x0000, 0x0001, 0x0007, 0x0011, 0x001e, 0x002e, 0x003f, 0x0052,
  176. 0x0064, 0x0073, 0x007d, 0x0080, 0x007a, 0x006c, 0x0053, 0x002f,
  177. 0x0000, 0x3fc6, 0x3f83, 0x3f39, 0x3eea, 0x3e9b, 0x3e4f, 0x3e0a,
  178. 0x3dd4, 0x3db0, 0x3da2, 0x3db1, 0x3dde, 0x3e2f, 0x3ea5, 0x3f40,
  179. 0x0000, 0x00e5, 0x01ee, 0x0315, 0x0456, 0x05aa, 0x0709, 0x086c,
  180. 0x09c9, 0x0b15, 0x0c4a, 0x0d5d, 0x0e4a, 0x0f06, 0x0f91, 0x0fe5,
  181. 0x1000, 0x0fe5, 0x0f91, 0x0f06, 0x0e4a, 0x0d5d, 0x0c4a, 0x0b15,
  182. 0x09c9, 0x086c, 0x0709, 0x05aa, 0x0456, 0x0315, 0x01ee, 0x00e5,
  183. 0x0000, 0x3f40, 0x3ea5, 0x3e2f, 0x3dde, 0x3db1, 0x3da2, 0x3db0,
  184. 0x3dd4, 0x3e0a, 0x3e4f, 0x3e9b, 0x3eea, 0x3f39, 0x3f83, 0x3fc6,
  185. 0x0000, 0x002f, 0x0053, 0x006c, 0x007a, 0x0080, 0x007d, 0x0073,
  186. 0x0064, 0x0052, 0x003f, 0x002e, 0x001e, 0x0011, 0x0007, 0x0001
  187. },
  188. [MALIDP_DOWNSCALING_1_5_COEFFS - 1] = {
  189. 0x0059, 0x004f, 0x0041, 0x002e, 0x0016, 0x3ffb, 0x3fd9, 0x3fb4,
  190. 0x3f8c, 0x3f62, 0x3f36, 0x3f09, 0x3edd, 0x3eb3, 0x3e8d, 0x3e6c,
  191. 0x3e52, 0x3e3f, 0x3e35, 0x3e37, 0x3e46, 0x3e61, 0x3e8c, 0x3ec5,
  192. 0x3f0f, 0x3f68, 0x3fd1, 0x004a, 0x00d3, 0x0169, 0x020b, 0x02b8,
  193. 0x036e, 0x042d, 0x04f2, 0x05b9, 0x0681, 0x0745, 0x0803, 0x08ba,
  194. 0x0965, 0x0a03, 0x0a91, 0x0b0d, 0x0b75, 0x0bc6, 0x0c00, 0x0c20,
  195. 0x0c28, 0x0c20, 0x0c00, 0x0bc6, 0x0b75, 0x0b0d, 0x0a91, 0x0a03,
  196. 0x0965, 0x08ba, 0x0803, 0x0745, 0x0681, 0x05b9, 0x04f2, 0x042d,
  197. 0x036e, 0x02b8, 0x020b, 0x0169, 0x00d3, 0x004a, 0x3fd1, 0x3f68,
  198. 0x3f0f, 0x3ec5, 0x3e8c, 0x3e61, 0x3e46, 0x3e37, 0x3e35, 0x3e3f,
  199. 0x3e52, 0x3e6c, 0x3e8d, 0x3eb3, 0x3edd, 0x3f09, 0x3f36, 0x3f62,
  200. 0x3f8c, 0x3fb4, 0x3fd9, 0x3ffb, 0x0016, 0x002e, 0x0041, 0x004f
  201. },
  202. [MALIDP_DOWNSCALING_2_COEFFS - 1] = {
  203. 0x3f19, 0x3f03, 0x3ef0, 0x3edf, 0x3ed0, 0x3ec5, 0x3ebd, 0x3eb9,
  204. 0x3eb9, 0x3ebf, 0x3eca, 0x3ed9, 0x3eef, 0x3f0a, 0x3f2c, 0x3f52,
  205. 0x3f7f, 0x3fb0, 0x3fe8, 0x0026, 0x006a, 0x00b4, 0x0103, 0x0158,
  206. 0x01b1, 0x020d, 0x026c, 0x02cd, 0x032f, 0x0392, 0x03f4, 0x0455,
  207. 0x04b4, 0x051e, 0x0585, 0x05eb, 0x064c, 0x06a8, 0x06fe, 0x074e,
  208. 0x0796, 0x07d5, 0x080c, 0x0839, 0x085c, 0x0875, 0x0882, 0x0887,
  209. 0x0881, 0x0887, 0x0882, 0x0875, 0x085c, 0x0839, 0x080c, 0x07d5,
  210. 0x0796, 0x074e, 0x06fe, 0x06a8, 0x064c, 0x05eb, 0x0585, 0x051e,
  211. 0x04b4, 0x0455, 0x03f4, 0x0392, 0x032f, 0x02cd, 0x026c, 0x020d,
  212. 0x01b1, 0x0158, 0x0103, 0x00b4, 0x006a, 0x0026, 0x3fe8, 0x3fb0,
  213. 0x3f7f, 0x3f52, 0x3f2c, 0x3f0a, 0x3eef, 0x3ed9, 0x3eca, 0x3ebf,
  214. 0x3eb9, 0x3eb9, 0x3ebd, 0x3ec5, 0x3ed0, 0x3edf, 0x3ef0, 0x3f03
  215. },
  216. [MALIDP_DOWNSCALING_2_75_COEFFS - 1] = {
  217. 0x3f51, 0x3f60, 0x3f71, 0x3f84, 0x3f98, 0x3faf, 0x3fc8, 0x3fe3,
  218. 0x0000, 0x001f, 0x0040, 0x0064, 0x008a, 0x00b1, 0x00da, 0x0106,
  219. 0x0133, 0x0160, 0x018e, 0x01bd, 0x01ec, 0x021d, 0x024e, 0x0280,
  220. 0x02b2, 0x02e4, 0x0317, 0x0349, 0x037c, 0x03ad, 0x03df, 0x0410,
  221. 0x0440, 0x0468, 0x048f, 0x04b3, 0x04d6, 0x04f8, 0x0516, 0x0533,
  222. 0x054e, 0x0566, 0x057c, 0x0590, 0x05a0, 0x05ae, 0x05ba, 0x05c3,
  223. 0x05c9, 0x05c3, 0x05ba, 0x05ae, 0x05a0, 0x0590, 0x057c, 0x0566,
  224. 0x054e, 0x0533, 0x0516, 0x04f8, 0x04d6, 0x04b3, 0x048f, 0x0468,
  225. 0x0440, 0x0410, 0x03df, 0x03ad, 0x037c, 0x0349, 0x0317, 0x02e4,
  226. 0x02b2, 0x0280, 0x024e, 0x021d, 0x01ec, 0x01bd, 0x018e, 0x0160,
  227. 0x0133, 0x0106, 0x00da, 0x00b1, 0x008a, 0x0064, 0x0040, 0x001f,
  228. 0x0000, 0x3fe3, 0x3fc8, 0x3faf, 0x3f98, 0x3f84, 0x3f71, 0x3f60
  229. },
  230. [MALIDP_DOWNSCALING_4_COEFFS - 1] = {
  231. 0x0094, 0x00a9, 0x00be, 0x00d4, 0x00ea, 0x0101, 0x0118, 0x012f,
  232. 0x0148, 0x0160, 0x017a, 0x0193, 0x01ae, 0x01c8, 0x01e4, 0x01ff,
  233. 0x021c, 0x0233, 0x024a, 0x0261, 0x0278, 0x028f, 0x02a6, 0x02bd,
  234. 0x02d4, 0x02eb, 0x0302, 0x0319, 0x032f, 0x0346, 0x035d, 0x0374,
  235. 0x038a, 0x0397, 0x03a3, 0x03af, 0x03bb, 0x03c6, 0x03d1, 0x03db,
  236. 0x03e4, 0x03ed, 0x03f6, 0x03fe, 0x0406, 0x040d, 0x0414, 0x041a,
  237. 0x0420, 0x041a, 0x0414, 0x040d, 0x0406, 0x03fe, 0x03f6, 0x03ed,
  238. 0x03e4, 0x03db, 0x03d1, 0x03c6, 0x03bb, 0x03af, 0x03a3, 0x0397,
  239. 0x038a, 0x0374, 0x035d, 0x0346, 0x032f, 0x0319, 0x0302, 0x02eb,
  240. 0x02d4, 0x02bd, 0x02a6, 0x028f, 0x0278, 0x0261, 0x024a, 0x0233,
  241. 0x021c, 0x01ff, 0x01e4, 0x01c8, 0x01ae, 0x0193, 0x017a, 0x0160,
  242. 0x0148, 0x012f, 0x0118, 0x0101, 0x00ea, 0x00d4, 0x00be, 0x00a9
  243. },
  244. };
  245. #define MALIDP_DE_DEFAULT_PREFETCH_START 5
  246. static int malidp500_query_hw(struct malidp_hw_device *hwdev)
  247. {
  248. u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
  249. /* bit 4 of the CONFIG_ID register holds the line size multiplier */
  250. u8 ln_size_mult = conf & 0x10 ? 2 : 1;
  251. hwdev->min_line_size = 2;
  252. hwdev->max_line_size = SZ_2K * ln_size_mult;
  253. hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
  254. hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
  255. return 0;
  256. }
  257. static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
  258. {
  259. u32 status, count = 100;
  260. malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
  261. while (count) {
  262. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  263. if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
  264. break;
  265. /*
  266. * entering config mode can take as long as the rendering
  267. * of a full frame, hence the long sleep here
  268. */
  269. usleep_range(1000, 10000);
  270. count--;
  271. }
  272. WARN(count == 0, "timeout while entering config mode");
  273. }
  274. static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
  275. {
  276. u32 status, count = 100;
  277. malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
  278. malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
  279. while (count) {
  280. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  281. if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
  282. break;
  283. usleep_range(100, 1000);
  284. count--;
  285. }
  286. WARN(count == 0, "timeout while leaving config mode");
  287. }
  288. static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
  289. {
  290. u32 status;
  291. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  292. if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
  293. return true;
  294. return false;
  295. }
  296. static void malidp500_set_config_valid(struct malidp_hw_device *hwdev, u8 value)
  297. {
  298. if (value)
  299. malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
  300. else
  301. malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
  302. }
  303. static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
  304. {
  305. u32 val = 0;
  306. malidp_hw_write(hwdev, hwdev->output_color_depth,
  307. hwdev->hw->map.out_depth_base);
  308. malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
  309. if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  310. val |= MALIDP500_HSYNCPOL;
  311. if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  312. val |= MALIDP500_VSYNCPOL;
  313. val |= MALIDP_DE_DEFAULT_PREFETCH_START;
  314. malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
  315. /*
  316. * Mali-DP500 encodes the background color like this:
  317. * - red @ MALIDP500_BGND_COLOR[12:0]
  318. * - green @ MALIDP500_BGND_COLOR[27:16]
  319. * - blue @ (MALIDP500_BGND_COLOR + 4)[12:0]
  320. */
  321. val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
  322. (MALIDP_BGND_COLOR_R & 0xfff);
  323. malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
  324. malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
  325. val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
  326. MALIDP_DE_H_BACKPORCH(mode->hback_porch);
  327. malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
  328. val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
  329. MALIDP_DE_V_BACKPORCH(mode->vback_porch);
  330. malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
  331. val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
  332. MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
  333. malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
  334. val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
  335. malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
  336. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  337. malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  338. else
  339. malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  340. /*
  341. * Program the RQoS register to avoid high resolutions flicker
  342. * issue on the LS1028A.
  343. */
  344. if (hwdev->arqos_value) {
  345. val = hwdev->arqos_value;
  346. malidp_hw_setbits(hwdev, val, MALIDP500_RQOS_QUALITY);
  347. }
  348. }
  349. int malidp_format_get_bpp(u32 fmt)
  350. {
  351. const struct drm_format_info *info = drm_format_info(fmt);
  352. int bpp = info->cpp[0] * 8;
  353. if (bpp == 0) {
  354. switch (fmt) {
  355. case DRM_FORMAT_VUY101010:
  356. bpp = 30;
  357. break;
  358. case DRM_FORMAT_YUV420_10BIT:
  359. bpp = 15;
  360. break;
  361. case DRM_FORMAT_YUV420_8BIT:
  362. bpp = 12;
  363. break;
  364. default:
  365. bpp = 0;
  366. }
  367. }
  368. return bpp;
  369. }
  370. static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
  371. u16 h, u32 fmt, bool has_modifier)
  372. {
  373. /*
  374. * Each layer needs enough rotation memory to fit 8 lines
  375. * worth of pixel data. Required size is then:
  376. * size = rotated_width * (bpp / 8) * 8;
  377. */
  378. int bpp = malidp_format_get_bpp(fmt);
  379. return w * bpp;
  380. }
  381. static void malidp500_se_write_pp_coefftab(struct malidp_hw_device *hwdev,
  382. u32 direction,
  383. u16 addr,
  384. u8 coeffs_id)
  385. {
  386. int i;
  387. u16 scaling_control = MALIDP500_SE_CONTROL + MALIDP_SE_SCALING_CONTROL;
  388. malidp_hw_write(hwdev,
  389. direction | (addr & MALIDP_SE_COEFFTAB_ADDR_MASK),
  390. scaling_control + MALIDP_SE_COEFFTAB_ADDR);
  391. for (i = 0; i < ARRAY_SIZE(dp500_se_scaling_coeffs); ++i)
  392. malidp_hw_write(hwdev, MALIDP_SE_SET_COEFFTAB_DATA(
  393. dp500_se_scaling_coeffs[coeffs_id][i]),
  394. scaling_control + MALIDP_SE_COEFFTAB_DATA);
  395. }
  396. static int malidp500_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
  397. struct malidp_se_config *se_config,
  398. struct malidp_se_config *old_config)
  399. {
  400. /* Get array indices into dp500_se_scaling_coeffs. */
  401. u8 h = (u8)se_config->hcoeff - 1;
  402. u8 v = (u8)se_config->vcoeff - 1;
  403. if (WARN_ON(h >= ARRAY_SIZE(dp500_se_scaling_coeffs) ||
  404. v >= ARRAY_SIZE(dp500_se_scaling_coeffs)))
  405. return -EINVAL;
  406. if ((h == v) && (se_config->hcoeff != old_config->hcoeff ||
  407. se_config->vcoeff != old_config->vcoeff)) {
  408. malidp500_se_write_pp_coefftab(hwdev,
  409. (MALIDP_SE_V_COEFFTAB |
  410. MALIDP_SE_H_COEFFTAB),
  411. 0, v);
  412. } else {
  413. if (se_config->vcoeff != old_config->vcoeff)
  414. malidp500_se_write_pp_coefftab(hwdev,
  415. MALIDP_SE_V_COEFFTAB,
  416. 0, v);
  417. if (se_config->hcoeff != old_config->hcoeff)
  418. malidp500_se_write_pp_coefftab(hwdev,
  419. MALIDP_SE_H_COEFFTAB,
  420. 0, h);
  421. }
  422. return 0;
  423. }
  424. static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev,
  425. struct malidp_se_config *se_config,
  426. struct videomode *vm)
  427. {
  428. unsigned long mclk;
  429. unsigned long pxlclk = vm->pixelclock; /* Hz */
  430. unsigned long htotal = vm->hactive + vm->hfront_porch +
  431. vm->hback_porch + vm->hsync_len;
  432. unsigned long input_size = se_config->input_w * se_config->input_h;
  433. unsigned long a = 10;
  434. long ret;
  435. /*
  436. * mclk = max(a, 1.5) * pxlclk
  437. *
  438. * To avoid float calculaiton, using 15 instead of 1.5 and div by
  439. * 10 to get mclk.
  440. */
  441. if (se_config->scale_enable) {
  442. a = 15 * input_size / (htotal * se_config->output_h);
  443. if (a < 15)
  444. a = 15;
  445. }
  446. mclk = a * pxlclk / 10;
  447. ret = clk_get_rate(hwdev->mclk);
  448. if (ret < mclk) {
  449. DRM_DEBUG_DRIVER("mclk requirement of %lu kHz can't be met.\n",
  450. mclk / 1000);
  451. return -EINVAL;
  452. }
  453. return ret;
  454. }
  455. static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev,
  456. dma_addr_t *addrs, s32 *pitches,
  457. int num_planes, u16 w, u16 h, u32 fmt_id,
  458. const s16 *rgb2yuv_coeffs)
  459. {
  460. u32 base = MALIDP500_SE_MEMWRITE_BASE;
  461. u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
  462. /* enable the scaling engine block */
  463. malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC);
  464. /* restart the writeback if already enabled */
  465. if (hwdev->mw_state != MW_NOT_ENABLED)
  466. hwdev->mw_state = MW_RESTART;
  467. else
  468. hwdev->mw_state = MW_START;
  469. malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT);
  470. switch (num_planes) {
  471. case 2:
  472. malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
  473. malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
  474. malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
  475. fallthrough;
  476. case 1:
  477. malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
  478. malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
  479. malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE);
  480. break;
  481. default:
  482. WARN(1, "Invalid number of planes");
  483. }
  484. malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h),
  485. MALIDP500_SE_MEMWRITE_OUT_SIZE);
  486. if (rgb2yuv_coeffs) {
  487. int i;
  488. for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
  489. malidp_hw_write(hwdev, rgb2yuv_coeffs[i],
  490. MALIDP500_SE_RGB_YUV_COEFFS + i * 4);
  491. }
  492. }
  493. malidp_hw_setbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL);
  494. return 0;
  495. }
  496. static void malidp500_disable_memwrite(struct malidp_hw_device *hwdev)
  497. {
  498. u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
  499. if (hwdev->mw_state == MW_START || hwdev->mw_state == MW_RESTART)
  500. hwdev->mw_state = MW_STOP;
  501. malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL);
  502. malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC);
  503. }
  504. static int malidp550_query_hw(struct malidp_hw_device *hwdev)
  505. {
  506. u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
  507. u8 ln_size = (conf >> 4) & 0x3, rsize;
  508. hwdev->min_line_size = 2;
  509. switch (ln_size) {
  510. case 0:
  511. hwdev->max_line_size = SZ_2K;
  512. /* two banks of 64KB for rotation memory */
  513. rsize = 64;
  514. break;
  515. case 1:
  516. hwdev->max_line_size = SZ_4K;
  517. /* two banks of 128KB for rotation memory */
  518. rsize = 128;
  519. break;
  520. case 2:
  521. hwdev->max_line_size = 1280;
  522. /* two banks of 40KB for rotation memory */
  523. rsize = 40;
  524. break;
  525. case 3:
  526. /* reserved value */
  527. hwdev->max_line_size = 0;
  528. return -EINVAL;
  529. }
  530. hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
  531. return 0;
  532. }
  533. static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
  534. {
  535. u32 status, count = 100;
  536. malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
  537. while (count) {
  538. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  539. if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
  540. break;
  541. /*
  542. * entering config mode can take as long as the rendering
  543. * of a full frame, hence the long sleep here
  544. */
  545. usleep_range(1000, 10000);
  546. count--;
  547. }
  548. WARN(count == 0, "timeout while entering config mode");
  549. }
  550. static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
  551. {
  552. u32 status, count = 100;
  553. malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
  554. malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
  555. while (count) {
  556. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  557. if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
  558. break;
  559. usleep_range(100, 1000);
  560. count--;
  561. }
  562. WARN(count == 0, "timeout while leaving config mode");
  563. }
  564. static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
  565. {
  566. u32 status;
  567. status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
  568. if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
  569. return true;
  570. return false;
  571. }
  572. static void malidp550_set_config_valid(struct malidp_hw_device *hwdev, u8 value)
  573. {
  574. if (value)
  575. malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
  576. else
  577. malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
  578. }
  579. static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
  580. {
  581. u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
  582. malidp_hw_write(hwdev, hwdev->output_color_depth,
  583. hwdev->hw->map.out_depth_base);
  584. malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
  585. /*
  586. * Mali-DP550 and Mali-DP650 encode the background color like this:
  587. * - red @ MALIDP550_DE_BGND_COLOR[23:16]
  588. * - green @ MALIDP550_DE_BGND_COLOR[15:8]
  589. * - blue @ MALIDP550_DE_BGND_COLOR[7:0]
  590. *
  591. * We need to truncate the least significant 4 bits from the default
  592. * MALIDP_BGND_COLOR_x values
  593. */
  594. val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
  595. (((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
  596. ((MALIDP_BGND_COLOR_B >> 4) & 0xff);
  597. malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
  598. val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
  599. MALIDP_DE_H_BACKPORCH(mode->hback_porch);
  600. malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
  601. val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
  602. MALIDP_DE_V_BACKPORCH(mode->vback_porch);
  603. malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
  604. val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
  605. MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
  606. if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  607. val |= MALIDP550_HSYNCPOL;
  608. if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  609. val |= MALIDP550_VSYNCPOL;
  610. malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
  611. val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
  612. malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
  613. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  614. malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  615. else
  616. malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  617. }
  618. static int malidpx50_get_bytes_per_column(u32 fmt)
  619. {
  620. u32 bytes_per_column;
  621. switch (fmt) {
  622. /* 8 lines at 4 bytes per pixel */
  623. case DRM_FORMAT_ARGB2101010:
  624. case DRM_FORMAT_ABGR2101010:
  625. case DRM_FORMAT_RGBA1010102:
  626. case DRM_FORMAT_BGRA1010102:
  627. case DRM_FORMAT_ARGB8888:
  628. case DRM_FORMAT_ABGR8888:
  629. case DRM_FORMAT_RGBA8888:
  630. case DRM_FORMAT_BGRA8888:
  631. case DRM_FORMAT_XRGB8888:
  632. case DRM_FORMAT_XBGR8888:
  633. case DRM_FORMAT_RGBX8888:
  634. case DRM_FORMAT_BGRX8888:
  635. case DRM_FORMAT_RGB888:
  636. case DRM_FORMAT_BGR888:
  637. /* 16 lines at 2 bytes per pixel */
  638. case DRM_FORMAT_RGBA5551:
  639. case DRM_FORMAT_ABGR1555:
  640. case DRM_FORMAT_RGB565:
  641. case DRM_FORMAT_BGR565:
  642. case DRM_FORMAT_UYVY:
  643. case DRM_FORMAT_YUYV:
  644. case DRM_FORMAT_X0L0:
  645. bytes_per_column = 32;
  646. break;
  647. /* 16 lines at 1.5 bytes per pixel */
  648. case DRM_FORMAT_NV12:
  649. case DRM_FORMAT_YUV420:
  650. /* 8 lines at 3 bytes per pixel */
  651. case DRM_FORMAT_VUY888:
  652. /* 16 lines at 12 bits per pixel */
  653. case DRM_FORMAT_YUV420_8BIT:
  654. /* 8 lines at 3 bytes per pixel */
  655. case DRM_FORMAT_P010:
  656. bytes_per_column = 24;
  657. break;
  658. /* 8 lines at 30 bits per pixel */
  659. case DRM_FORMAT_VUY101010:
  660. /* 16 lines at 15 bits per pixel */
  661. case DRM_FORMAT_YUV420_10BIT:
  662. bytes_per_column = 30;
  663. break;
  664. default:
  665. return -EINVAL;
  666. }
  667. return bytes_per_column;
  668. }
  669. static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
  670. u16 h, u32 fmt, bool has_modifier)
  671. {
  672. int bytes_per_column = 0;
  673. switch (fmt) {
  674. /* 8 lines at 15 bits per pixel */
  675. case DRM_FORMAT_YUV420_10BIT:
  676. bytes_per_column = 15;
  677. break;
  678. /* Uncompressed YUV 420 10 bit single plane cannot be rotated */
  679. case DRM_FORMAT_X0L2:
  680. if (has_modifier)
  681. bytes_per_column = 8;
  682. else
  683. return -EINVAL;
  684. break;
  685. default:
  686. bytes_per_column = malidpx50_get_bytes_per_column(fmt);
  687. }
  688. if (bytes_per_column == -EINVAL)
  689. return bytes_per_column;
  690. return w * bytes_per_column;
  691. }
  692. static int malidp650_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
  693. u16 h, u32 fmt, bool has_modifier)
  694. {
  695. int bytes_per_column = 0;
  696. switch (fmt) {
  697. /* 16 lines at 2 bytes per pixel */
  698. case DRM_FORMAT_X0L2:
  699. bytes_per_column = 32;
  700. break;
  701. default:
  702. bytes_per_column = malidpx50_get_bytes_per_column(fmt);
  703. }
  704. if (bytes_per_column == -EINVAL)
  705. return bytes_per_column;
  706. return w * bytes_per_column;
  707. }
  708. static int malidp550_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
  709. struct malidp_se_config *se_config,
  710. struct malidp_se_config *old_config)
  711. {
  712. u32 mask = MALIDP550_SE_CTL_VCSEL(MALIDP550_SE_CTL_SEL_MASK) |
  713. MALIDP550_SE_CTL_HCSEL(MALIDP550_SE_CTL_SEL_MASK);
  714. u32 new_value = MALIDP550_SE_CTL_VCSEL(se_config->vcoeff) |
  715. MALIDP550_SE_CTL_HCSEL(se_config->hcoeff);
  716. malidp_hw_clearbits(hwdev, mask, MALIDP550_SE_CONTROL);
  717. malidp_hw_setbits(hwdev, new_value, MALIDP550_SE_CONTROL);
  718. return 0;
  719. }
  720. static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev,
  721. struct malidp_se_config *se_config,
  722. struct videomode *vm)
  723. {
  724. unsigned long mclk;
  725. unsigned long pxlclk = vm->pixelclock;
  726. unsigned long htotal = vm->hactive + vm->hfront_porch +
  727. vm->hback_porch + vm->hsync_len;
  728. unsigned long numerator = 1, denominator = 1;
  729. long ret;
  730. if (se_config->scale_enable) {
  731. numerator = max(se_config->input_w, se_config->output_w) *
  732. se_config->input_h;
  733. numerator += se_config->output_w *
  734. (se_config->output_h -
  735. min(se_config->input_h, se_config->output_h));
  736. denominator = (htotal - 2) * se_config->output_h;
  737. }
  738. /* mclk can't be slower than pxlclk. */
  739. if (numerator < denominator)
  740. numerator = denominator = 1;
  741. mclk = (pxlclk * numerator) / denominator;
  742. ret = clk_get_rate(hwdev->mclk);
  743. if (ret < mclk) {
  744. DRM_DEBUG_DRIVER("mclk requirement of %lu kHz can't be met.\n",
  745. mclk / 1000);
  746. return -EINVAL;
  747. }
  748. return ret;
  749. }
  750. static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev,
  751. dma_addr_t *addrs, s32 *pitches,
  752. int num_planes, u16 w, u16 h, u32 fmt_id,
  753. const s16 *rgb2yuv_coeffs)
  754. {
  755. u32 base = MALIDP550_SE_MEMWRITE_BASE;
  756. u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
  757. /* enable the scaling engine block */
  758. malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC);
  759. hwdev->mw_state = MW_ONESHOT;
  760. malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT);
  761. switch (num_planes) {
  762. case 2:
  763. malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
  764. malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
  765. malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
  766. fallthrough;
  767. case 1:
  768. malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
  769. malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
  770. malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE);
  771. break;
  772. default:
  773. WARN(1, "Invalid number of planes");
  774. }
  775. malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h),
  776. MALIDP550_SE_MEMWRITE_OUT_SIZE);
  777. malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN,
  778. MALIDP550_SE_CONTROL);
  779. if (rgb2yuv_coeffs) {
  780. int i;
  781. for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
  782. malidp_hw_write(hwdev, rgb2yuv_coeffs[i],
  783. MALIDP550_SE_RGB_YUV_COEFFS + i * 4);
  784. }
  785. }
  786. return 0;
  787. }
  788. static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev)
  789. {
  790. u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
  791. malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN,
  792. MALIDP550_SE_CONTROL);
  793. malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC);
  794. }
  795. static int malidp650_query_hw(struct malidp_hw_device *hwdev)
  796. {
  797. u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
  798. u8 ln_size = (conf >> 4) & 0x3, rsize;
  799. hwdev->min_line_size = 4;
  800. switch (ln_size) {
  801. case 0:
  802. case 2:
  803. /* reserved values */
  804. hwdev->max_line_size = 0;
  805. return -EINVAL;
  806. case 1:
  807. hwdev->max_line_size = SZ_4K;
  808. /* two banks of 128KB for rotation memory */
  809. rsize = 128;
  810. break;
  811. case 3:
  812. hwdev->max_line_size = 2560;
  813. /* two banks of 80KB for rotation memory */
  814. rsize = 80;
  815. }
  816. hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
  817. return 0;
  818. }
  819. const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
  820. [MALIDP_500] = {
  821. .map = {
  822. .coeffs_base = MALIDP500_COEFFS_BASE,
  823. .se_base = MALIDP500_SE_BASE,
  824. .dc_base = MALIDP500_DC_BASE,
  825. .out_depth_base = MALIDP500_OUTPUT_DEPTH,
  826. .features = 0, /* no CLEARIRQ register */
  827. .n_layers = ARRAY_SIZE(malidp500_layers),
  828. .layers = malidp500_layers,
  829. .de_irq_map = {
  830. .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
  831. MALIDP500_DE_IRQ_AXI_ERR |
  832. MALIDP500_DE_IRQ_VSYNC |
  833. MALIDP500_DE_IRQ_GLOBAL,
  834. .vsync_irq = MALIDP500_DE_IRQ_VSYNC,
  835. .err_mask = MALIDP_DE_IRQ_UNDERRUN |
  836. MALIDP500_DE_IRQ_AXI_ERR |
  837. MALIDP500_DE_IRQ_SATURATION,
  838. },
  839. .se_irq_map = {
  840. .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
  841. MALIDP500_SE_IRQ_CONF_VALID |
  842. MALIDP500_SE_IRQ_GLOBAL,
  843. .vsync_irq = MALIDP500_SE_IRQ_CONF_VALID,
  844. .err_mask = MALIDP500_SE_IRQ_INIT_BUSY |
  845. MALIDP500_SE_IRQ_AXI_ERROR |
  846. MALIDP500_SE_IRQ_OVERRUN,
  847. },
  848. .dc_irq_map = {
  849. .irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
  850. .vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
  851. },
  852. .pixel_formats = malidp500_de_formats,
  853. .n_pixel_formats = ARRAY_SIZE(malidp500_de_formats),
  854. .bus_align_bytes = 8,
  855. },
  856. .query_hw = malidp500_query_hw,
  857. .enter_config_mode = malidp500_enter_config_mode,
  858. .leave_config_mode = malidp500_leave_config_mode,
  859. .in_config_mode = malidp500_in_config_mode,
  860. .set_config_valid = malidp500_set_config_valid,
  861. .modeset = malidp500_modeset,
  862. .rotmem_required = malidp500_rotmem_required,
  863. .se_set_scaling_coeffs = malidp500_se_set_scaling_coeffs,
  864. .se_calc_mclk = malidp500_se_calc_mclk,
  865. .enable_memwrite = malidp500_enable_memwrite,
  866. .disable_memwrite = malidp500_disable_memwrite,
  867. .features = MALIDP_DEVICE_LV_HAS_3_STRIDES,
  868. },
  869. [MALIDP_550] = {
  870. .map = {
  871. .coeffs_base = MALIDP550_COEFFS_BASE,
  872. .se_base = MALIDP550_SE_BASE,
  873. .dc_base = MALIDP550_DC_BASE,
  874. .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
  875. .features = MALIDP_REGMAP_HAS_CLEARIRQ |
  876. MALIDP_DEVICE_AFBC_SUPPORT_SPLIT |
  877. MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT |
  878. MALIDP_DEVICE_AFBC_YUYV_USE_422_P2,
  879. .n_layers = ARRAY_SIZE(malidp550_layers),
  880. .layers = malidp550_layers,
  881. .de_irq_map = {
  882. .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
  883. MALIDP550_DE_IRQ_VSYNC,
  884. .vsync_irq = MALIDP550_DE_IRQ_VSYNC,
  885. .err_mask = MALIDP_DE_IRQ_UNDERRUN |
  886. MALIDP550_DE_IRQ_SATURATION |
  887. MALIDP550_DE_IRQ_AXI_ERR,
  888. },
  889. .se_irq_map = {
  890. .irq_mask = MALIDP550_SE_IRQ_EOW,
  891. .vsync_irq = MALIDP550_SE_IRQ_EOW,
  892. .err_mask = MALIDP550_SE_IRQ_AXI_ERR |
  893. MALIDP550_SE_IRQ_OVR |
  894. MALIDP550_SE_IRQ_IBSY,
  895. },
  896. .dc_irq_map = {
  897. .irq_mask = MALIDP550_DC_IRQ_CONF_VALID |
  898. MALIDP550_DC_IRQ_SE,
  899. .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
  900. },
  901. .pixel_formats = malidp550_de_formats,
  902. .n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),
  903. .bus_align_bytes = 8,
  904. },
  905. .query_hw = malidp550_query_hw,
  906. .enter_config_mode = malidp550_enter_config_mode,
  907. .leave_config_mode = malidp550_leave_config_mode,
  908. .in_config_mode = malidp550_in_config_mode,
  909. .set_config_valid = malidp550_set_config_valid,
  910. .modeset = malidp550_modeset,
  911. .rotmem_required = malidp550_rotmem_required,
  912. .se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs,
  913. .se_calc_mclk = malidp550_se_calc_mclk,
  914. .enable_memwrite = malidp550_enable_memwrite,
  915. .disable_memwrite = malidp550_disable_memwrite,
  916. .features = 0,
  917. },
  918. [MALIDP_650] = {
  919. .map = {
  920. .coeffs_base = MALIDP550_COEFFS_BASE,
  921. .se_base = MALIDP550_SE_BASE,
  922. .dc_base = MALIDP550_DC_BASE,
  923. .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
  924. .features = MALIDP_REGMAP_HAS_CLEARIRQ |
  925. MALIDP_DEVICE_AFBC_SUPPORT_SPLIT |
  926. MALIDP_DEVICE_AFBC_YUYV_USE_422_P2,
  927. .n_layers = ARRAY_SIZE(malidp650_layers),
  928. .layers = malidp650_layers,
  929. .de_irq_map = {
  930. .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
  931. MALIDP650_DE_IRQ_DRIFT |
  932. MALIDP550_DE_IRQ_VSYNC,
  933. .vsync_irq = MALIDP550_DE_IRQ_VSYNC,
  934. .err_mask = MALIDP_DE_IRQ_UNDERRUN |
  935. MALIDP650_DE_IRQ_DRIFT |
  936. MALIDP550_DE_IRQ_SATURATION |
  937. MALIDP550_DE_IRQ_AXI_ERR |
  938. MALIDP650_DE_IRQ_ACEV1 |
  939. MALIDP650_DE_IRQ_ACEV2 |
  940. MALIDP650_DE_IRQ_ACEG |
  941. MALIDP650_DE_IRQ_AXIEP,
  942. },
  943. .se_irq_map = {
  944. .irq_mask = MALIDP550_SE_IRQ_EOW,
  945. .vsync_irq = MALIDP550_SE_IRQ_EOW,
  946. .err_mask = MALIDP550_SE_IRQ_AXI_ERR |
  947. MALIDP550_SE_IRQ_OVR |
  948. MALIDP550_SE_IRQ_IBSY,
  949. },
  950. .dc_irq_map = {
  951. .irq_mask = MALIDP550_DC_IRQ_CONF_VALID |
  952. MALIDP550_DC_IRQ_SE,
  953. .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
  954. },
  955. .pixel_formats = malidp650_de_formats,
  956. .n_pixel_formats = ARRAY_SIZE(malidp650_de_formats),
  957. .bus_align_bytes = 16,
  958. },
  959. .query_hw = malidp650_query_hw,
  960. .enter_config_mode = malidp550_enter_config_mode,
  961. .leave_config_mode = malidp550_leave_config_mode,
  962. .in_config_mode = malidp550_in_config_mode,
  963. .set_config_valid = malidp550_set_config_valid,
  964. .modeset = malidp550_modeset,
  965. .rotmem_required = malidp650_rotmem_required,
  966. .se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs,
  967. .se_calc_mclk = malidp550_se_calc_mclk,
  968. .enable_memwrite = malidp550_enable_memwrite,
  969. .disable_memwrite = malidp550_disable_memwrite,
  970. .features = 0,
  971. },
  972. };
  973. u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
  974. u8 layer_id, u32 format, bool has_modifier)
  975. {
  976. unsigned int i;
  977. for (i = 0; i < map->n_pixel_formats; i++) {
  978. if (((map->pixel_formats[i].layer & layer_id) == layer_id) &&
  979. (map->pixel_formats[i].format == format)) {
  980. /*
  981. * In some DP550 and DP650, DRM_FORMAT_YUYV + AFBC modifier
  982. * is supported by a different h/w format id than
  983. * DRM_FORMAT_YUYV (only).
  984. */
  985. if (format == DRM_FORMAT_YUYV &&
  986. (has_modifier) &&
  987. (map->features & MALIDP_DEVICE_AFBC_YUYV_USE_422_P2))
  988. return AFBC_YUV_422_FORMAT_ID;
  989. else
  990. return map->pixel_formats[i].id;
  991. }
  992. }
  993. return MALIDP_INVALID_FORMAT_ID;
  994. }
  995. bool malidp_hw_format_is_linear_only(u32 format)
  996. {
  997. switch (format) {
  998. case DRM_FORMAT_ARGB2101010:
  999. case DRM_FORMAT_RGBA1010102:
  1000. case DRM_FORMAT_BGRA1010102:
  1001. case DRM_FORMAT_ARGB8888:
  1002. case DRM_FORMAT_RGBA8888:
  1003. case DRM_FORMAT_BGRA8888:
  1004. case DRM_FORMAT_XBGR8888:
  1005. case DRM_FORMAT_XRGB8888:
  1006. case DRM_FORMAT_RGBX8888:
  1007. case DRM_FORMAT_BGRX8888:
  1008. case DRM_FORMAT_RGB888:
  1009. case DRM_FORMAT_RGB565:
  1010. case DRM_FORMAT_ARGB1555:
  1011. case DRM_FORMAT_RGBA5551:
  1012. case DRM_FORMAT_BGRA5551:
  1013. case DRM_FORMAT_UYVY:
  1014. case DRM_FORMAT_XYUV8888:
  1015. case DRM_FORMAT_XVYU2101010:
  1016. case DRM_FORMAT_X0L2:
  1017. case DRM_FORMAT_X0L0:
  1018. return true;
  1019. default:
  1020. return false;
  1021. }
  1022. }
  1023. bool malidp_hw_format_is_afbc_only(u32 format)
  1024. {
  1025. switch (format) {
  1026. case DRM_FORMAT_VUY888:
  1027. case DRM_FORMAT_VUY101010:
  1028. case DRM_FORMAT_YUV420_8BIT:
  1029. case DRM_FORMAT_YUV420_10BIT:
  1030. return true;
  1031. default:
  1032. return false;
  1033. }
  1034. }
  1035. static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
  1036. {
  1037. u32 base = malidp_get_block_base(hwdev, block);
  1038. if (hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
  1039. malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
  1040. else
  1041. malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
  1042. }
  1043. static irqreturn_t malidp_de_irq(int irq, void *arg)
  1044. {
  1045. struct drm_device *drm = arg;
  1046. struct malidp_drm *malidp = drm->dev_private;
  1047. struct malidp_hw_device *hwdev;
  1048. struct malidp_hw *hw;
  1049. const struct malidp_irq_map *de;
  1050. u32 status, mask, dc_status;
  1051. irqreturn_t ret = IRQ_NONE;
  1052. hwdev = malidp->dev;
  1053. hw = hwdev->hw;
  1054. de = &hw->map.de_irq_map;
  1055. /*
  1056. * if we are suspended it is likely that we were invoked because
  1057. * we share an interrupt line with some other driver, don't try
  1058. * to read the hardware registers
  1059. */
  1060. if (hwdev->pm_suspended)
  1061. return IRQ_NONE;
  1062. /* first handle the config valid IRQ */
  1063. dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
  1064. if (dc_status & hw->map.dc_irq_map.vsync_irq) {
  1065. malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
  1066. /* do we have a page flip event? */
  1067. if (malidp->event != NULL) {
  1068. spin_lock(&drm->event_lock);
  1069. drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
  1070. malidp->event = NULL;
  1071. spin_unlock(&drm->event_lock);
  1072. }
  1073. atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
  1074. ret = IRQ_WAKE_THREAD;
  1075. }
  1076. status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
  1077. if (!(status & de->irq_mask))
  1078. return ret;
  1079. mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
  1080. /* keep the status of the enabled interrupts, plus the error bits */
  1081. status &= (mask | de->err_mask);
  1082. if ((status & de->vsync_irq) && malidp->crtc.enabled)
  1083. drm_crtc_handle_vblank(&malidp->crtc);
  1084. #ifdef CONFIG_DEBUG_FS
  1085. if (status & de->err_mask) {
  1086. malidp_error(malidp, &malidp->de_errors, status,
  1087. drm_crtc_vblank_count(&malidp->crtc));
  1088. }
  1089. #endif
  1090. malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
  1091. return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
  1092. }
  1093. static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
  1094. {
  1095. struct drm_device *drm = arg;
  1096. struct malidp_drm *malidp = drm->dev_private;
  1097. wake_up(&malidp->wq);
  1098. return IRQ_HANDLED;
  1099. }
  1100. void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev)
  1101. {
  1102. /* ensure interrupts are disabled */
  1103. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
  1104. malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
  1105. malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
  1106. malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
  1107. /* first enable the DC block IRQs */
  1108. malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
  1109. hwdev->hw->map.dc_irq_map.irq_mask);
  1110. /* now enable the DE block IRQs */
  1111. malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
  1112. hwdev->hw->map.de_irq_map.irq_mask);
  1113. }
  1114. int malidp_de_irq_init(struct drm_device *drm, int irq)
  1115. {
  1116. struct malidp_drm *malidp = drm->dev_private;
  1117. struct malidp_hw_device *hwdev = malidp->dev;
  1118. int ret;
  1119. /* ensure interrupts are disabled */
  1120. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
  1121. malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
  1122. malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
  1123. malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
  1124. ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
  1125. malidp_de_irq_thread_handler,
  1126. IRQF_SHARED, "malidp-de", drm);
  1127. if (ret < 0) {
  1128. DRM_ERROR("failed to install DE IRQ handler\n");
  1129. return ret;
  1130. }
  1131. malidp_de_irq_hw_init(hwdev);
  1132. return 0;
  1133. }
  1134. void malidp_de_irq_fini(struct malidp_hw_device *hwdev)
  1135. {
  1136. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
  1137. hwdev->hw->map.de_irq_map.irq_mask);
  1138. malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
  1139. hwdev->hw->map.dc_irq_map.irq_mask);
  1140. }
  1141. static irqreturn_t malidp_se_irq(int irq, void *arg)
  1142. {
  1143. struct drm_device *drm = arg;
  1144. struct malidp_drm *malidp = drm->dev_private;
  1145. struct malidp_hw_device *hwdev = malidp->dev;
  1146. struct malidp_hw *hw = hwdev->hw;
  1147. const struct malidp_irq_map *se = &hw->map.se_irq_map;
  1148. u32 status, mask;
  1149. /*
  1150. * if we are suspended it is likely that we were invoked because
  1151. * we share an interrupt line with some other driver, don't try
  1152. * to read the hardware registers
  1153. */
  1154. if (hwdev->pm_suspended)
  1155. return IRQ_NONE;
  1156. status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
  1157. if (!(status & (se->irq_mask | se->err_mask)))
  1158. return IRQ_NONE;
  1159. #ifdef CONFIG_DEBUG_FS
  1160. if (status & se->err_mask)
  1161. malidp_error(malidp, &malidp->se_errors, status,
  1162. drm_crtc_vblank_count(&malidp->crtc));
  1163. #endif
  1164. mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ);
  1165. status &= mask;
  1166. if (status & se->vsync_irq) {
  1167. switch (hwdev->mw_state) {
  1168. case MW_ONESHOT:
  1169. drm_writeback_signal_completion(&malidp->mw_connector, 0);
  1170. break;
  1171. case MW_STOP:
  1172. drm_writeback_signal_completion(&malidp->mw_connector, 0);
  1173. /* disable writeback after stop */
  1174. hwdev->mw_state = MW_NOT_ENABLED;
  1175. break;
  1176. case MW_RESTART:
  1177. drm_writeback_signal_completion(&malidp->mw_connector, 0);
  1178. fallthrough; /* to a new start */
  1179. case MW_START:
  1180. /* writeback started, need to emulate one-shot mode */
  1181. hw->disable_memwrite(hwdev);
  1182. /*
  1183. * only set config_valid HW bit if there is no other update
  1184. * in progress or if we raced ahead of the DE IRQ handler
  1185. * and config_valid flag will not be update until later
  1186. */
  1187. status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
  1188. if ((atomic_read(&malidp->config_valid) != MALIDP_CONFIG_START) ||
  1189. (status & hw->map.dc_irq_map.vsync_irq))
  1190. hw->set_config_valid(hwdev, 1);
  1191. break;
  1192. }
  1193. }
  1194. malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
  1195. return IRQ_HANDLED;
  1196. }
  1197. void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev)
  1198. {
  1199. /* ensure interrupts are disabled */
  1200. malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
  1201. malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
  1202. malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
  1203. hwdev->hw->map.se_irq_map.irq_mask);
  1204. }
  1205. static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
  1206. {
  1207. return IRQ_HANDLED;
  1208. }
  1209. int malidp_se_irq_init(struct drm_device *drm, int irq)
  1210. {
  1211. struct malidp_drm *malidp = drm->dev_private;
  1212. struct malidp_hw_device *hwdev = malidp->dev;
  1213. int ret;
  1214. /* ensure interrupts are disabled */
  1215. malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
  1216. malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
  1217. ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
  1218. malidp_se_irq_thread_handler,
  1219. IRQF_SHARED, "malidp-se", drm);
  1220. if (ret < 0) {
  1221. DRM_ERROR("failed to install SE IRQ handler\n");
  1222. return ret;
  1223. }
  1224. hwdev->mw_state = MW_NOT_ENABLED;
  1225. malidp_se_irq_hw_init(hwdev);
  1226. return 0;
  1227. }
  1228. void malidp_se_irq_fini(struct malidp_hw_device *hwdev)
  1229. {
  1230. malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
  1231. hwdev->hw->map.se_irq_map.irq_mask);
  1232. }