malidp_drv.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  4. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  5. *
  6. * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  7. */
  8. #include <linux/module.h>
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/of_device.h>
  12. #include <linux/of_graph.h>
  13. #include <linux/of_reserved_mem.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/debugfs.h>
  16. #include <drm/drm_atomic.h>
  17. #include <drm/drm_atomic_helper.h>
  18. #include <drm/drm_crtc.h>
  19. #include <drm/drm_drv.h>
  20. #include <drm/drm_fb_cma_helper.h>
  21. #include <drm/drm_fb_helper.h>
  22. #include <drm/drm_fourcc.h>
  23. #include <drm/drm_gem_cma_helper.h>
  24. #include <drm/drm_gem_framebuffer_helper.h>
  25. #include <drm/drm_modeset_helper.h>
  26. #include <drm/drm_of.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include <drm/drm_vblank.h>
  29. #include "malidp_drv.h"
  30. #include "malidp_mw.h"
  31. #include "malidp_regs.h"
  32. #include "malidp_hw.h"
  33. #define MALIDP_CONF_VALID_TIMEOUT 250
  34. #define AFBC_HEADER_SIZE 16
  35. #define AFBC_SUPERBLK_ALIGNMENT 128
  36. static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  37. u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  38. {
  39. int i;
  40. /* Update all channels with a single gamma curve. */
  41. const u32 gamma_write_mask = GENMASK(18, 16);
  42. /*
  43. * Always write an entire table, so the address field in
  44. * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  45. * directly.
  46. */
  47. malidp_hw_write(hwdev, gamma_write_mask,
  48. hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  49. for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  50. malidp_hw_write(hwdev, data[i],
  51. hwdev->hw->map.coeffs_base +
  52. MALIDP_COEF_TABLE_DATA);
  53. }
  54. static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  55. struct drm_crtc_state *old_state)
  56. {
  57. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  58. struct malidp_hw_device *hwdev = malidp->dev;
  59. if (!crtc->state->color_mgmt_changed)
  60. return;
  61. if (!crtc->state->gamma_lut) {
  62. malidp_hw_clearbits(hwdev,
  63. MALIDP_DISP_FUNC_GAMMA,
  64. MALIDP_DE_DISPLAY_FUNC);
  65. } else {
  66. struct malidp_crtc_state *mc =
  67. to_malidp_crtc_state(crtc->state);
  68. if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  69. old_state->gamma_lut->base.id))
  70. malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  71. malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  72. MALIDP_DE_DISPLAY_FUNC);
  73. }
  74. }
  75. static
  76. void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  77. struct drm_crtc_state *old_state)
  78. {
  79. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  80. struct malidp_hw_device *hwdev = malidp->dev;
  81. int i;
  82. if (!crtc->state->color_mgmt_changed)
  83. return;
  84. if (!crtc->state->ctm) {
  85. malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
  86. MALIDP_DE_DISPLAY_FUNC);
  87. } else {
  88. struct malidp_crtc_state *mc =
  89. to_malidp_crtc_state(crtc->state);
  90. if (!old_state->ctm || (crtc->state->ctm->base.id !=
  91. old_state->ctm->base.id))
  92. for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
  93. malidp_hw_write(hwdev,
  94. mc->coloradj_coeffs[i],
  95. hwdev->hw->map.coeffs_base +
  96. MALIDP_COLOR_ADJ_COEF + 4 * i);
  97. malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
  98. MALIDP_DE_DISPLAY_FUNC);
  99. }
  100. }
  101. static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
  102. struct drm_crtc_state *old_state)
  103. {
  104. struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
  105. struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
  106. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  107. struct malidp_hw_device *hwdev = malidp->dev;
  108. struct malidp_se_config *s = &cs->scaler_config;
  109. struct malidp_se_config *old_s = &old_cs->scaler_config;
  110. u32 se_control = hwdev->hw->map.se_base +
  111. ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
  112. 0x10 : 0xC);
  113. u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
  114. u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
  115. u32 val;
  116. /* Set SE_CONTROL */
  117. if (!s->scale_enable) {
  118. val = malidp_hw_read(hwdev, se_control);
  119. val &= ~MALIDP_SE_SCALING_EN;
  120. malidp_hw_write(hwdev, val, se_control);
  121. return;
  122. }
  123. hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
  124. val = malidp_hw_read(hwdev, se_control);
  125. val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
  126. val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
  127. val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
  128. val |= MALIDP_SE_RGBO_IF_EN;
  129. malidp_hw_write(hwdev, val, se_control);
  130. /* Set IN_SIZE & OUT_SIZE. */
  131. val = MALIDP_SE_SET_V_SIZE(s->input_h) |
  132. MALIDP_SE_SET_H_SIZE(s->input_w);
  133. malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
  134. val = MALIDP_SE_SET_V_SIZE(s->output_h) |
  135. MALIDP_SE_SET_H_SIZE(s->output_w);
  136. malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
  137. /* Set phase regs. */
  138. malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
  139. malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
  140. malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
  141. malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
  142. }
  143. /*
  144. * set the "config valid" bit and wait until the hardware acts on it
  145. */
  146. static int malidp_set_and_wait_config_valid(struct drm_device *drm)
  147. {
  148. struct malidp_drm *malidp = drm->dev_private;
  149. struct malidp_hw_device *hwdev = malidp->dev;
  150. int ret;
  151. hwdev->hw->set_config_valid(hwdev, 1);
  152. /* don't wait for config_valid flag if we are in config mode */
  153. if (hwdev->hw->in_config_mode(hwdev)) {
  154. atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
  155. return 0;
  156. }
  157. ret = wait_event_interruptible_timeout(malidp->wq,
  158. atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE,
  159. msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
  160. return (ret > 0) ? 0 : -ETIMEDOUT;
  161. }
  162. static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
  163. {
  164. struct drm_device *drm = state->dev;
  165. struct malidp_drm *malidp = drm->dev_private;
  166. int loop = 5;
  167. malidp->event = malidp->crtc.state->event;
  168. malidp->crtc.state->event = NULL;
  169. if (malidp->crtc.state->active) {
  170. /*
  171. * if we have an event to deliver to userspace, make sure
  172. * the vblank is enabled as we are sending it from the IRQ
  173. * handler.
  174. */
  175. if (malidp->event)
  176. drm_crtc_vblank_get(&malidp->crtc);
  177. /* only set config_valid if the CRTC is enabled */
  178. if (malidp_set_and_wait_config_valid(drm) < 0) {
  179. /*
  180. * make a loop around the second CVAL setting and
  181. * try 5 times before giving up.
  182. */
  183. while (loop--) {
  184. if (!malidp_set_and_wait_config_valid(drm))
  185. break;
  186. }
  187. DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
  188. }
  189. } else if (malidp->event) {
  190. /* CRTC inactive means vblank IRQ is disabled, send event directly */
  191. spin_lock_irq(&drm->event_lock);
  192. drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
  193. malidp->event = NULL;
  194. spin_unlock_irq(&drm->event_lock);
  195. }
  196. drm_atomic_helper_commit_hw_done(state);
  197. }
  198. static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
  199. {
  200. struct drm_device *drm = state->dev;
  201. struct malidp_drm *malidp = drm->dev_private;
  202. struct drm_crtc *crtc;
  203. struct drm_crtc_state *old_crtc_state;
  204. int i;
  205. pm_runtime_get_sync(drm->dev);
  206. /*
  207. * set config_valid to a special value to let IRQ handlers
  208. * know that we are updating registers
  209. */
  210. atomic_set(&malidp->config_valid, MALIDP_CONFIG_START);
  211. malidp->dev->hw->set_config_valid(malidp->dev, 0);
  212. drm_atomic_helper_commit_modeset_disables(drm, state);
  213. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  214. malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
  215. malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
  216. malidp_atomic_commit_se_config(crtc, old_crtc_state);
  217. }
  218. drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY);
  219. malidp_mw_atomic_commit(drm, state);
  220. drm_atomic_helper_commit_modeset_enables(drm, state);
  221. malidp_atomic_commit_hw_done(state);
  222. pm_runtime_put(drm->dev);
  223. drm_atomic_helper_cleanup_planes(drm, state);
  224. }
  225. static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
  226. .atomic_commit_tail = malidp_atomic_commit_tail,
  227. };
  228. static bool
  229. malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
  230. const struct drm_mode_fb_cmd2 *mode_cmd)
  231. {
  232. if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
  233. mode_cmd->modifier[0]) == false)
  234. return false;
  235. if (mode_cmd->offsets[0] != 0) {
  236. DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
  237. return false;
  238. }
  239. switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
  240. case AFBC_SIZE_16X16:
  241. if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
  242. DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
  243. return false;
  244. }
  245. break;
  246. default:
  247. DRM_DEBUG_KMS("Unsupported AFBC block size\n");
  248. return false;
  249. }
  250. return true;
  251. }
  252. static bool
  253. malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
  254. struct drm_file *file,
  255. const struct drm_mode_fb_cmd2 *mode_cmd)
  256. {
  257. int n_superblocks = 0;
  258. const struct drm_format_info *info;
  259. struct drm_gem_object *objs = NULL;
  260. u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
  261. u32 afbc_superblock_width = 0, afbc_size = 0;
  262. int bpp = 0;
  263. switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
  264. case AFBC_SIZE_16X16:
  265. afbc_superblock_height = 16;
  266. afbc_superblock_width = 16;
  267. break;
  268. default:
  269. DRM_DEBUG_KMS("AFBC superblock size is not supported\n");
  270. return false;
  271. }
  272. info = drm_get_format_info(dev, mode_cmd);
  273. n_superblocks = (mode_cmd->width / afbc_superblock_width) *
  274. (mode_cmd->height / afbc_superblock_height);
  275. bpp = malidp_format_get_bpp(info->format);
  276. afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height)
  277. / BITS_PER_BYTE;
  278. afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT);
  279. afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT);
  280. if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) {
  281. DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) "
  282. "should be same as width (=%u) * bpp (=%u)\n",
  283. (mode_cmd->pitches[0] * BITS_PER_BYTE),
  284. mode_cmd->width, bpp);
  285. return false;
  286. }
  287. objs = drm_gem_object_lookup(file, mode_cmd->handles[0]);
  288. if (!objs) {
  289. DRM_DEBUG_KMS("Failed to lookup GEM object\n");
  290. return false;
  291. }
  292. if (objs->size < afbc_size) {
  293. DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n",
  294. objs->size, afbc_size);
  295. drm_gem_object_put(objs);
  296. return false;
  297. }
  298. drm_gem_object_put(objs);
  299. return true;
  300. }
  301. static bool
  302. malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file,
  303. const struct drm_mode_fb_cmd2 *mode_cmd)
  304. {
  305. if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd))
  306. return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd);
  307. return false;
  308. }
  309. static struct drm_framebuffer *
  310. malidp_fb_create(struct drm_device *dev, struct drm_file *file,
  311. const struct drm_mode_fb_cmd2 *mode_cmd)
  312. {
  313. if (mode_cmd->modifier[0]) {
  314. if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd))
  315. return ERR_PTR(-EINVAL);
  316. }
  317. return drm_gem_fb_create(dev, file, mode_cmd);
  318. }
  319. static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
  320. .fb_create = malidp_fb_create,
  321. .atomic_check = drm_atomic_helper_check,
  322. .atomic_commit = drm_atomic_helper_commit,
  323. };
  324. static int malidp_init(struct drm_device *drm)
  325. {
  326. int ret;
  327. struct malidp_drm *malidp = drm->dev_private;
  328. struct malidp_hw_device *hwdev = malidp->dev;
  329. drm_mode_config_init(drm);
  330. drm->mode_config.min_width = hwdev->min_line_size;
  331. drm->mode_config.min_height = hwdev->min_line_size;
  332. drm->mode_config.max_width = hwdev->max_line_size;
  333. drm->mode_config.max_height = hwdev->max_line_size;
  334. drm->mode_config.funcs = &malidp_mode_config_funcs;
  335. drm->mode_config.helper_private = &malidp_mode_config_helpers;
  336. drm->mode_config.allow_fb_modifiers = true;
  337. ret = malidp_crtc_init(drm);
  338. if (ret)
  339. goto crtc_fail;
  340. ret = malidp_mw_connector_init(drm);
  341. if (ret)
  342. goto crtc_fail;
  343. return 0;
  344. crtc_fail:
  345. drm_mode_config_cleanup(drm);
  346. return ret;
  347. }
  348. static void malidp_fini(struct drm_device *drm)
  349. {
  350. drm_mode_config_cleanup(drm);
  351. }
  352. static int malidp_irq_init(struct platform_device *pdev)
  353. {
  354. int irq_de, irq_se, ret = 0;
  355. struct drm_device *drm = dev_get_drvdata(&pdev->dev);
  356. struct malidp_drm *malidp = drm->dev_private;
  357. struct malidp_hw_device *hwdev = malidp->dev;
  358. /* fetch the interrupts from DT */
  359. irq_de = platform_get_irq_byname(pdev, "DE");
  360. if (irq_de < 0) {
  361. DRM_ERROR("no 'DE' IRQ specified!\n");
  362. return irq_de;
  363. }
  364. irq_se = platform_get_irq_byname(pdev, "SE");
  365. if (irq_se < 0) {
  366. DRM_ERROR("no 'SE' IRQ specified!\n");
  367. return irq_se;
  368. }
  369. ret = malidp_de_irq_init(drm, irq_de);
  370. if (ret)
  371. return ret;
  372. ret = malidp_se_irq_init(drm, irq_se);
  373. if (ret) {
  374. malidp_de_irq_fini(hwdev);
  375. return ret;
  376. }
  377. return 0;
  378. }
  379. DEFINE_DRM_GEM_CMA_FOPS(fops);
  380. static int malidp_dumb_create(struct drm_file *file_priv,
  381. struct drm_device *drm,
  382. struct drm_mode_create_dumb *args)
  383. {
  384. struct malidp_drm *malidp = drm->dev_private;
  385. /* allocate for the worst case scenario, i.e. rotated buffers */
  386. u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
  387. args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
  388. return drm_gem_cma_dumb_create_internal(file_priv, drm, args);
  389. }
  390. #ifdef CONFIG_DEBUG_FS
  391. static void malidp_error_stats_init(struct malidp_error_stats *error_stats)
  392. {
  393. error_stats->num_errors = 0;
  394. error_stats->last_error_status = 0;
  395. error_stats->last_error_vblank = -1;
  396. }
  397. void malidp_error(struct malidp_drm *malidp,
  398. struct malidp_error_stats *error_stats, u32 status,
  399. u64 vblank)
  400. {
  401. unsigned long irqflags;
  402. spin_lock_irqsave(&malidp->errors_lock, irqflags);
  403. error_stats->last_error_status = status;
  404. error_stats->last_error_vblank = vblank;
  405. error_stats->num_errors++;
  406. spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
  407. }
  408. static void malidp_error_stats_dump(const char *prefix,
  409. struct malidp_error_stats error_stats,
  410. struct seq_file *m)
  411. {
  412. seq_printf(m, "[%s] num_errors : %d\n", prefix,
  413. error_stats.num_errors);
  414. seq_printf(m, "[%s] last_error_status : 0x%08x\n", prefix,
  415. error_stats.last_error_status);
  416. seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix,
  417. error_stats.last_error_vblank);
  418. }
  419. static int malidp_show_stats(struct seq_file *m, void *arg)
  420. {
  421. struct drm_device *drm = m->private;
  422. struct malidp_drm *malidp = drm->dev_private;
  423. unsigned long irqflags;
  424. struct malidp_error_stats de_errors, se_errors;
  425. spin_lock_irqsave(&malidp->errors_lock, irqflags);
  426. de_errors = malidp->de_errors;
  427. se_errors = malidp->se_errors;
  428. spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
  429. malidp_error_stats_dump("DE", de_errors, m);
  430. malidp_error_stats_dump("SE", se_errors, m);
  431. return 0;
  432. }
  433. static int malidp_debugfs_open(struct inode *inode, struct file *file)
  434. {
  435. return single_open(file, malidp_show_stats, inode->i_private);
  436. }
  437. static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf,
  438. size_t len, loff_t *offp)
  439. {
  440. struct seq_file *m = file->private_data;
  441. struct drm_device *drm = m->private;
  442. struct malidp_drm *malidp = drm->dev_private;
  443. unsigned long irqflags;
  444. spin_lock_irqsave(&malidp->errors_lock, irqflags);
  445. malidp_error_stats_init(&malidp->de_errors);
  446. malidp_error_stats_init(&malidp->se_errors);
  447. spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
  448. return len;
  449. }
  450. static const struct file_operations malidp_debugfs_fops = {
  451. .owner = THIS_MODULE,
  452. .open = malidp_debugfs_open,
  453. .read = seq_read,
  454. .write = malidp_debugfs_write,
  455. .llseek = seq_lseek,
  456. .release = single_release,
  457. };
  458. static void malidp_debugfs_init(struct drm_minor *minor)
  459. {
  460. struct malidp_drm *malidp = minor->dev->dev_private;
  461. malidp_error_stats_init(&malidp->de_errors);
  462. malidp_error_stats_init(&malidp->se_errors);
  463. spin_lock_init(&malidp->errors_lock);
  464. debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root,
  465. minor->dev, &malidp_debugfs_fops);
  466. }
  467. #endif //CONFIG_DEBUG_FS
  468. static struct drm_driver malidp_driver = {
  469. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  470. DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(malidp_dumb_create),
  471. #ifdef CONFIG_DEBUG_FS
  472. .debugfs_init = malidp_debugfs_init,
  473. #endif
  474. .fops = &fops,
  475. .name = "mali-dp",
  476. .desc = "ARM Mali Display Processor driver",
  477. .date = "20160106",
  478. .major = 1,
  479. .minor = 0,
  480. };
  481. static const struct of_device_id malidp_drm_of_match[] = {
  482. {
  483. .compatible = "arm,mali-dp500",
  484. .data = &malidp_device[MALIDP_500]
  485. },
  486. {
  487. .compatible = "arm,mali-dp550",
  488. .data = &malidp_device[MALIDP_550]
  489. },
  490. {
  491. .compatible = "arm,mali-dp650",
  492. .data = &malidp_device[MALIDP_650]
  493. },
  494. {},
  495. };
  496. MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
  497. static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
  498. const struct of_device_id *dev_id)
  499. {
  500. u32 core_id;
  501. const char *compatstr_dp500 = "arm,mali-dp500";
  502. bool is_dp500;
  503. bool dt_is_dp500;
  504. /*
  505. * The DP500 CORE_ID register is in a different location, so check it
  506. * first. If the product id field matches, then this is DP500, otherwise
  507. * check the DP550/650 CORE_ID register.
  508. */
  509. core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
  510. /* Offset 0x18 will never read 0x500 on products other than DP500. */
  511. is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
  512. dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
  513. sizeof(dev_id->compatible)) != NULL;
  514. if (is_dp500 != dt_is_dp500) {
  515. DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
  516. dev_id->compatible, is_dp500 ? "is" : "is not");
  517. return false;
  518. } else if (!dt_is_dp500) {
  519. u16 product_id;
  520. char buf[32];
  521. core_id = malidp_hw_read(hwdev,
  522. MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
  523. product_id = MALIDP_PRODUCT_ID(core_id);
  524. snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
  525. if (!strnstr(dev_id->compatible, buf,
  526. sizeof(dev_id->compatible))) {
  527. DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
  528. dev_id->compatible, product_id);
  529. return false;
  530. }
  531. }
  532. return true;
  533. }
  534. static bool malidp_has_sufficient_address_space(const struct resource *res,
  535. const struct of_device_id *dev_id)
  536. {
  537. resource_size_t res_size = resource_size(res);
  538. const char *compatstr_dp500 = "arm,mali-dp500";
  539. if (!strnstr(dev_id->compatible, compatstr_dp500,
  540. sizeof(dev_id->compatible)))
  541. return res_size >= MALIDP550_ADDR_SPACE_SIZE;
  542. else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
  543. return false;
  544. return true;
  545. }
  546. static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
  547. char *buf)
  548. {
  549. struct drm_device *drm = dev_get_drvdata(dev);
  550. struct malidp_drm *malidp = drm->dev_private;
  551. return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id);
  552. }
  553. static DEVICE_ATTR_RO(core_id);
  554. static struct attribute *mali_dp_attrs[] = {
  555. &dev_attr_core_id.attr,
  556. NULL,
  557. };
  558. ATTRIBUTE_GROUPS(mali_dp);
  559. #define MAX_OUTPUT_CHANNELS 3
  560. static int malidp_runtime_pm_suspend(struct device *dev)
  561. {
  562. struct drm_device *drm = dev_get_drvdata(dev);
  563. struct malidp_drm *malidp = drm->dev_private;
  564. struct malidp_hw_device *hwdev = malidp->dev;
  565. /* we can only suspend if the hardware is in config mode */
  566. WARN_ON(!hwdev->hw->in_config_mode(hwdev));
  567. malidp_se_irq_fini(hwdev);
  568. malidp_de_irq_fini(hwdev);
  569. hwdev->pm_suspended = true;
  570. clk_disable_unprepare(hwdev->mclk);
  571. clk_disable_unprepare(hwdev->aclk);
  572. clk_disable_unprepare(hwdev->pclk);
  573. return 0;
  574. }
  575. static int malidp_runtime_pm_resume(struct device *dev)
  576. {
  577. struct drm_device *drm = dev_get_drvdata(dev);
  578. struct malidp_drm *malidp = drm->dev_private;
  579. struct malidp_hw_device *hwdev = malidp->dev;
  580. clk_prepare_enable(hwdev->pclk);
  581. clk_prepare_enable(hwdev->aclk);
  582. clk_prepare_enable(hwdev->mclk);
  583. hwdev->pm_suspended = false;
  584. malidp_de_irq_hw_init(hwdev);
  585. malidp_se_irq_hw_init(hwdev);
  586. return 0;
  587. }
  588. static int malidp_bind(struct device *dev)
  589. {
  590. struct resource *res;
  591. struct drm_device *drm;
  592. struct malidp_drm *malidp;
  593. struct malidp_hw_device *hwdev;
  594. struct platform_device *pdev = to_platform_device(dev);
  595. struct of_device_id const *dev_id;
  596. struct drm_encoder *encoder;
  597. /* number of lines for the R, G and B output */
  598. u8 output_width[MAX_OUTPUT_CHANNELS];
  599. int ret = 0, i;
  600. u32 version, out_depth = 0;
  601. malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
  602. if (!malidp)
  603. return -ENOMEM;
  604. hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
  605. if (!hwdev)
  606. return -ENOMEM;
  607. hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
  608. malidp->dev = hwdev;
  609. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  610. hwdev->regs = devm_ioremap_resource(dev, res);
  611. if (IS_ERR(hwdev->regs))
  612. return PTR_ERR(hwdev->regs);
  613. hwdev->pclk = devm_clk_get(dev, "pclk");
  614. if (IS_ERR(hwdev->pclk))
  615. return PTR_ERR(hwdev->pclk);
  616. hwdev->aclk = devm_clk_get(dev, "aclk");
  617. if (IS_ERR(hwdev->aclk))
  618. return PTR_ERR(hwdev->aclk);
  619. hwdev->mclk = devm_clk_get(dev, "mclk");
  620. if (IS_ERR(hwdev->mclk))
  621. return PTR_ERR(hwdev->mclk);
  622. hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
  623. if (IS_ERR(hwdev->pxlclk))
  624. return PTR_ERR(hwdev->pxlclk);
  625. /* Get the optional framebuffer memory resource */
  626. ret = of_reserved_mem_device_init(dev);
  627. if (ret && ret != -ENODEV)
  628. return ret;
  629. drm = drm_dev_alloc(&malidp_driver, dev);
  630. if (IS_ERR(drm)) {
  631. ret = PTR_ERR(drm);
  632. goto alloc_fail;
  633. }
  634. drm->dev_private = malidp;
  635. dev_set_drvdata(dev, drm);
  636. /* Enable power management */
  637. pm_runtime_enable(dev);
  638. /* Resume device to enable the clocks */
  639. if (pm_runtime_enabled(dev))
  640. pm_runtime_get_sync(dev);
  641. else
  642. malidp_runtime_pm_resume(dev);
  643. dev_id = of_match_device(malidp_drm_of_match, dev);
  644. if (!dev_id) {
  645. ret = -EINVAL;
  646. goto query_hw_fail;
  647. }
  648. if (!malidp_has_sufficient_address_space(res, dev_id)) {
  649. DRM_ERROR("Insufficient address space in device-tree.\n");
  650. ret = -EINVAL;
  651. goto query_hw_fail;
  652. }
  653. if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
  654. ret = -EINVAL;
  655. goto query_hw_fail;
  656. }
  657. ret = hwdev->hw->query_hw(hwdev);
  658. if (ret) {
  659. DRM_ERROR("Invalid HW configuration\n");
  660. goto query_hw_fail;
  661. }
  662. version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
  663. DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
  664. (version >> 12) & 0xf, (version >> 8) & 0xf);
  665. malidp->core_id = version;
  666. ret = of_property_read_u32(dev->of_node,
  667. "arm,malidp-arqos-value",
  668. &hwdev->arqos_value);
  669. if (ret)
  670. hwdev->arqos_value = 0x0;
  671. /* set the number of lines used for output of RGB data */
  672. ret = of_property_read_u8_array(dev->of_node,
  673. "arm,malidp-output-port-lines",
  674. output_width, MAX_OUTPUT_CHANNELS);
  675. if (ret)
  676. goto query_hw_fail;
  677. for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
  678. out_depth = (out_depth << 8) | (output_width[i] & 0xf);
  679. malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
  680. hwdev->output_color_depth = out_depth;
  681. atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT);
  682. init_waitqueue_head(&malidp->wq);
  683. ret = malidp_init(drm);
  684. if (ret < 0)
  685. goto query_hw_fail;
  686. /* Set the CRTC's port so that the encoder component can find it */
  687. malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
  688. ret = component_bind_all(dev, drm);
  689. if (ret) {
  690. DRM_ERROR("Failed to bind all components\n");
  691. goto bind_fail;
  692. }
  693. /* We expect to have a maximum of two encoders one for the actual
  694. * display and a virtual one for the writeback connector
  695. */
  696. WARN_ON(drm->mode_config.num_encoder > 2);
  697. list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) {
  698. encoder->possible_clones =
  699. (1 << drm->mode_config.num_encoder) - 1;
  700. }
  701. ret = malidp_irq_init(pdev);
  702. if (ret < 0)
  703. goto irq_init_fail;
  704. drm->irq_enabled = true;
  705. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  706. if (ret < 0) {
  707. DRM_ERROR("failed to initialise vblank\n");
  708. goto vblank_fail;
  709. }
  710. pm_runtime_put(dev);
  711. drm_mode_config_reset(drm);
  712. drm_kms_helper_poll_init(drm);
  713. ret = drm_dev_register(drm, 0);
  714. if (ret)
  715. goto register_fail;
  716. drm_fbdev_generic_setup(drm, 32);
  717. return 0;
  718. register_fail:
  719. drm_kms_helper_poll_fini(drm);
  720. pm_runtime_get_sync(dev);
  721. vblank_fail:
  722. malidp_se_irq_fini(hwdev);
  723. malidp_de_irq_fini(hwdev);
  724. drm->irq_enabled = false;
  725. irq_init_fail:
  726. drm_atomic_helper_shutdown(drm);
  727. component_unbind_all(dev, drm);
  728. bind_fail:
  729. of_node_put(malidp->crtc.port);
  730. malidp->crtc.port = NULL;
  731. malidp_fini(drm);
  732. query_hw_fail:
  733. pm_runtime_put(dev);
  734. if (pm_runtime_enabled(dev))
  735. pm_runtime_disable(dev);
  736. else
  737. malidp_runtime_pm_suspend(dev);
  738. drm->dev_private = NULL;
  739. dev_set_drvdata(dev, NULL);
  740. drm_dev_put(drm);
  741. alloc_fail:
  742. of_reserved_mem_device_release(dev);
  743. return ret;
  744. }
  745. static void malidp_unbind(struct device *dev)
  746. {
  747. struct drm_device *drm = dev_get_drvdata(dev);
  748. struct malidp_drm *malidp = drm->dev_private;
  749. struct malidp_hw_device *hwdev = malidp->dev;
  750. drm_dev_unregister(drm);
  751. drm_kms_helper_poll_fini(drm);
  752. pm_runtime_get_sync(dev);
  753. drm_atomic_helper_shutdown(drm);
  754. malidp_se_irq_fini(hwdev);
  755. malidp_de_irq_fini(hwdev);
  756. drm->irq_enabled = false;
  757. component_unbind_all(dev, drm);
  758. of_node_put(malidp->crtc.port);
  759. malidp->crtc.port = NULL;
  760. malidp_fini(drm);
  761. pm_runtime_put(dev);
  762. if (pm_runtime_enabled(dev))
  763. pm_runtime_disable(dev);
  764. else
  765. malidp_runtime_pm_suspend(dev);
  766. drm->dev_private = NULL;
  767. dev_set_drvdata(dev, NULL);
  768. drm_dev_put(drm);
  769. of_reserved_mem_device_release(dev);
  770. }
  771. static const struct component_master_ops malidp_master_ops = {
  772. .bind = malidp_bind,
  773. .unbind = malidp_unbind,
  774. };
  775. static int malidp_compare_dev(struct device *dev, void *data)
  776. {
  777. struct device_node *np = data;
  778. return dev->of_node == np;
  779. }
  780. static int malidp_platform_probe(struct platform_device *pdev)
  781. {
  782. struct device_node *port;
  783. struct component_match *match = NULL;
  784. if (!pdev->dev.of_node)
  785. return -ENODEV;
  786. /* there is only one output port inside each device, find it */
  787. port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
  788. if (!port)
  789. return -ENODEV;
  790. drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
  791. port);
  792. of_node_put(port);
  793. return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
  794. match);
  795. }
  796. static int malidp_platform_remove(struct platform_device *pdev)
  797. {
  798. component_master_del(&pdev->dev, &malidp_master_ops);
  799. return 0;
  800. }
  801. static int __maybe_unused malidp_pm_suspend(struct device *dev)
  802. {
  803. struct drm_device *drm = dev_get_drvdata(dev);
  804. return drm_mode_config_helper_suspend(drm);
  805. }
  806. static int __maybe_unused malidp_pm_resume(struct device *dev)
  807. {
  808. struct drm_device *drm = dev_get_drvdata(dev);
  809. drm_mode_config_helper_resume(drm);
  810. return 0;
  811. }
  812. static int __maybe_unused malidp_pm_suspend_late(struct device *dev)
  813. {
  814. if (!pm_runtime_status_suspended(dev)) {
  815. malidp_runtime_pm_suspend(dev);
  816. pm_runtime_set_suspended(dev);
  817. }
  818. return 0;
  819. }
  820. static int __maybe_unused malidp_pm_resume_early(struct device *dev)
  821. {
  822. malidp_runtime_pm_resume(dev);
  823. pm_runtime_set_active(dev);
  824. return 0;
  825. }
  826. static const struct dev_pm_ops malidp_pm_ops = {
  827. SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
  828. SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \
  829. SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
  830. };
  831. static struct platform_driver malidp_platform_driver = {
  832. .probe = malidp_platform_probe,
  833. .remove = malidp_platform_remove,
  834. .driver = {
  835. .name = "mali-dp",
  836. .pm = &malidp_pm_ops,
  837. .of_match_table = malidp_drm_of_match,
  838. .dev_groups = mali_dp_groups,
  839. },
  840. };
  841. module_platform_driver(malidp_platform_driver);
  842. MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
  843. MODULE_DESCRIPTION("ARM Mali DP DRM driver");
  844. MODULE_LICENSE("GPL v2");