malidp_crtc.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  4. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  5. *
  6. * ARM Mali DP500/DP550/DP650 driver (crtc operations)
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/pm_runtime.h>
  10. #include <video/videomode.h>
  11. #include <drm/drm_atomic.h>
  12. #include <drm/drm_atomic_helper.h>
  13. #include <drm/drm_crtc.h>
  14. #include <drm/drm_print.h>
  15. #include <drm/drm_probe_helper.h>
  16. #include <drm/drm_vblank.h>
  17. #include "malidp_drv.h"
  18. #include "malidp_hw.h"
  19. static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
  20. const struct drm_display_mode *mode)
  21. {
  22. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  23. struct malidp_hw_device *hwdev = malidp->dev;
  24. /*
  25. * check that the hardware can drive the required clock rate,
  26. * but skip the check if the clock is meant to be disabled (req_rate = 0)
  27. */
  28. long rate, req_rate = mode->crtc_clock * 1000;
  29. if (req_rate) {
  30. rate = clk_round_rate(hwdev->pxlclk, req_rate);
  31. if (rate != req_rate) {
  32. DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
  33. req_rate);
  34. return MODE_NOCLOCK;
  35. }
  36. }
  37. return MODE_OK;
  38. }
  39. static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,
  40. struct drm_crtc_state *old_state)
  41. {
  42. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  43. struct malidp_hw_device *hwdev = malidp->dev;
  44. struct videomode vm;
  45. int err = pm_runtime_get_sync(crtc->dev->dev);
  46. if (err < 0) {
  47. DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
  48. return;
  49. }
  50. drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
  51. clk_prepare_enable(hwdev->pxlclk);
  52. /* We rely on firmware to set mclk to a sensible level. */
  53. clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
  54. hwdev->hw->modeset(hwdev, &vm);
  55. hwdev->hw->leave_config_mode(hwdev);
  56. drm_crtc_vblank_on(crtc);
  57. }
  58. static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,
  59. struct drm_crtc_state *old_state)
  60. {
  61. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  62. struct malidp_hw_device *hwdev = malidp->dev;
  63. int err;
  64. /* always disable planes on the CRTC that is being turned off */
  65. drm_atomic_helper_disable_planes_on_crtc(old_state, false);
  66. drm_crtc_vblank_off(crtc);
  67. hwdev->hw->enter_config_mode(hwdev);
  68. clk_disable_unprepare(hwdev->pxlclk);
  69. err = pm_runtime_put(crtc->dev->dev);
  70. if (err < 0) {
  71. DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
  72. }
  73. }
  74. static const struct gamma_curve_segment {
  75. u16 start;
  76. u16 end;
  77. } segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
  78. /* sector 0 */
  79. { 0, 0 }, { 1, 1 }, { 2, 2 }, { 3, 3 },
  80. { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
  81. { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 },
  82. { 12, 12 }, { 13, 13 }, { 14, 14 }, { 15, 15 },
  83. /* sector 1 */
  84. { 16, 19 }, { 20, 23 }, { 24, 27 }, { 28, 31 },
  85. /* sector 2 */
  86. { 32, 39 }, { 40, 47 }, { 48, 55 }, { 56, 63 },
  87. /* sector 3 */
  88. { 64, 79 }, { 80, 95 }, { 96, 111 }, { 112, 127 },
  89. /* sector 4 */
  90. { 128, 159 }, { 160, 191 }, { 192, 223 }, { 224, 255 },
  91. /* sector 5 */
  92. { 256, 319 }, { 320, 383 }, { 384, 447 }, { 448, 511 },
  93. /* sector 6 */
  94. { 512, 639 }, { 640, 767 }, { 768, 895 }, { 896, 1023 },
  95. { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
  96. { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
  97. { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
  98. { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
  99. { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
  100. { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
  101. };
  102. #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
  103. static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
  104. u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
  105. {
  106. struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
  107. int i;
  108. for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
  109. u32 a, b, delta_in, out_start, out_end;
  110. delta_in = segments[i].end - segments[i].start;
  111. /* DP has 12-bit internal precision for its LUTs. */
  112. out_start = drm_color_lut_extract(lut[segments[i].start].green,
  113. 12);
  114. out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
  115. a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
  116. b = out_start;
  117. coeffs[i] = DE_COEFTAB_DATA(a, b);
  118. }
  119. }
  120. /*
  121. * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
  122. * reject any LUTs that use distinct red, green, and blue curves.
  123. */
  124. static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
  125. struct drm_crtc_state *state)
  126. {
  127. struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
  128. struct drm_color_lut *lut;
  129. size_t lut_size;
  130. int i;
  131. if (!state->color_mgmt_changed || !state->gamma_lut)
  132. return 0;
  133. if (crtc->state->gamma_lut &&
  134. (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
  135. return 0;
  136. if (state->gamma_lut->length % sizeof(struct drm_color_lut))
  137. return -EINVAL;
  138. lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
  139. if (lut_size != MALIDP_GAMMA_LUT_SIZE)
  140. return -EINVAL;
  141. lut = (struct drm_color_lut *)state->gamma_lut->data;
  142. for (i = 0; i < lut_size; ++i)
  143. if (!((lut[i].red == lut[i].green) &&
  144. (lut[i].red == lut[i].blue)))
  145. return -EINVAL;
  146. if (!state->mode_changed) {
  147. int ret;
  148. state->mode_changed = true;
  149. /*
  150. * Kerneldoc for drm_atomic_helper_check_modeset mandates that
  151. * it be invoked when the driver sets ->mode_changed. Since
  152. * changing the gamma LUT doesn't depend on any external
  153. * resources, it is safe to call it only once.
  154. */
  155. ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
  156. if (ret)
  157. return ret;
  158. }
  159. malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
  160. return 0;
  161. }
  162. /*
  163. * Check if there is a new CTM and if it contains valid input. Valid here means
  164. * that the number is inside the representable range for a Q3.12 number,
  165. * excluding truncating the fractional part of the input data.
  166. *
  167. * The COLORADJ registers can be changed atomically.
  168. */
  169. static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
  170. struct drm_crtc_state *state)
  171. {
  172. struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
  173. struct drm_color_ctm *ctm;
  174. int i;
  175. if (!state->color_mgmt_changed)
  176. return 0;
  177. if (!state->ctm)
  178. return 0;
  179. if (crtc->state->ctm && (crtc->state->ctm->base.id ==
  180. state->ctm->base.id))
  181. return 0;
  182. /*
  183. * The size of the ctm is checked in
  184. * drm_atomic_replace_property_blob_from_id.
  185. */
  186. ctm = (struct drm_color_ctm *)state->ctm->data;
  187. for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
  188. /* Convert from S31.32 to Q3.12. */
  189. s64 val = ctm->matrix[i];
  190. u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
  191. GENMASK_ULL(14, 0);
  192. /*
  193. * Convert to 2s complement and check the destination's top bit
  194. * for overflow. NB: Can't check before converting or it'd
  195. * incorrectly reject the case:
  196. * sign == 1
  197. * mag == 0x2000
  198. */
  199. if (val & BIT_ULL(63))
  200. mag = ~mag + 1;
  201. if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
  202. return -EINVAL;
  203. mc->coloradj_coeffs[i] = mag;
  204. }
  205. return 0;
  206. }
  207. static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
  208. struct drm_crtc_state *state)
  209. {
  210. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  211. struct malidp_hw_device *hwdev = malidp->dev;
  212. struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
  213. struct malidp_se_config *s = &cs->scaler_config;
  214. struct drm_plane *plane;
  215. struct videomode vm;
  216. const struct drm_plane_state *pstate;
  217. u32 h_upscale_factor = 0; /* U16.16 */
  218. u32 v_upscale_factor = 0; /* U16.16 */
  219. u8 scaling = cs->scaled_planes_mask;
  220. int ret;
  221. if (!scaling) {
  222. s->scale_enable = false;
  223. goto mclk_calc;
  224. }
  225. /* The scaling engine can only handle one plane at a time. */
  226. if (scaling & (scaling - 1))
  227. return -EINVAL;
  228. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  229. struct malidp_plane *mp = to_malidp_plane(plane);
  230. u32 phase;
  231. if (!(mp->layer->id & scaling))
  232. continue;
  233. /*
  234. * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
  235. * to get the U16.16 result.
  236. */
  237. h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
  238. pstate->src_w);
  239. v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
  240. pstate->src_h);
  241. s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
  242. (v_upscale_factor >> 16) >= 2);
  243. if (pstate->rotation & MALIDP_ROTATED_MASK) {
  244. s->input_w = pstate->src_h >> 16;
  245. s->input_h = pstate->src_w >> 16;
  246. } else {
  247. s->input_w = pstate->src_w >> 16;
  248. s->input_h = pstate->src_h >> 16;
  249. }
  250. s->output_w = pstate->crtc_w;
  251. s->output_h = pstate->crtc_h;
  252. #define SE_N_PHASE 4
  253. #define SE_SHIFT_N_PHASE 12
  254. /* Calculate initial_phase and delta_phase for horizontal. */
  255. phase = s->input_w;
  256. s->h_init_phase =
  257. ((phase << SE_N_PHASE) / s->output_w + 1) / 2;
  258. phase = s->input_w;
  259. phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
  260. s->h_delta_phase = phase / s->output_w;
  261. /* Same for vertical. */
  262. phase = s->input_h;
  263. s->v_init_phase =
  264. ((phase << SE_N_PHASE) / s->output_h + 1) / 2;
  265. phase = s->input_h;
  266. phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
  267. s->v_delta_phase = phase / s->output_h;
  268. #undef SE_N_PHASE
  269. #undef SE_SHIFT_N_PHASE
  270. s->plane_src_id = mp->layer->id;
  271. }
  272. s->scale_enable = true;
  273. s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
  274. s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
  275. mclk_calc:
  276. drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
  277. ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm);
  278. if (ret < 0)
  279. return -EINVAL;
  280. return 0;
  281. }
  282. static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
  283. struct drm_crtc_state *state)
  284. {
  285. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  286. struct malidp_hw_device *hwdev = malidp->dev;
  287. struct drm_plane *plane;
  288. const struct drm_plane_state *pstate;
  289. u32 rot_mem_free, rot_mem_usable;
  290. int rotated_planes = 0;
  291. int ret;
  292. /*
  293. * check if there is enough rotation memory available for planes
  294. * that need 90° and 270° rotion or planes that are compressed.
  295. * Each plane has set its required memory size in the ->plane_check()
  296. * callback, here we only make sure that the sums are less that the
  297. * total usable memory.
  298. *
  299. * The rotation memory allocation algorithm (for each plane):
  300. * a. If no more rotated or compressed planes exist, all remaining
  301. * rotate memory in the bank is available for use by the plane.
  302. * b. If other rotated or compressed planes exist, and plane's
  303. * layer ID is DE_VIDEO1, it can use all the memory from first bank
  304. * if secondary rotation memory bank is available, otherwise it can
  305. * use up to half the bank's memory.
  306. * c. If other rotated or compressed planes exist, and plane's layer ID
  307. * is not DE_VIDEO1, it can use half of the available memory.
  308. *
  309. * Note: this algorithm assumes that the order in which the planes are
  310. * checked always has DE_VIDEO1 plane first in the list if it is
  311. * rotated. Because that is how we create the planes in the first
  312. * place, under current DRM version things work, but if ever the order
  313. * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
  314. * changes, we need to pre-sort the planes before validation.
  315. */
  316. /* first count the number of rotated planes */
  317. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  318. struct drm_framebuffer *fb = pstate->fb;
  319. if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier)
  320. rotated_planes++;
  321. }
  322. rot_mem_free = hwdev->rotation_memory[0];
  323. /*
  324. * if we have more than 1 plane using rotation memory, use the second
  325. * block of rotation memory as well
  326. */
  327. if (rotated_planes > 1)
  328. rot_mem_free += hwdev->rotation_memory[1];
  329. /* now validate the rotation memory requirements */
  330. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  331. struct malidp_plane *mp = to_malidp_plane(plane);
  332. struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
  333. struct drm_framebuffer *fb = pstate->fb;
  334. if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier) {
  335. /* process current plane */
  336. rotated_planes--;
  337. if (!rotated_planes) {
  338. /* no more rotated planes, we can use what's left */
  339. rot_mem_usable = rot_mem_free;
  340. } else {
  341. if ((mp->layer->id != DE_VIDEO1) ||
  342. (hwdev->rotation_memory[1] == 0))
  343. rot_mem_usable = rot_mem_free / 2;
  344. else
  345. rot_mem_usable = hwdev->rotation_memory[0];
  346. }
  347. rot_mem_free -= rot_mem_usable;
  348. if (ms->rotmem_size > rot_mem_usable)
  349. return -EINVAL;
  350. }
  351. }
  352. /* If only the writeback routing has changed, we don't need a modeset */
  353. if (state->connectors_changed) {
  354. u32 old_mask = crtc->state->connector_mask;
  355. u32 new_mask = state->connector_mask;
  356. if ((old_mask ^ new_mask) ==
  357. (1 << drm_connector_index(&malidp->mw_connector.base)))
  358. state->connectors_changed = false;
  359. }
  360. ret = malidp_crtc_atomic_check_gamma(crtc, state);
  361. ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);
  362. ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);
  363. return ret;
  364. }
  365. static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
  366. .mode_valid = malidp_crtc_mode_valid,
  367. .atomic_check = malidp_crtc_atomic_check,
  368. .atomic_enable = malidp_crtc_atomic_enable,
  369. .atomic_disable = malidp_crtc_atomic_disable,
  370. };
  371. static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
  372. {
  373. struct malidp_crtc_state *state, *old_state;
  374. if (WARN_ON(!crtc->state))
  375. return NULL;
  376. old_state = to_malidp_crtc_state(crtc->state);
  377. state = kmalloc(sizeof(*state), GFP_KERNEL);
  378. if (!state)
  379. return NULL;
  380. __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
  381. memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
  382. sizeof(state->gamma_coeffs));
  383. memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
  384. sizeof(state->coloradj_coeffs));
  385. memcpy(&state->scaler_config, &old_state->scaler_config,
  386. sizeof(state->scaler_config));
  387. state->scaled_planes_mask = 0;
  388. return &state->base;
  389. }
  390. static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
  391. struct drm_crtc_state *state)
  392. {
  393. struct malidp_crtc_state *mali_state = NULL;
  394. if (state) {
  395. mali_state = to_malidp_crtc_state(state);
  396. __drm_atomic_helper_crtc_destroy_state(state);
  397. }
  398. kfree(mali_state);
  399. }
  400. static void malidp_crtc_reset(struct drm_crtc *crtc)
  401. {
  402. struct malidp_crtc_state *state =
  403. kzalloc(sizeof(*state), GFP_KERNEL);
  404. if (crtc->state)
  405. malidp_crtc_destroy_state(crtc, crtc->state);
  406. __drm_atomic_helper_crtc_reset(crtc, &state->base);
  407. }
  408. static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
  409. {
  410. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  411. struct malidp_hw_device *hwdev = malidp->dev;
  412. malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
  413. hwdev->hw->map.de_irq_map.vsync_irq);
  414. return 0;
  415. }
  416. static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
  417. {
  418. struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  419. struct malidp_hw_device *hwdev = malidp->dev;
  420. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
  421. hwdev->hw->map.de_irq_map.vsync_irq);
  422. }
  423. static const struct drm_crtc_funcs malidp_crtc_funcs = {
  424. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  425. .destroy = drm_crtc_cleanup,
  426. .set_config = drm_atomic_helper_set_config,
  427. .page_flip = drm_atomic_helper_page_flip,
  428. .reset = malidp_crtc_reset,
  429. .atomic_duplicate_state = malidp_crtc_duplicate_state,
  430. .atomic_destroy_state = malidp_crtc_destroy_state,
  431. .enable_vblank = malidp_crtc_enable_vblank,
  432. .disable_vblank = malidp_crtc_disable_vblank,
  433. };
  434. int malidp_crtc_init(struct drm_device *drm)
  435. {
  436. struct malidp_drm *malidp = drm->dev_private;
  437. struct drm_plane *primary = NULL, *plane;
  438. int ret;
  439. ret = malidp_de_planes_init(drm);
  440. if (ret < 0) {
  441. DRM_ERROR("Failed to initialise planes\n");
  442. return ret;
  443. }
  444. drm_for_each_plane(plane, drm) {
  445. if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
  446. primary = plane;
  447. break;
  448. }
  449. }
  450. if (!primary) {
  451. DRM_ERROR("no primary plane found\n");
  452. return -EINVAL;
  453. }
  454. ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
  455. &malidp_crtc_funcs, NULL);
  456. if (ret)
  457. return ret;
  458. drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
  459. drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
  460. /* No inverse-gamma: it is per-plane. */
  461. drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
  462. malidp_se_set_enh_coeffs(malidp->dev);
  463. return 0;
  464. }