hdlcd_regs.h 2.8 KB

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  1. /*
  2. * Copyright (C) 2013,2014 ARM Limited
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file COPYING in the main directory of this archive
  6. * for more details.
  7. *
  8. * ARM HDLCD Controller register definition
  9. */
  10. #ifndef __HDLCD_REGS_H__
  11. #define __HDLCD_REGS_H__
  12. /* register offsets */
  13. #define HDLCD_REG_VERSION 0x0000 /* ro */
  14. #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
  15. #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
  16. #define HDLCD_REG_INT_MASK 0x0018 /* rw */
  17. #define HDLCD_REG_INT_STATUS 0x001c /* ro */
  18. #define HDLCD_REG_FB_BASE 0x0100 /* rw */
  19. #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
  20. #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
  21. #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
  22. #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
  23. #define HDLCD_REG_V_SYNC 0x0200 /* rw */
  24. #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
  25. #define HDLCD_REG_V_DATA 0x0208 /* rw */
  26. #define HDLCD_REG_V_FRONT_PORCH 0x020c /* rw */
  27. #define HDLCD_REG_H_SYNC 0x0210 /* rw */
  28. #define HDLCD_REG_H_BACK_PORCH 0x0214 /* rw */
  29. #define HDLCD_REG_H_DATA 0x0218 /* rw */
  30. #define HDLCD_REG_H_FRONT_PORCH 0x021c /* rw */
  31. #define HDLCD_REG_POLARITIES 0x0220 /* rw */
  32. #define HDLCD_REG_COMMAND 0x0230 /* rw */
  33. #define HDLCD_REG_PIXEL_FORMAT 0x0240 /* rw */
  34. #define HDLCD_REG_RED_SELECT 0x0244 /* rw */
  35. #define HDLCD_REG_GREEN_SELECT 0x0248 /* rw */
  36. #define HDLCD_REG_BLUE_SELECT 0x024c /* rw */
  37. /* version */
  38. #define HDLCD_PRODUCT_ID 0x1CDC0000
  39. #define HDLCD_PRODUCT_MASK 0xFFFF0000
  40. #define HDLCD_VERSION_MAJOR_MASK 0x0000FF00
  41. #define HDLCD_VERSION_MINOR_MASK 0x000000FF
  42. /* interrupts */
  43. #define HDLCD_INTERRUPT_DMA_END (1 << 0)
  44. #define HDLCD_INTERRUPT_BUS_ERROR (1 << 1)
  45. #define HDLCD_INTERRUPT_VSYNC (1 << 2)
  46. #define HDLCD_INTERRUPT_UNDERRUN (1 << 3)
  47. #define HDLCD_DEBUG_INT_MASK (HDLCD_INTERRUPT_DMA_END | \
  48. HDLCD_INTERRUPT_BUS_ERROR | \
  49. HDLCD_INTERRUPT_UNDERRUN)
  50. /* polarities */
  51. #define HDLCD_POLARITY_VSYNC (1 << 0)
  52. #define HDLCD_POLARITY_HSYNC (1 << 1)
  53. #define HDLCD_POLARITY_DATAEN (1 << 2)
  54. #define HDLCD_POLARITY_DATA (1 << 3)
  55. #define HDLCD_POLARITY_PIXELCLK (1 << 4)
  56. /* commands */
  57. #define HDLCD_COMMAND_DISABLE (0 << 0)
  58. #define HDLCD_COMMAND_ENABLE (1 << 0)
  59. /* pixel format */
  60. #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN (0 << 31)
  61. #define HDLCD_PIXEL_FMT_BIG_ENDIAN (1 << 31)
  62. #define HDLCD_BYTES_PER_PIXEL_MASK (3 << 3)
  63. /* bus options */
  64. #define HDLCD_BUS_BURST_MASK 0x01f
  65. #define HDLCD_BUS_MAX_OUTSTAND 0xf00
  66. #define HDLCD_BUS_BURST_NONE (0 << 0)
  67. #define HDLCD_BUS_BURST_1 (1 << 0)
  68. #define HDLCD_BUS_BURST_2 (1 << 1)
  69. #define HDLCD_BUS_BURST_4 (1 << 2)
  70. #define HDLCD_BUS_BURST_8 (1 << 3)
  71. #define HDLCD_BUS_BURST_16 (1 << 4)
  72. /* Max resolution supported is 4096x4096, 32bpp */
  73. #define HDLCD_MAX_XRES 4096
  74. #define HDLCD_MAX_YRES 4096
  75. #define NR_PALETTE 256
  76. #endif /* __HDLCD_REGS_H__ */