hdlcd_drv.c 10 KB

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  1. /*
  2. * Copyright (C) 2013-2015 ARM Limited
  3. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4. *
  5. * This file is subject to the terms and conditions of the GNU General Public
  6. * License. See the file COPYING in the main directory of this archive
  7. * for more details.
  8. *
  9. * ARM HDLCD Driver
  10. */
  11. #include <linux/module.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/clk.h>
  14. #include <linux/component.h>
  15. #include <linux/console.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/list.h>
  18. #include <linux/of_graph.h>
  19. #include <linux/of_reserved_mem.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include <drm/drm_crtc.h>
  24. #include <drm/drm_debugfs.h>
  25. #include <drm/drm_drv.h>
  26. #include <drm/drm_fb_cma_helper.h>
  27. #include <drm/drm_fb_helper.h>
  28. #include <drm/drm_gem_cma_helper.h>
  29. #include <drm/drm_gem_framebuffer_helper.h>
  30. #include <drm/drm_irq.h>
  31. #include <drm/drm_modeset_helper.h>
  32. #include <drm/drm_of.h>
  33. #include <drm/drm_probe_helper.h>
  34. #include <drm/drm_vblank.h>
  35. #include "hdlcd_drv.h"
  36. #include "hdlcd_regs.h"
  37. static int hdlcd_load(struct drm_device *drm, unsigned long flags)
  38. {
  39. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  40. struct platform_device *pdev = to_platform_device(drm->dev);
  41. struct resource *res;
  42. u32 version;
  43. int ret;
  44. hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
  45. if (IS_ERR(hdlcd->clk))
  46. return PTR_ERR(hdlcd->clk);
  47. #ifdef CONFIG_DEBUG_FS
  48. atomic_set(&hdlcd->buffer_underrun_count, 0);
  49. atomic_set(&hdlcd->bus_error_count, 0);
  50. atomic_set(&hdlcd->vsync_count, 0);
  51. atomic_set(&hdlcd->dma_end_count, 0);
  52. #endif
  53. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  54. hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
  55. if (IS_ERR(hdlcd->mmio)) {
  56. DRM_ERROR("failed to map control registers area\n");
  57. ret = PTR_ERR(hdlcd->mmio);
  58. hdlcd->mmio = NULL;
  59. return ret;
  60. }
  61. version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
  62. if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
  63. DRM_ERROR("unknown product id: 0x%x\n", version);
  64. return -EINVAL;
  65. }
  66. DRM_INFO("found ARM HDLCD version r%dp%d\n",
  67. (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
  68. version & HDLCD_VERSION_MINOR_MASK);
  69. /* Get the optional framebuffer memory resource */
  70. ret = of_reserved_mem_device_init(drm->dev);
  71. if (ret && ret != -ENODEV)
  72. return ret;
  73. ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
  74. if (ret)
  75. goto setup_fail;
  76. ret = hdlcd_setup_crtc(drm);
  77. if (ret < 0) {
  78. DRM_ERROR("failed to create crtc\n");
  79. goto setup_fail;
  80. }
  81. ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
  82. if (ret < 0) {
  83. DRM_ERROR("failed to install IRQ handler\n");
  84. goto irq_fail;
  85. }
  86. return 0;
  87. irq_fail:
  88. drm_crtc_cleanup(&hdlcd->crtc);
  89. setup_fail:
  90. of_reserved_mem_device_release(drm->dev);
  91. return ret;
  92. }
  93. static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
  94. .fb_create = drm_gem_fb_create,
  95. .atomic_check = drm_atomic_helper_check,
  96. .atomic_commit = drm_atomic_helper_commit,
  97. };
  98. static void hdlcd_setup_mode_config(struct drm_device *drm)
  99. {
  100. drm_mode_config_init(drm);
  101. drm->mode_config.min_width = 0;
  102. drm->mode_config.min_height = 0;
  103. drm->mode_config.max_width = HDLCD_MAX_XRES;
  104. drm->mode_config.max_height = HDLCD_MAX_YRES;
  105. drm->mode_config.funcs = &hdlcd_mode_config_funcs;
  106. }
  107. static irqreturn_t hdlcd_irq(int irq, void *arg)
  108. {
  109. struct drm_device *drm = arg;
  110. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  111. unsigned long irq_status;
  112. irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
  113. #ifdef CONFIG_DEBUG_FS
  114. if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
  115. atomic_inc(&hdlcd->buffer_underrun_count);
  116. if (irq_status & HDLCD_INTERRUPT_DMA_END)
  117. atomic_inc(&hdlcd->dma_end_count);
  118. if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
  119. atomic_inc(&hdlcd->bus_error_count);
  120. if (irq_status & HDLCD_INTERRUPT_VSYNC)
  121. atomic_inc(&hdlcd->vsync_count);
  122. #endif
  123. if (irq_status & HDLCD_INTERRUPT_VSYNC)
  124. drm_crtc_handle_vblank(&hdlcd->crtc);
  125. /* acknowledge interrupt(s) */
  126. hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
  127. return IRQ_HANDLED;
  128. }
  129. static void hdlcd_irq_preinstall(struct drm_device *drm)
  130. {
  131. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  132. /* Ensure interrupts are disabled */
  133. hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
  134. hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
  135. }
  136. static int hdlcd_irq_postinstall(struct drm_device *drm)
  137. {
  138. #ifdef CONFIG_DEBUG_FS
  139. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  140. unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
  141. /* enable debug interrupts */
  142. irq_mask |= HDLCD_DEBUG_INT_MASK;
  143. hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
  144. #endif
  145. return 0;
  146. }
  147. static void hdlcd_irq_uninstall(struct drm_device *drm)
  148. {
  149. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  150. /* disable all the interrupts that we might have enabled */
  151. unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
  152. #ifdef CONFIG_DEBUG_FS
  153. /* disable debug interrupts */
  154. irq_mask &= ~HDLCD_DEBUG_INT_MASK;
  155. #endif
  156. /* disable vsync interrupts */
  157. irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
  158. hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
  159. }
  160. #ifdef CONFIG_DEBUG_FS
  161. static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
  162. {
  163. struct drm_info_node *node = (struct drm_info_node *)m->private;
  164. struct drm_device *drm = node->minor->dev;
  165. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  166. seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
  167. seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
  168. seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
  169. seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
  170. return 0;
  171. }
  172. static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
  173. {
  174. struct drm_info_node *node = (struct drm_info_node *)m->private;
  175. struct drm_device *drm = node->minor->dev;
  176. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  177. unsigned long clkrate = clk_get_rate(hdlcd->clk);
  178. unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
  179. seq_printf(m, "hw : %lu\n", clkrate);
  180. seq_printf(m, "mode: %lu\n", mode_clock);
  181. return 0;
  182. }
  183. static struct drm_info_list hdlcd_debugfs_list[] = {
  184. { "interrupt_count", hdlcd_show_underrun_count, 0 },
  185. { "clocks", hdlcd_show_pxlclock, 0 },
  186. };
  187. static void hdlcd_debugfs_init(struct drm_minor *minor)
  188. {
  189. drm_debugfs_create_files(hdlcd_debugfs_list,
  190. ARRAY_SIZE(hdlcd_debugfs_list),
  191. minor->debugfs_root, minor);
  192. }
  193. #endif
  194. DEFINE_DRM_GEM_CMA_FOPS(fops);
  195. static struct drm_driver hdlcd_driver = {
  196. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  197. .irq_handler = hdlcd_irq,
  198. .irq_preinstall = hdlcd_irq_preinstall,
  199. .irq_postinstall = hdlcd_irq_postinstall,
  200. .irq_uninstall = hdlcd_irq_uninstall,
  201. DRM_GEM_CMA_DRIVER_OPS,
  202. #ifdef CONFIG_DEBUG_FS
  203. .debugfs_init = hdlcd_debugfs_init,
  204. #endif
  205. .fops = &fops,
  206. .name = "hdlcd",
  207. .desc = "ARM HDLCD Controller DRM",
  208. .date = "20151021",
  209. .major = 1,
  210. .minor = 0,
  211. };
  212. static int hdlcd_drm_bind(struct device *dev)
  213. {
  214. struct drm_device *drm;
  215. struct hdlcd_drm_private *hdlcd;
  216. int ret;
  217. hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
  218. if (!hdlcd)
  219. return -ENOMEM;
  220. drm = drm_dev_alloc(&hdlcd_driver, dev);
  221. if (IS_ERR(drm))
  222. return PTR_ERR(drm);
  223. drm->dev_private = hdlcd;
  224. dev_set_drvdata(dev, drm);
  225. hdlcd_setup_mode_config(drm);
  226. ret = hdlcd_load(drm, 0);
  227. if (ret)
  228. goto err_free;
  229. /* Set the CRTC's port so that the encoder component can find it */
  230. hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
  231. ret = component_bind_all(dev, drm);
  232. if (ret) {
  233. DRM_ERROR("Failed to bind all components\n");
  234. goto err_unload;
  235. }
  236. ret = pm_runtime_set_active(dev);
  237. if (ret)
  238. goto err_pm_active;
  239. pm_runtime_enable(dev);
  240. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  241. if (ret < 0) {
  242. DRM_ERROR("failed to initialise vblank\n");
  243. goto err_vblank;
  244. }
  245. drm_mode_config_reset(drm);
  246. drm_kms_helper_poll_init(drm);
  247. ret = drm_dev_register(drm, 0);
  248. if (ret)
  249. goto err_register;
  250. drm_fbdev_generic_setup(drm, 32);
  251. return 0;
  252. err_register:
  253. drm_kms_helper_poll_fini(drm);
  254. err_vblank:
  255. pm_runtime_disable(drm->dev);
  256. err_pm_active:
  257. drm_atomic_helper_shutdown(drm);
  258. component_unbind_all(dev, drm);
  259. err_unload:
  260. of_node_put(hdlcd->crtc.port);
  261. hdlcd->crtc.port = NULL;
  262. drm_irq_uninstall(drm);
  263. of_reserved_mem_device_release(drm->dev);
  264. err_free:
  265. drm_mode_config_cleanup(drm);
  266. dev_set_drvdata(dev, NULL);
  267. drm_dev_put(drm);
  268. return ret;
  269. }
  270. static void hdlcd_drm_unbind(struct device *dev)
  271. {
  272. struct drm_device *drm = dev_get_drvdata(dev);
  273. struct hdlcd_drm_private *hdlcd = drm->dev_private;
  274. drm_dev_unregister(drm);
  275. drm_kms_helper_poll_fini(drm);
  276. component_unbind_all(dev, drm);
  277. of_node_put(hdlcd->crtc.port);
  278. hdlcd->crtc.port = NULL;
  279. pm_runtime_get_sync(dev);
  280. drm_atomic_helper_shutdown(drm);
  281. drm_irq_uninstall(drm);
  282. pm_runtime_put(dev);
  283. if (pm_runtime_enabled(dev))
  284. pm_runtime_disable(dev);
  285. of_reserved_mem_device_release(dev);
  286. drm_mode_config_cleanup(drm);
  287. drm->dev_private = NULL;
  288. dev_set_drvdata(dev, NULL);
  289. drm_dev_put(drm);
  290. }
  291. static const struct component_master_ops hdlcd_master_ops = {
  292. .bind = hdlcd_drm_bind,
  293. .unbind = hdlcd_drm_unbind,
  294. };
  295. static int compare_dev(struct device *dev, void *data)
  296. {
  297. return dev->of_node == data;
  298. }
  299. static int hdlcd_probe(struct platform_device *pdev)
  300. {
  301. struct device_node *port;
  302. struct component_match *match = NULL;
  303. /* there is only one output port inside each device, find it */
  304. port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
  305. if (!port)
  306. return -ENODEV;
  307. drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
  308. of_node_put(port);
  309. return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
  310. match);
  311. }
  312. static int hdlcd_remove(struct platform_device *pdev)
  313. {
  314. component_master_del(&pdev->dev, &hdlcd_master_ops);
  315. return 0;
  316. }
  317. static const struct of_device_id hdlcd_of_match[] = {
  318. { .compatible = "arm,hdlcd" },
  319. {},
  320. };
  321. MODULE_DEVICE_TABLE(of, hdlcd_of_match);
  322. static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
  323. {
  324. struct drm_device *drm = dev_get_drvdata(dev);
  325. return drm_mode_config_helper_suspend(drm);
  326. }
  327. static int __maybe_unused hdlcd_pm_resume(struct device *dev)
  328. {
  329. struct drm_device *drm = dev_get_drvdata(dev);
  330. drm_mode_config_helper_resume(drm);
  331. return 0;
  332. }
  333. static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
  334. static struct platform_driver hdlcd_platform_driver = {
  335. .probe = hdlcd_probe,
  336. .remove = hdlcd_remove,
  337. .driver = {
  338. .name = "hdlcd",
  339. .pm = &hdlcd_pm_ops,
  340. .of_match_table = hdlcd_of_match,
  341. },
  342. };
  343. module_platform_driver(hdlcd_platform_driver);
  344. MODULE_AUTHOR("Liviu Dudau");
  345. MODULE_DESCRIPTION("ARM HDLCD DRM driver");
  346. MODULE_LICENSE("GPL v2");