fsi-master-ast-cf.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright 2018 IBM Corp
  3. /*
  4. * A FSI master controller, using a simple GPIO bit-banging interface
  5. */
  6. #include <linux/crc4.h>
  7. #include <linux/delay.h>
  8. #include <linux/device.h>
  9. #include <linux/fsi.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/io.h>
  12. #include <linux/irqflags.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/regmap.h>
  18. #include <linux/firmware.h>
  19. #include <linux/gpio/aspeed.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/of_address.h>
  22. #include <linux/genalloc.h>
  23. #include "fsi-master.h"
  24. #include "cf-fsi-fw.h"
  25. #define FW_FILE_NAME "cf-fsi-fw.bin"
  26. /* Common SCU based coprocessor control registers */
  27. #define SCU_COPRO_CTRL 0x100
  28. #define SCU_COPRO_RESET 0x00000002
  29. #define SCU_COPRO_CLK_EN 0x00000001
  30. /* AST2500 specific ones */
  31. #define SCU_2500_COPRO_SEG0 0x104
  32. #define SCU_2500_COPRO_SEG1 0x108
  33. #define SCU_2500_COPRO_SEG2 0x10c
  34. #define SCU_2500_COPRO_SEG3 0x110
  35. #define SCU_2500_COPRO_SEG4 0x114
  36. #define SCU_2500_COPRO_SEG5 0x118
  37. #define SCU_2500_COPRO_SEG6 0x11c
  38. #define SCU_2500_COPRO_SEG7 0x120
  39. #define SCU_2500_COPRO_SEG8 0x124
  40. #define SCU_2500_COPRO_SEG_SWAP 0x00000001
  41. #define SCU_2500_COPRO_CACHE_CTL 0x128
  42. #define SCU_2500_COPRO_CACHE_EN 0x00000001
  43. #define SCU_2500_COPRO_SEG0_CACHE_EN 0x00000002
  44. #define SCU_2500_COPRO_SEG1_CACHE_EN 0x00000004
  45. #define SCU_2500_COPRO_SEG2_CACHE_EN 0x00000008
  46. #define SCU_2500_COPRO_SEG3_CACHE_EN 0x00000010
  47. #define SCU_2500_COPRO_SEG4_CACHE_EN 0x00000020
  48. #define SCU_2500_COPRO_SEG5_CACHE_EN 0x00000040
  49. #define SCU_2500_COPRO_SEG6_CACHE_EN 0x00000080
  50. #define SCU_2500_COPRO_SEG7_CACHE_EN 0x00000100
  51. #define SCU_2500_COPRO_SEG8_CACHE_EN 0x00000200
  52. #define SCU_2400_COPRO_SEG0 0x104
  53. #define SCU_2400_COPRO_SEG2 0x108
  54. #define SCU_2400_COPRO_SEG4 0x10c
  55. #define SCU_2400_COPRO_SEG6 0x110
  56. #define SCU_2400_COPRO_SEG8 0x114
  57. #define SCU_2400_COPRO_SEG_SWAP 0x80000000
  58. #define SCU_2400_COPRO_CACHE_CTL 0x118
  59. #define SCU_2400_COPRO_CACHE_EN 0x00000001
  60. #define SCU_2400_COPRO_SEG0_CACHE_EN 0x00000002
  61. #define SCU_2400_COPRO_SEG2_CACHE_EN 0x00000004
  62. #define SCU_2400_COPRO_SEG4_CACHE_EN 0x00000008
  63. #define SCU_2400_COPRO_SEG6_CACHE_EN 0x00000010
  64. #define SCU_2400_COPRO_SEG8_CACHE_EN 0x00000020
  65. /* CVIC registers */
  66. #define CVIC_EN_REG 0x10
  67. #define CVIC_TRIG_REG 0x18
  68. /*
  69. * System register base address (needed for configuring the
  70. * coldfire maps)
  71. */
  72. #define SYSREG_BASE 0x1e600000
  73. /* Amount of SRAM required */
  74. #define SRAM_SIZE 0x1000
  75. #define LAST_ADDR_INVALID 0x1
  76. struct fsi_master_acf {
  77. struct fsi_master master;
  78. struct device *dev;
  79. struct regmap *scu;
  80. struct mutex lock; /* mutex for command ordering */
  81. struct gpio_desc *gpio_clk;
  82. struct gpio_desc *gpio_data;
  83. struct gpio_desc *gpio_trans; /* Voltage translator */
  84. struct gpio_desc *gpio_enable; /* FSI enable */
  85. struct gpio_desc *gpio_mux; /* Mux control */
  86. uint16_t gpio_clk_vreg;
  87. uint16_t gpio_clk_dreg;
  88. uint16_t gpio_dat_vreg;
  89. uint16_t gpio_dat_dreg;
  90. uint16_t gpio_tra_vreg;
  91. uint16_t gpio_tra_dreg;
  92. uint8_t gpio_clk_bit;
  93. uint8_t gpio_dat_bit;
  94. uint8_t gpio_tra_bit;
  95. uint32_t cf_mem_addr;
  96. size_t cf_mem_size;
  97. void __iomem *cf_mem;
  98. void __iomem *cvic;
  99. struct gen_pool *sram_pool;
  100. void __iomem *sram;
  101. bool is_ast2500;
  102. bool external_mode;
  103. bool trace_enabled;
  104. uint32_t last_addr;
  105. uint8_t t_send_delay;
  106. uint8_t t_echo_delay;
  107. uint32_t cvic_sw_irq;
  108. };
  109. #define to_fsi_master_acf(m) container_of(m, struct fsi_master_acf, master)
  110. struct fsi_msg {
  111. uint64_t msg;
  112. uint8_t bits;
  113. };
  114. #define CREATE_TRACE_POINTS
  115. #include <trace/events/fsi_master_ast_cf.h>
  116. static void msg_push_bits(struct fsi_msg *msg, uint64_t data, int bits)
  117. {
  118. msg->msg <<= bits;
  119. msg->msg |= data & ((1ull << bits) - 1);
  120. msg->bits += bits;
  121. }
  122. static void msg_push_crc(struct fsi_msg *msg)
  123. {
  124. uint8_t crc;
  125. int top;
  126. top = msg->bits & 0x3;
  127. /* start bit, and any non-aligned top bits */
  128. crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
  129. /* aligned bits */
  130. crc = crc4(crc, msg->msg, msg->bits - top);
  131. msg_push_bits(msg, crc, 4);
  132. }
  133. static void msg_finish_cmd(struct fsi_msg *cmd)
  134. {
  135. /* Left align message */
  136. cmd->msg <<= (64 - cmd->bits);
  137. }
  138. static bool check_same_address(struct fsi_master_acf *master, int id,
  139. uint32_t addr)
  140. {
  141. /* this will also handle LAST_ADDR_INVALID */
  142. return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
  143. }
  144. static bool check_relative_address(struct fsi_master_acf *master, int id,
  145. uint32_t addr, uint32_t *rel_addrp)
  146. {
  147. uint32_t last_addr = master->last_addr;
  148. int32_t rel_addr;
  149. if (last_addr == LAST_ADDR_INVALID)
  150. return false;
  151. /* We may be in 23-bit addressing mode, which uses the id as the
  152. * top two address bits. So, if we're referencing a different ID,
  153. * use absolute addresses.
  154. */
  155. if (((last_addr >> 21) & 0x3) != id)
  156. return false;
  157. /* remove the top two bits from any 23-bit addressing */
  158. last_addr &= (1 << 21) - 1;
  159. /* We know that the addresses are limited to 21 bits, so this won't
  160. * overflow the signed rel_addr */
  161. rel_addr = addr - last_addr;
  162. if (rel_addr > 255 || rel_addr < -256)
  163. return false;
  164. *rel_addrp = (uint32_t)rel_addr;
  165. return true;
  166. }
  167. static void last_address_update(struct fsi_master_acf *master,
  168. int id, bool valid, uint32_t addr)
  169. {
  170. if (!valid)
  171. master->last_addr = LAST_ADDR_INVALID;
  172. else
  173. master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
  174. }
  175. /*
  176. * Encode an Absolute/Relative/Same Address command
  177. */
  178. static void build_ar_command(struct fsi_master_acf *master,
  179. struct fsi_msg *cmd, uint8_t id,
  180. uint32_t addr, size_t size,
  181. const void *data)
  182. {
  183. int i, addr_bits, opcode_bits;
  184. bool write = !!data;
  185. uint8_t ds, opcode;
  186. uint32_t rel_addr;
  187. cmd->bits = 0;
  188. cmd->msg = 0;
  189. /* we have 21 bits of address max */
  190. addr &= ((1 << 21) - 1);
  191. /* cmd opcodes are variable length - SAME_AR is only two bits */
  192. opcode_bits = 3;
  193. if (check_same_address(master, id, addr)) {
  194. /* we still address the byte offset within the word */
  195. addr_bits = 2;
  196. opcode_bits = 2;
  197. opcode = FSI_CMD_SAME_AR;
  198. trace_fsi_master_acf_cmd_same_addr(master);
  199. } else if (check_relative_address(master, id, addr, &rel_addr)) {
  200. /* 8 bits plus sign */
  201. addr_bits = 9;
  202. addr = rel_addr;
  203. opcode = FSI_CMD_REL_AR;
  204. trace_fsi_master_acf_cmd_rel_addr(master, rel_addr);
  205. } else {
  206. addr_bits = 21;
  207. opcode = FSI_CMD_ABS_AR;
  208. trace_fsi_master_acf_cmd_abs_addr(master, addr);
  209. }
  210. /*
  211. * The read/write size is encoded in the lower bits of the address
  212. * (as it must be naturally-aligned), and the following ds bit.
  213. *
  214. * size addr:1 addr:0 ds
  215. * 1 x x 0
  216. * 2 x 0 1
  217. * 4 0 1 1
  218. *
  219. */
  220. ds = size > 1 ? 1 : 0;
  221. addr &= ~(size - 1);
  222. if (size == 4)
  223. addr |= 1;
  224. msg_push_bits(cmd, id, 2);
  225. msg_push_bits(cmd, opcode, opcode_bits);
  226. msg_push_bits(cmd, write ? 0 : 1, 1);
  227. msg_push_bits(cmd, addr, addr_bits);
  228. msg_push_bits(cmd, ds, 1);
  229. for (i = 0; write && i < size; i++)
  230. msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
  231. msg_push_crc(cmd);
  232. msg_finish_cmd(cmd);
  233. }
  234. static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id)
  235. {
  236. cmd->bits = 0;
  237. cmd->msg = 0;
  238. msg_push_bits(cmd, slave_id, 2);
  239. msg_push_bits(cmd, FSI_CMD_DPOLL, 3);
  240. msg_push_crc(cmd);
  241. msg_finish_cmd(cmd);
  242. }
  243. static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id)
  244. {
  245. cmd->bits = 0;
  246. cmd->msg = 0;
  247. msg_push_bits(cmd, slave_id, 2);
  248. msg_push_bits(cmd, FSI_CMD_EPOLL, 3);
  249. msg_push_crc(cmd);
  250. msg_finish_cmd(cmd);
  251. }
  252. static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id)
  253. {
  254. cmd->bits = 0;
  255. cmd->msg = 0;
  256. msg_push_bits(cmd, slave_id, 2);
  257. msg_push_bits(cmd, FSI_CMD_TERM, 6);
  258. msg_push_crc(cmd);
  259. msg_finish_cmd(cmd);
  260. }
  261. static int do_copro_command(struct fsi_master_acf *master, uint32_t op)
  262. {
  263. uint32_t timeout = 10000000;
  264. uint8_t stat;
  265. trace_fsi_master_acf_copro_command(master, op);
  266. /* Send command */
  267. iowrite32be(op, master->sram + CMD_STAT_REG);
  268. /* Ring doorbell if any */
  269. if (master->cvic)
  270. iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
  271. /* Wait for status to indicate completion (or error) */
  272. do {
  273. if (timeout-- == 0) {
  274. dev_warn(master->dev,
  275. "Timeout waiting for coprocessor completion\n");
  276. return -ETIMEDOUT;
  277. }
  278. stat = ioread8(master->sram + CMD_STAT_REG);
  279. } while(stat < STAT_COMPLETE || stat == 0xff);
  280. if (stat == STAT_COMPLETE)
  281. return 0;
  282. switch(stat) {
  283. case STAT_ERR_INVAL_CMD:
  284. return -EINVAL;
  285. case STAT_ERR_INVAL_IRQ:
  286. return -EIO;
  287. case STAT_ERR_MTOE:
  288. return -ESHUTDOWN;
  289. }
  290. return -ENXIO;
  291. }
  292. static int clock_zeros(struct fsi_master_acf *master, int count)
  293. {
  294. while (count) {
  295. int rc, lcnt = min(count, 255);
  296. rc = do_copro_command(master,
  297. CMD_IDLE_CLOCKS | (lcnt << CMD_REG_CLEN_SHIFT));
  298. if (rc)
  299. return rc;
  300. count -= lcnt;
  301. }
  302. return 0;
  303. }
  304. static int send_request(struct fsi_master_acf *master, struct fsi_msg *cmd,
  305. unsigned int resp_bits)
  306. {
  307. uint32_t op;
  308. trace_fsi_master_acf_send_request(master, cmd, resp_bits);
  309. /* Store message into SRAM */
  310. iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA);
  311. iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4);
  312. op = CMD_COMMAND;
  313. op |= cmd->bits << CMD_REG_CLEN_SHIFT;
  314. if (resp_bits)
  315. op |= resp_bits << CMD_REG_RLEN_SHIFT;
  316. return do_copro_command(master, op);
  317. }
  318. static int read_copro_response(struct fsi_master_acf *master, uint8_t size,
  319. uint32_t *response, u8 *tag)
  320. {
  321. uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf;
  322. uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf;
  323. uint32_t rdata = 0;
  324. uint32_t crc;
  325. uint8_t ack;
  326. *tag = ack = rtag & 3;
  327. /* we have a whole message now; check CRC */
  328. crc = crc4(0, 1, 1);
  329. crc = crc4(crc, rtag, 4);
  330. if (ack == FSI_RESP_ACK && size) {
  331. rdata = ioread32be(master->sram + RSP_DATA);
  332. crc = crc4(crc, rdata, size);
  333. if (response)
  334. *response = rdata;
  335. }
  336. crc = crc4(crc, rcrc, 4);
  337. trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0);
  338. if (crc) {
  339. /*
  340. * Check if it's all 1's or all 0's, that probably means
  341. * the host is off
  342. */
  343. if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0))
  344. return -ENODEV;
  345. dev_dbg(master->dev, "Bad response CRC !\n");
  346. return -EAGAIN;
  347. }
  348. return 0;
  349. }
  350. static int send_term(struct fsi_master_acf *master, uint8_t slave)
  351. {
  352. struct fsi_msg cmd;
  353. uint8_t tag;
  354. int rc;
  355. build_term_command(&cmd, slave);
  356. rc = send_request(master, &cmd, 0);
  357. if (rc) {
  358. dev_warn(master->dev, "Error %d sending term\n", rc);
  359. return rc;
  360. }
  361. rc = read_copro_response(master, 0, NULL, &tag);
  362. if (rc < 0) {
  363. dev_err(master->dev,
  364. "TERM failed; lost communication with slave\n");
  365. return -EIO;
  366. } else if (tag != FSI_RESP_ACK) {
  367. dev_err(master->dev, "TERM failed; response %d\n", tag);
  368. return -EIO;
  369. }
  370. return 0;
  371. }
  372. static void dump_ucode_trace(struct fsi_master_acf *master)
  373. {
  374. char trbuf[52];
  375. char *p;
  376. int i;
  377. dev_dbg(master->dev,
  378. "CMDSTAT:%08x RTAG=%02x RCRC=%02x RDATA=%02x #INT=%08x\n",
  379. ioread32be(master->sram + CMD_STAT_REG),
  380. ioread8(master->sram + STAT_RTAG),
  381. ioread8(master->sram + STAT_RCRC),
  382. ioread32be(master->sram + RSP_DATA),
  383. ioread32be(master->sram + INT_CNT));
  384. for (i = 0; i < 512; i++) {
  385. uint8_t v;
  386. if ((i % 16) == 0)
  387. p = trbuf;
  388. v = ioread8(master->sram + TRACEBUF + i);
  389. p += sprintf(p, "%02x ", v);
  390. if (((i % 16) == 15) || v == TR_END)
  391. dev_dbg(master->dev, "%s\n", trbuf);
  392. if (v == TR_END)
  393. break;
  394. }
  395. }
  396. static int handle_response(struct fsi_master_acf *master,
  397. uint8_t slave, uint8_t size, void *data)
  398. {
  399. int busy_count = 0, rc;
  400. int crc_err_retries = 0;
  401. struct fsi_msg cmd;
  402. uint32_t response;
  403. uint8_t tag;
  404. retry:
  405. rc = read_copro_response(master, size, &response, &tag);
  406. /* Handle retries on CRC errors */
  407. if (rc == -EAGAIN) {
  408. /* Too many retries ? */
  409. if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
  410. /*
  411. * Pass it up as a -EIO otherwise upper level will retry
  412. * the whole command which isn't what we want here.
  413. */
  414. rc = -EIO;
  415. goto bail;
  416. }
  417. trace_fsi_master_acf_crc_rsp_error(master, crc_err_retries);
  418. if (master->trace_enabled)
  419. dump_ucode_trace(master);
  420. rc = clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS);
  421. if (rc) {
  422. dev_warn(master->dev,
  423. "Error %d clocking zeros for E_POLL\n", rc);
  424. return rc;
  425. }
  426. build_epoll_command(&cmd, slave);
  427. rc = send_request(master, &cmd, size);
  428. if (rc) {
  429. dev_warn(master->dev, "Error %d sending E_POLL\n", rc);
  430. return -EIO;
  431. }
  432. goto retry;
  433. }
  434. if (rc)
  435. return rc;
  436. switch (tag) {
  437. case FSI_RESP_ACK:
  438. if (size && data) {
  439. if (size == 32)
  440. *(__be32 *)data = cpu_to_be32(response);
  441. else if (size == 16)
  442. *(__be16 *)data = cpu_to_be16(response);
  443. else
  444. *(u8 *)data = response;
  445. }
  446. break;
  447. case FSI_RESP_BUSY:
  448. /*
  449. * Its necessary to clock slave before issuing
  450. * d-poll, not indicated in the hardware protocol
  451. * spec. < 20 clocks causes slave to hang, 21 ok.
  452. */
  453. dev_dbg(master->dev, "Busy, retrying...\n");
  454. if (master->trace_enabled)
  455. dump_ucode_trace(master);
  456. rc = clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
  457. if (rc) {
  458. dev_warn(master->dev,
  459. "Error %d clocking zeros for D_POLL\n", rc);
  460. break;
  461. }
  462. if (busy_count++ < FSI_MASTER_MAX_BUSY) {
  463. build_dpoll_command(&cmd, slave);
  464. rc = send_request(master, &cmd, size);
  465. if (rc) {
  466. dev_warn(master->dev, "Error %d sending D_POLL\n", rc);
  467. break;
  468. }
  469. goto retry;
  470. }
  471. dev_dbg(master->dev,
  472. "ERR slave is stuck in busy state, issuing TERM\n");
  473. send_term(master, slave);
  474. rc = -EIO;
  475. break;
  476. case FSI_RESP_ERRA:
  477. dev_dbg(master->dev, "ERRA received\n");
  478. if (master->trace_enabled)
  479. dump_ucode_trace(master);
  480. rc = -EIO;
  481. break;
  482. case FSI_RESP_ERRC:
  483. dev_dbg(master->dev, "ERRC received\n");
  484. if (master->trace_enabled)
  485. dump_ucode_trace(master);
  486. rc = -EAGAIN;
  487. break;
  488. }
  489. bail:
  490. if (busy_count > 0) {
  491. trace_fsi_master_acf_poll_response_busy(master, busy_count);
  492. }
  493. return rc;
  494. }
  495. static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave,
  496. struct fsi_msg *cmd, size_t resp_len, void *resp)
  497. {
  498. int rc = -EAGAIN, retries = 0;
  499. resp_len <<= 3;
  500. while ((retries++) < FSI_CRC_ERR_RETRIES) {
  501. rc = send_request(master, cmd, resp_len);
  502. if (rc) {
  503. if (rc != -ESHUTDOWN)
  504. dev_warn(master->dev, "Error %d sending command\n", rc);
  505. break;
  506. }
  507. rc = handle_response(master, slave, resp_len, resp);
  508. if (rc != -EAGAIN)
  509. break;
  510. rc = -EIO;
  511. dev_dbg(master->dev, "ECRC retry %d\n", retries);
  512. /* Pace it a bit before retry */
  513. msleep(1);
  514. }
  515. return rc;
  516. }
  517. static int fsi_master_acf_read(struct fsi_master *_master, int link,
  518. uint8_t id, uint32_t addr, void *val,
  519. size_t size)
  520. {
  521. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  522. struct fsi_msg cmd;
  523. int rc;
  524. if (link != 0)
  525. return -ENODEV;
  526. mutex_lock(&master->lock);
  527. dev_dbg(master->dev, "read id %d addr %x size %zd\n", id, addr, size);
  528. build_ar_command(master, &cmd, id, addr, size, NULL);
  529. rc = fsi_master_acf_xfer(master, id, &cmd, size, val);
  530. last_address_update(master, id, rc == 0, addr);
  531. if (rc)
  532. dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n",
  533. id, addr, rc);
  534. mutex_unlock(&master->lock);
  535. return rc;
  536. }
  537. static int fsi_master_acf_write(struct fsi_master *_master, int link,
  538. uint8_t id, uint32_t addr, const void *val,
  539. size_t size)
  540. {
  541. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  542. struct fsi_msg cmd;
  543. int rc;
  544. if (link != 0)
  545. return -ENODEV;
  546. mutex_lock(&master->lock);
  547. build_ar_command(master, &cmd, id, addr, size, val);
  548. dev_dbg(master->dev, "write id %d addr %x size %zd raw_data: %08x\n",
  549. id, addr, size, *(uint32_t *)val);
  550. rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
  551. last_address_update(master, id, rc == 0, addr);
  552. if (rc)
  553. dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n",
  554. id, addr, rc);
  555. mutex_unlock(&master->lock);
  556. return rc;
  557. }
  558. static int fsi_master_acf_term(struct fsi_master *_master,
  559. int link, uint8_t id)
  560. {
  561. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  562. struct fsi_msg cmd;
  563. int rc;
  564. if (link != 0)
  565. return -ENODEV;
  566. mutex_lock(&master->lock);
  567. build_term_command(&cmd, id);
  568. dev_dbg(master->dev, "term id %d\n", id);
  569. rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
  570. last_address_update(master, id, false, 0);
  571. mutex_unlock(&master->lock);
  572. return rc;
  573. }
  574. static int fsi_master_acf_break(struct fsi_master *_master, int link)
  575. {
  576. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  577. int rc;
  578. if (link != 0)
  579. return -ENODEV;
  580. mutex_lock(&master->lock);
  581. if (master->external_mode) {
  582. mutex_unlock(&master->lock);
  583. return -EBUSY;
  584. }
  585. dev_dbg(master->dev, "sending BREAK\n");
  586. rc = do_copro_command(master, CMD_BREAK);
  587. last_address_update(master, 0, false, 0);
  588. mutex_unlock(&master->lock);
  589. /* Wait for logic reset to take effect */
  590. udelay(200);
  591. return rc;
  592. }
  593. static void reset_cf(struct fsi_master_acf *master)
  594. {
  595. regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_RESET);
  596. usleep_range(20,20);
  597. regmap_write(master->scu, SCU_COPRO_CTRL, 0);
  598. usleep_range(20,20);
  599. }
  600. static void start_cf(struct fsi_master_acf *master)
  601. {
  602. regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_CLK_EN);
  603. }
  604. static void setup_ast2500_cf_maps(struct fsi_master_acf *master)
  605. {
  606. /*
  607. * Note about byteswap setting: the bus is wired backwards,
  608. * so setting the byteswap bit actually makes the ColdFire
  609. * work "normally" for a BE processor, ie, put the MSB in
  610. * the lowest address byte.
  611. *
  612. * We thus need to set the bit for our main memory which
  613. * contains our program code. We create two mappings for
  614. * the register, one with each setting.
  615. *
  616. * Segments 2 and 3 has a "swapped" mapping (BE)
  617. * and 6 and 7 have a non-swapped mapping (LE) which allows
  618. * us to avoid byteswapping register accesses since the
  619. * registers are all LE.
  620. */
  621. /* Setup segment 0 to our memory region */
  622. regmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr |
  623. SCU_2500_COPRO_SEG_SWAP);
  624. /* Segments 2 and 3 to sysregs with byteswap (for SRAM) */
  625. regmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE |
  626. SCU_2500_COPRO_SEG_SWAP);
  627. regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |
  628. SCU_2500_COPRO_SEG_SWAP);
  629. /* And segment 6 and 7 to sysregs no byteswap */
  630. regmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE);
  631. regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);
  632. /* Memory cachable, regs and SRAM not cachable */
  633. regmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL,
  634. SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN);
  635. }
  636. static void setup_ast2400_cf_maps(struct fsi_master_acf *master)
  637. {
  638. /* Setup segment 0 to our memory region */
  639. regmap_write(master->scu, SCU_2400_COPRO_SEG0, master->cf_mem_addr |
  640. SCU_2400_COPRO_SEG_SWAP);
  641. /* Segments 2 to sysregs with byteswap (for SRAM) */
  642. regmap_write(master->scu, SCU_2400_COPRO_SEG2, SYSREG_BASE |
  643. SCU_2400_COPRO_SEG_SWAP);
  644. /* And segment 6 to sysregs no byteswap */
  645. regmap_write(master->scu, SCU_2400_COPRO_SEG6, SYSREG_BASE);
  646. /* Memory cachable, regs and SRAM not cachable */
  647. regmap_write(master->scu, SCU_2400_COPRO_CACHE_CTL,
  648. SCU_2400_COPRO_SEG0_CACHE_EN | SCU_2400_COPRO_CACHE_EN);
  649. }
  650. static void setup_common_fw_config(struct fsi_master_acf *master,
  651. void __iomem *base)
  652. {
  653. iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR);
  654. iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR);
  655. iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR);
  656. iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR);
  657. iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR);
  658. iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR);
  659. iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT);
  660. iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT);
  661. iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT);
  662. }
  663. static void setup_ast2500_fw_config(struct fsi_master_acf *master)
  664. {
  665. void __iomem *base = master->cf_mem + HDR_OFFSET;
  666. setup_common_fw_config(master, base);
  667. iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL);
  668. }
  669. static void setup_ast2400_fw_config(struct fsi_master_acf *master)
  670. {
  671. void __iomem *base = master->cf_mem + HDR_OFFSET;
  672. setup_common_fw_config(master, base);
  673. iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL);
  674. }
  675. static int setup_gpios_for_copro(struct fsi_master_acf *master)
  676. {
  677. int rc;
  678. /* This aren't under ColdFire control, just set them up appropriately */
  679. gpiod_direction_output(master->gpio_mux, 1);
  680. gpiod_direction_output(master->gpio_enable, 1);
  681. /* Those are under ColdFire control, let it configure them */
  682. rc = aspeed_gpio_copro_grab_gpio(master->gpio_clk, &master->gpio_clk_vreg,
  683. &master->gpio_clk_dreg, &master->gpio_clk_bit);
  684. if (rc) {
  685. dev_err(master->dev, "failed to assign clock gpio to coprocessor\n");
  686. return rc;
  687. }
  688. rc = aspeed_gpio_copro_grab_gpio(master->gpio_data, &master->gpio_dat_vreg,
  689. &master->gpio_dat_dreg, &master->gpio_dat_bit);
  690. if (rc) {
  691. dev_err(master->dev, "failed to assign data gpio to coprocessor\n");
  692. aspeed_gpio_copro_release_gpio(master->gpio_clk);
  693. return rc;
  694. }
  695. rc = aspeed_gpio_copro_grab_gpio(master->gpio_trans, &master->gpio_tra_vreg,
  696. &master->gpio_tra_dreg, &master->gpio_tra_bit);
  697. if (rc) {
  698. dev_err(master->dev, "failed to assign trans gpio to coprocessor\n");
  699. aspeed_gpio_copro_release_gpio(master->gpio_clk);
  700. aspeed_gpio_copro_release_gpio(master->gpio_data);
  701. return rc;
  702. }
  703. return 0;
  704. }
  705. static void release_copro_gpios(struct fsi_master_acf *master)
  706. {
  707. aspeed_gpio_copro_release_gpio(master->gpio_clk);
  708. aspeed_gpio_copro_release_gpio(master->gpio_data);
  709. aspeed_gpio_copro_release_gpio(master->gpio_trans);
  710. }
  711. static int load_copro_firmware(struct fsi_master_acf *master)
  712. {
  713. const struct firmware *fw;
  714. uint16_t sig = 0, wanted_sig;
  715. const u8 *data;
  716. size_t size = 0;
  717. int rc;
  718. /* Get the binary */
  719. rc = request_firmware(&fw, FW_FILE_NAME, master->dev);
  720. if (rc) {
  721. dev_err(
  722. master->dev, "Error %d to load firmware '%s' !\n",
  723. rc, FW_FILE_NAME);
  724. return rc;
  725. }
  726. /* Which image do we want ? (shared vs. split clock/data GPIOs) */
  727. if (master->gpio_clk_vreg == master->gpio_dat_vreg)
  728. wanted_sig = SYS_SIG_SHARED;
  729. else
  730. wanted_sig = SYS_SIG_SPLIT;
  731. dev_dbg(master->dev, "Looking for image sig %04x\n", wanted_sig);
  732. /* Try to find it */
  733. for (data = fw->data; data < (fw->data + fw->size);) {
  734. sig = be16_to_cpup((__be16 *)(data + HDR_OFFSET + HDR_SYS_SIG));
  735. size = be32_to_cpup((__be32 *)(data + HDR_OFFSET + HDR_FW_SIZE));
  736. if (sig == wanted_sig)
  737. break;
  738. data += size;
  739. }
  740. if (sig != wanted_sig) {
  741. dev_err(master->dev, "Failed to locate image sig %04x in FW blob\n",
  742. wanted_sig);
  743. rc = -ENODEV;
  744. goto release_fw;
  745. }
  746. if (size > master->cf_mem_size) {
  747. dev_err(master->dev, "FW size (%zd) bigger than memory reserve (%zd)\n",
  748. fw->size, master->cf_mem_size);
  749. rc = -ENOMEM;
  750. } else {
  751. memcpy_toio(master->cf_mem, data, size);
  752. }
  753. release_fw:
  754. release_firmware(fw);
  755. return rc;
  756. }
  757. static int check_firmware_image(struct fsi_master_acf *master)
  758. {
  759. uint32_t fw_vers, fw_api, fw_options;
  760. fw_vers = ioread16be(master->cf_mem + HDR_OFFSET + HDR_FW_VERS);
  761. fw_api = ioread16be(master->cf_mem + HDR_OFFSET + HDR_API_VERS);
  762. fw_options = ioread32be(master->cf_mem + HDR_OFFSET + HDR_FW_OPTIONS);
  763. master->trace_enabled = !!(fw_options & FW_OPTION_TRACE_EN);
  764. /* Check version and signature */
  765. dev_info(master->dev, "ColdFire initialized, firmware v%d API v%d.%d (trace %s)\n",
  766. fw_vers, fw_api >> 8, fw_api & 0xff,
  767. master->trace_enabled ? "enabled" : "disabled");
  768. if ((fw_api >> 8) != API_VERSION_MAJ) {
  769. dev_err(master->dev, "Unsupported coprocessor API version !\n");
  770. return -ENODEV;
  771. }
  772. return 0;
  773. }
  774. static int copro_enable_sw_irq(struct fsi_master_acf *master)
  775. {
  776. int timeout;
  777. uint32_t val;
  778. /*
  779. * Enable coprocessor interrupt input. I've had problems getting the
  780. * value to stick, so try in a loop
  781. */
  782. for (timeout = 0; timeout < 10; timeout++) {
  783. iowrite32(0x2, master->cvic + CVIC_EN_REG);
  784. val = ioread32(master->cvic + CVIC_EN_REG);
  785. if (val & 2)
  786. break;
  787. msleep(1);
  788. }
  789. if (!(val & 2)) {
  790. dev_err(master->dev, "Failed to enable coprocessor interrupt !\n");
  791. return -ENODEV;
  792. }
  793. return 0;
  794. }
  795. static int fsi_master_acf_setup(struct fsi_master_acf *master)
  796. {
  797. int timeout, rc;
  798. uint32_t val;
  799. /* Make sure the ColdFire is stopped */
  800. reset_cf(master);
  801. /*
  802. * Clear SRAM. This needs to happen before we setup the GPIOs
  803. * as we might start trying to arbitrate as soon as that happens.
  804. */
  805. memset_io(master->sram, 0, SRAM_SIZE);
  806. /* Configure GPIOs */
  807. rc = setup_gpios_for_copro(master);
  808. if (rc)
  809. return rc;
  810. /* Load the firmware into the reserved memory */
  811. rc = load_copro_firmware(master);
  812. if (rc)
  813. return rc;
  814. /* Read signature and check versions */
  815. rc = check_firmware_image(master);
  816. if (rc)
  817. return rc;
  818. /* Setup coldfire memory map */
  819. if (master->is_ast2500) {
  820. setup_ast2500_cf_maps(master);
  821. setup_ast2500_fw_config(master);
  822. } else {
  823. setup_ast2400_cf_maps(master);
  824. setup_ast2400_fw_config(master);
  825. }
  826. /* Start the ColdFire */
  827. start_cf(master);
  828. /* Wait for status register to indicate command completion
  829. * which signals the initialization is complete
  830. */
  831. for (timeout = 0; timeout < 10; timeout++) {
  832. val = ioread8(master->sram + CF_STARTED);
  833. if (val)
  834. break;
  835. msleep(1);
  836. }
  837. if (!val) {
  838. dev_err(master->dev, "Coprocessor startup timeout !\n");
  839. rc = -ENODEV;
  840. goto err;
  841. }
  842. /* Configure echo & send delay */
  843. iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
  844. iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
  845. /* Enable SW interrupt to copro if any */
  846. if (master->cvic) {
  847. rc = copro_enable_sw_irq(master);
  848. if (rc)
  849. goto err;
  850. }
  851. return 0;
  852. err:
  853. /* An error occurred, don't leave the coprocessor running */
  854. reset_cf(master);
  855. /* Release the GPIOs */
  856. release_copro_gpios(master);
  857. return rc;
  858. }
  859. static void fsi_master_acf_terminate(struct fsi_master_acf *master)
  860. {
  861. unsigned long flags;
  862. /*
  863. * A GPIO arbitration requestion could come in while this is
  864. * happening. To avoid problems, we disable interrupts so it
  865. * cannot preempt us on this CPU
  866. */
  867. local_irq_save(flags);
  868. /* Stop the coprocessor */
  869. reset_cf(master);
  870. /* We mark the copro not-started */
  871. iowrite32(0, master->sram + CF_STARTED);
  872. /* We mark the ARB register as having given up arbitration to
  873. * deal with a potential race with the arbitration request
  874. */
  875. iowrite8(ARB_ARM_ACK, master->sram + ARB_REG);
  876. local_irq_restore(flags);
  877. /* Return the GPIOs to the ARM */
  878. release_copro_gpios(master);
  879. }
  880. static void fsi_master_acf_setup_external(struct fsi_master_acf *master)
  881. {
  882. /* Setup GPIOs for external FSI master (FSP box) */
  883. gpiod_direction_output(master->gpio_mux, 0);
  884. gpiod_direction_output(master->gpio_trans, 0);
  885. gpiod_direction_output(master->gpio_enable, 1);
  886. gpiod_direction_input(master->gpio_clk);
  887. gpiod_direction_input(master->gpio_data);
  888. }
  889. static int fsi_master_acf_link_enable(struct fsi_master *_master, int link,
  890. bool enable)
  891. {
  892. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  893. int rc = -EBUSY;
  894. if (link != 0)
  895. return -ENODEV;
  896. mutex_lock(&master->lock);
  897. if (!master->external_mode) {
  898. gpiod_set_value(master->gpio_enable, enable ? 1 : 0);
  899. rc = 0;
  900. }
  901. mutex_unlock(&master->lock);
  902. return rc;
  903. }
  904. static int fsi_master_acf_link_config(struct fsi_master *_master, int link,
  905. u8 t_send_delay, u8 t_echo_delay)
  906. {
  907. struct fsi_master_acf *master = to_fsi_master_acf(_master);
  908. if (link != 0)
  909. return -ENODEV;
  910. mutex_lock(&master->lock);
  911. master->t_send_delay = t_send_delay;
  912. master->t_echo_delay = t_echo_delay;
  913. dev_dbg(master->dev, "Changing delays: send=%d echo=%d\n",
  914. t_send_delay, t_echo_delay);
  915. iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
  916. iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
  917. mutex_unlock(&master->lock);
  918. return 0;
  919. }
  920. static ssize_t external_mode_show(struct device *dev,
  921. struct device_attribute *attr, char *buf)
  922. {
  923. struct fsi_master_acf *master = dev_get_drvdata(dev);
  924. return snprintf(buf, PAGE_SIZE - 1, "%u\n",
  925. master->external_mode ? 1 : 0);
  926. }
  927. static ssize_t external_mode_store(struct device *dev,
  928. struct device_attribute *attr, const char *buf, size_t count)
  929. {
  930. struct fsi_master_acf *master = dev_get_drvdata(dev);
  931. unsigned long val;
  932. bool external_mode;
  933. int err;
  934. err = kstrtoul(buf, 0, &val);
  935. if (err)
  936. return err;
  937. external_mode = !!val;
  938. mutex_lock(&master->lock);
  939. if (external_mode == master->external_mode) {
  940. mutex_unlock(&master->lock);
  941. return count;
  942. }
  943. master->external_mode = external_mode;
  944. if (master->external_mode) {
  945. fsi_master_acf_terminate(master);
  946. fsi_master_acf_setup_external(master);
  947. } else
  948. fsi_master_acf_setup(master);
  949. mutex_unlock(&master->lock);
  950. fsi_master_rescan(&master->master);
  951. return count;
  952. }
  953. static DEVICE_ATTR(external_mode, 0664,
  954. external_mode_show, external_mode_store);
  955. static int fsi_master_acf_gpio_request(void *data)
  956. {
  957. struct fsi_master_acf *master = data;
  958. int timeout;
  959. u8 val;
  960. /* Note: This doesn't require holding out mutex */
  961. /* Write reqest */
  962. iowrite8(ARB_ARM_REQ, master->sram + ARB_REG);
  963. /*
  964. * There is a race (which does happen at boot time) when we get an
  965. * arbitration request as we are either about to or just starting
  966. * the coprocessor.
  967. *
  968. * To handle it, we first check if we are running. If not yet we
  969. * check whether the copro is started in the SCU.
  970. *
  971. * If it's not started, we can basically just assume we have arbitration
  972. * and return. Otherwise, we wait normally expecting for the arbitration
  973. * to eventually complete.
  974. */
  975. if (ioread32(master->sram + CF_STARTED) == 0) {
  976. unsigned int reg = 0;
  977. regmap_read(master->scu, SCU_COPRO_CTRL, &reg);
  978. if (!(reg & SCU_COPRO_CLK_EN))
  979. return 0;
  980. }
  981. /* Ring doorbell if any */
  982. if (master->cvic)
  983. iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
  984. for (timeout = 0; timeout < 10000; timeout++) {
  985. val = ioread8(master->sram + ARB_REG);
  986. if (val != ARB_ARM_REQ)
  987. break;
  988. udelay(1);
  989. }
  990. /* If it failed, override anyway */
  991. if (val != ARB_ARM_ACK)
  992. dev_warn(master->dev, "GPIO request arbitration timeout\n");
  993. return 0;
  994. }
  995. static int fsi_master_acf_gpio_release(void *data)
  996. {
  997. struct fsi_master_acf *master = data;
  998. /* Write release */
  999. iowrite8(0, master->sram + ARB_REG);
  1000. /* Ring doorbell if any */
  1001. if (master->cvic)
  1002. iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
  1003. return 0;
  1004. }
  1005. static void fsi_master_acf_release(struct device *dev)
  1006. {
  1007. struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev));
  1008. /* Cleanup, stop coprocessor */
  1009. mutex_lock(&master->lock);
  1010. fsi_master_acf_terminate(master);
  1011. aspeed_gpio_copro_set_ops(NULL, NULL);
  1012. mutex_unlock(&master->lock);
  1013. /* Free resources */
  1014. gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
  1015. of_node_put(dev_of_node(master->dev));
  1016. kfree(master);
  1017. }
  1018. static const struct aspeed_gpio_copro_ops fsi_master_acf_gpio_ops = {
  1019. .request_access = fsi_master_acf_gpio_request,
  1020. .release_access = fsi_master_acf_gpio_release,
  1021. };
  1022. static int fsi_master_acf_probe(struct platform_device *pdev)
  1023. {
  1024. struct device_node *np, *mnode = dev_of_node(&pdev->dev);
  1025. struct genpool_data_fixed gpdf;
  1026. struct fsi_master_acf *master;
  1027. struct gpio_desc *gpio;
  1028. struct resource res;
  1029. uint32_t cf_mem_align;
  1030. int rc;
  1031. master = kzalloc(sizeof(*master), GFP_KERNEL);
  1032. if (!master)
  1033. return -ENOMEM;
  1034. master->dev = &pdev->dev;
  1035. master->master.dev.parent = master->dev;
  1036. master->last_addr = LAST_ADDR_INVALID;
  1037. /* AST2400 vs. AST2500 */
  1038. master->is_ast2500 = of_device_is_compatible(mnode, "aspeed,ast2500-cf-fsi-master");
  1039. /* Grab the SCU, we'll need to access it to configure the coprocessor */
  1040. if (master->is_ast2500)
  1041. master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
  1042. else
  1043. master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2400-scu");
  1044. if (IS_ERR(master->scu)) {
  1045. dev_err(&pdev->dev, "failed to find SCU regmap\n");
  1046. rc = PTR_ERR(master->scu);
  1047. goto err_free;
  1048. }
  1049. /* Grab all the GPIOs we need */
  1050. gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
  1051. if (IS_ERR(gpio)) {
  1052. dev_err(&pdev->dev, "failed to get clock gpio\n");
  1053. rc = PTR_ERR(gpio);
  1054. goto err_free;
  1055. }
  1056. master->gpio_clk = gpio;
  1057. gpio = devm_gpiod_get(&pdev->dev, "data", 0);
  1058. if (IS_ERR(gpio)) {
  1059. dev_err(&pdev->dev, "failed to get data gpio\n");
  1060. rc = PTR_ERR(gpio);
  1061. goto err_free;
  1062. }
  1063. master->gpio_data = gpio;
  1064. /* Optional GPIOs */
  1065. gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
  1066. if (IS_ERR(gpio)) {
  1067. dev_err(&pdev->dev, "failed to get trans gpio\n");
  1068. rc = PTR_ERR(gpio);
  1069. goto err_free;
  1070. }
  1071. master->gpio_trans = gpio;
  1072. gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
  1073. if (IS_ERR(gpio)) {
  1074. dev_err(&pdev->dev, "failed to get enable gpio\n");
  1075. rc = PTR_ERR(gpio);
  1076. goto err_free;
  1077. }
  1078. master->gpio_enable = gpio;
  1079. gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
  1080. if (IS_ERR(gpio)) {
  1081. dev_err(&pdev->dev, "failed to get mux gpio\n");
  1082. rc = PTR_ERR(gpio);
  1083. goto err_free;
  1084. }
  1085. master->gpio_mux = gpio;
  1086. /* Grab the reserved memory region (use DMA API instead ?) */
  1087. np = of_parse_phandle(mnode, "memory-region", 0);
  1088. if (!np) {
  1089. dev_err(&pdev->dev, "Didn't find reserved memory\n");
  1090. rc = -EINVAL;
  1091. goto err_free;
  1092. }
  1093. rc = of_address_to_resource(np, 0, &res);
  1094. of_node_put(np);
  1095. if (rc) {
  1096. dev_err(&pdev->dev, "Couldn't address to resource for reserved memory\n");
  1097. rc = -ENOMEM;
  1098. goto err_free;
  1099. }
  1100. master->cf_mem_size = resource_size(&res);
  1101. master->cf_mem_addr = (uint32_t)res.start;
  1102. cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000;
  1103. if (master->cf_mem_addr & (cf_mem_align - 1)) {
  1104. dev_err(&pdev->dev, "Reserved memory has insufficient alignment\n");
  1105. rc = -ENOMEM;
  1106. goto err_free;
  1107. }
  1108. master->cf_mem = devm_ioremap_resource(&pdev->dev, &res);
  1109. if (IS_ERR(master->cf_mem)) {
  1110. rc = PTR_ERR(master->cf_mem);
  1111. dev_err(&pdev->dev, "Error %d mapping coldfire memory\n", rc);
  1112. goto err_free;
  1113. }
  1114. dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr);
  1115. /* AST2500 has a SW interrupt to the coprocessor */
  1116. if (master->is_ast2500) {
  1117. /* Grab the CVIC (ColdFire interrupts controller) */
  1118. np = of_parse_phandle(mnode, "aspeed,cvic", 0);
  1119. if (!np) {
  1120. dev_err(&pdev->dev, "Didn't find CVIC\n");
  1121. rc = -EINVAL;
  1122. goto err_free;
  1123. }
  1124. master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);
  1125. if (IS_ERR(master->cvic)) {
  1126. rc = PTR_ERR(master->cvic);
  1127. dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc);
  1128. goto err_free;
  1129. }
  1130. rc = of_property_read_u32(np, "copro-sw-interrupts",
  1131. &master->cvic_sw_irq);
  1132. if (rc) {
  1133. dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n");
  1134. goto err_free;
  1135. }
  1136. }
  1137. /* Grab the SRAM */
  1138. master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0);
  1139. if (!master->sram_pool) {
  1140. rc = -ENODEV;
  1141. dev_err(&pdev->dev, "Can't find sram pool\n");
  1142. goto err_free;
  1143. }
  1144. /* Current microcode only deals with fixed location in SRAM */
  1145. gpdf.offset = 0;
  1146. master->sram = (void __iomem *)gen_pool_alloc_algo(master->sram_pool, SRAM_SIZE,
  1147. gen_pool_fixed_alloc, &gpdf);
  1148. if (!master->sram) {
  1149. rc = -ENOMEM;
  1150. dev_err(&pdev->dev, "Failed to allocate sram from pool\n");
  1151. goto err_free;
  1152. }
  1153. dev_dbg(&pdev->dev, "SRAM allocation @%lx\n",
  1154. (unsigned long)gen_pool_virt_to_phys(master->sram_pool,
  1155. (unsigned long)master->sram));
  1156. /*
  1157. * Hookup with the GPIO driver for arbitration of GPIO banks
  1158. * ownership.
  1159. */
  1160. aspeed_gpio_copro_set_ops(&fsi_master_acf_gpio_ops, master);
  1161. /* Default FSI command delays */
  1162. master->t_send_delay = FSI_SEND_DELAY_CLOCKS;
  1163. master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS;
  1164. master->master.n_links = 1;
  1165. if (master->is_ast2500)
  1166. master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
  1167. master->master.read = fsi_master_acf_read;
  1168. master->master.write = fsi_master_acf_write;
  1169. master->master.term = fsi_master_acf_term;
  1170. master->master.send_break = fsi_master_acf_break;
  1171. master->master.link_enable = fsi_master_acf_link_enable;
  1172. master->master.link_config = fsi_master_acf_link_config;
  1173. master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
  1174. master->master.dev.release = fsi_master_acf_release;
  1175. platform_set_drvdata(pdev, master);
  1176. mutex_init(&master->lock);
  1177. mutex_lock(&master->lock);
  1178. rc = fsi_master_acf_setup(master);
  1179. mutex_unlock(&master->lock);
  1180. if (rc)
  1181. goto release_of_dev;
  1182. rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
  1183. if (rc)
  1184. goto stop_copro;
  1185. rc = fsi_master_register(&master->master);
  1186. if (!rc)
  1187. return 0;
  1188. device_remove_file(master->dev, &dev_attr_external_mode);
  1189. put_device(&master->master.dev);
  1190. return rc;
  1191. stop_copro:
  1192. fsi_master_acf_terminate(master);
  1193. release_of_dev:
  1194. aspeed_gpio_copro_set_ops(NULL, NULL);
  1195. gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
  1196. of_node_put(dev_of_node(master->dev));
  1197. err_free:
  1198. kfree(master);
  1199. return rc;
  1200. }
  1201. static int fsi_master_acf_remove(struct platform_device *pdev)
  1202. {
  1203. struct fsi_master_acf *master = platform_get_drvdata(pdev);
  1204. device_remove_file(master->dev, &dev_attr_external_mode);
  1205. fsi_master_unregister(&master->master);
  1206. return 0;
  1207. }
  1208. static const struct of_device_id fsi_master_acf_match[] = {
  1209. { .compatible = "aspeed,ast2400-cf-fsi-master" },
  1210. { .compatible = "aspeed,ast2500-cf-fsi-master" },
  1211. { },
  1212. };
  1213. MODULE_DEVICE_TABLE(of, fsi_master_acf_match);
  1214. static struct platform_driver fsi_master_acf = {
  1215. .driver = {
  1216. .name = "fsi-master-acf",
  1217. .of_match_table = fsi_master_acf_match,
  1218. },
  1219. .probe = fsi_master_acf_probe,
  1220. .remove = fsi_master_acf_remove,
  1221. };
  1222. module_platform_driver(fsi_master_acf);
  1223. MODULE_LICENSE("GPL");