fsi-master-aspeed.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright (C) IBM Corporation 2018
  3. // FSI master driver for AST2600
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/fsi.h>
  7. #include <linux/io.h>
  8. #include <linux/mfd/syscon.h>
  9. #include <linux/module.h>
  10. #include <linux/mutex.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. #include <linux/slab.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/gpio/consumer.h>
  17. #include "fsi-master.h"
  18. struct fsi_master_aspeed {
  19. struct fsi_master master;
  20. struct mutex lock; /* protect HW access */
  21. struct device *dev;
  22. void __iomem *base;
  23. struct clk *clk;
  24. struct gpio_desc *cfam_reset_gpio;
  25. };
  26. #define to_fsi_master_aspeed(m) \
  27. container_of(m, struct fsi_master_aspeed, master)
  28. /* Control register (size 0x400) */
  29. static const u32 ctrl_base = 0x80000000;
  30. static const u32 fsi_base = 0xa0000000;
  31. #define OPB_FSI_VER 0x00
  32. #define OPB_TRIGGER 0x04
  33. #define OPB_CTRL_BASE 0x08
  34. #define OPB_FSI_BASE 0x0c
  35. #define OPB_CLK_SYNC 0x3c
  36. #define OPB_IRQ_CLEAR 0x40
  37. #define OPB_IRQ_MASK 0x44
  38. #define OPB_IRQ_STATUS 0x48
  39. #define OPB0_SELECT 0x10
  40. #define OPB0_RW 0x14
  41. #define OPB0_XFER_SIZE 0x18
  42. #define OPB0_FSI_ADDR 0x1c
  43. #define OPB0_FSI_DATA_W 0x20
  44. #define OPB0_STATUS 0x80
  45. #define OPB0_FSI_DATA_R 0x84
  46. #define OPB0_WRITE_ORDER1 0x4c
  47. #define OPB0_WRITE_ORDER2 0x50
  48. #define OPB1_WRITE_ORDER1 0x54
  49. #define OPB1_WRITE_ORDER2 0x58
  50. #define OPB0_READ_ORDER1 0x5c
  51. #define OPB1_READ_ORDER2 0x60
  52. #define OPB_RETRY_COUNTER 0x64
  53. /* OPBn_STATUS */
  54. #define STATUS_HALFWORD_ACK BIT(0)
  55. #define STATUS_FULLWORD_ACK BIT(1)
  56. #define STATUS_ERR_ACK BIT(2)
  57. #define STATUS_RETRY BIT(3)
  58. #define STATUS_TIMEOUT BIT(4)
  59. /* OPB_IRQ_MASK */
  60. #define OPB1_XFER_ACK_EN BIT(17)
  61. #define OPB0_XFER_ACK_EN BIT(16)
  62. /* OPB_RW */
  63. #define CMD_READ BIT(0)
  64. #define CMD_WRITE 0
  65. /* OPBx_XFER_SIZE */
  66. #define XFER_FULLWORD (BIT(1) | BIT(0))
  67. #define XFER_HALFWORD (BIT(0))
  68. #define XFER_BYTE (0)
  69. #define CREATE_TRACE_POINTS
  70. #include <trace/events/fsi_master_aspeed.h>
  71. #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */
  72. /* Run the bus at maximum speed by default */
  73. #define FSI_DIVISOR_DEFAULT 1
  74. #define FSI_DIVISOR_CABLED 2
  75. static u16 aspeed_fsi_divisor = FSI_DIVISOR_DEFAULT;
  76. module_param_named(bus_div,aspeed_fsi_divisor, ushort, 0);
  77. #define OPB_POLL_TIMEOUT 10000
  78. static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr,
  79. u32 val, u32 transfer_size)
  80. {
  81. void __iomem *base = aspeed->base;
  82. u32 reg, status;
  83. int ret;
  84. writel(CMD_WRITE, base + OPB0_RW);
  85. writel(transfer_size, base + OPB0_XFER_SIZE);
  86. writel(addr, base + OPB0_FSI_ADDR);
  87. writel(val, base + OPB0_FSI_DATA_W);
  88. writel(0x1, base + OPB_IRQ_CLEAR);
  89. writel(0x1, base + OPB_TRIGGER);
  90. ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
  91. (reg & OPB0_XFER_ACK_EN) != 0,
  92. 0, OPB_POLL_TIMEOUT);
  93. status = readl(base + OPB0_STATUS);
  94. trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg);
  95. /* Return error when poll timed out */
  96. if (ret)
  97. return ret;
  98. /* Command failed, master will reset */
  99. if (status & STATUS_ERR_ACK)
  100. return -EIO;
  101. return 0;
  102. }
  103. static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val)
  104. {
  105. return __opb_write(aspeed, addr, val, XFER_BYTE);
  106. }
  107. static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val)
  108. {
  109. return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD);
  110. }
  111. static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val)
  112. {
  113. return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD);
  114. }
  115. static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr,
  116. u32 transfer_size, void *out)
  117. {
  118. void __iomem *base = aspeed->base;
  119. u32 result, reg;
  120. int status, ret;
  121. writel(CMD_READ, base + OPB0_RW);
  122. writel(transfer_size, base + OPB0_XFER_SIZE);
  123. writel(addr, base + OPB0_FSI_ADDR);
  124. writel(0x1, base + OPB_IRQ_CLEAR);
  125. writel(0x1, base + OPB_TRIGGER);
  126. ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
  127. (reg & OPB0_XFER_ACK_EN) != 0,
  128. 0, OPB_POLL_TIMEOUT);
  129. status = readl(base + OPB0_STATUS);
  130. result = readl(base + OPB0_FSI_DATA_R);
  131. trace_fsi_master_aspeed_opb_read(addr, transfer_size, result,
  132. readl(base + OPB0_STATUS),
  133. reg);
  134. /* Return error when poll timed out */
  135. if (ret)
  136. return ret;
  137. /* Command failed, master will reset */
  138. if (status & STATUS_ERR_ACK)
  139. return -EIO;
  140. if (out) {
  141. switch (transfer_size) {
  142. case XFER_BYTE:
  143. *(u8 *)out = result;
  144. break;
  145. case XFER_HALFWORD:
  146. *(u16 *)out = result;
  147. break;
  148. case XFER_FULLWORD:
  149. *(u32 *)out = result;
  150. break;
  151. default:
  152. return -EINVAL;
  153. }
  154. }
  155. return 0;
  156. }
  157. static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out)
  158. {
  159. return __opb_read(aspeed, addr, XFER_FULLWORD, out);
  160. }
  161. static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out)
  162. {
  163. return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out);
  164. }
  165. static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out)
  166. {
  167. return __opb_read(aspeed, addr, XFER_BYTE, (void *)out);
  168. }
  169. static int check_errors(struct fsi_master_aspeed *aspeed, int err)
  170. {
  171. int ret;
  172. if (trace_fsi_master_aspeed_opb_error_enabled()) {
  173. __be32 mresp0, mstap0, mesrb0;
  174. opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);
  175. opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);
  176. opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);
  177. trace_fsi_master_aspeed_opb_error(
  178. be32_to_cpu(mresp0),
  179. be32_to_cpu(mstap0),
  180. be32_to_cpu(mesrb0));
  181. }
  182. if (err == -EIO) {
  183. /* Check MAEB (0x70) ? */
  184. /* Then clear errors in master */
  185. ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,
  186. cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));
  187. if (ret) {
  188. /* TODO: log? return different code? */
  189. return ret;
  190. }
  191. /* TODO: confirm that 0x70 was okay */
  192. }
  193. /* This will pass through timeout errors */
  194. return err;
  195. }
  196. static int aspeed_master_read(struct fsi_master *master, int link,
  197. uint8_t id, uint32_t addr, void *val, size_t size)
  198. {
  199. struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
  200. int ret;
  201. if (id > 0x3)
  202. return -EINVAL;
  203. addr |= id << 21;
  204. addr += link * FSI_HUB_LINK_SIZE;
  205. mutex_lock(&aspeed->lock);
  206. switch (size) {
  207. case 1:
  208. ret = opb_readb(aspeed, fsi_base + addr, val);
  209. break;
  210. case 2:
  211. ret = opb_readw(aspeed, fsi_base + addr, val);
  212. break;
  213. case 4:
  214. ret = opb_readl(aspeed, fsi_base + addr, val);
  215. break;
  216. default:
  217. ret = -EINVAL;
  218. goto done;
  219. }
  220. ret = check_errors(aspeed, ret);
  221. done:
  222. mutex_unlock(&aspeed->lock);
  223. return ret;
  224. }
  225. static int aspeed_master_write(struct fsi_master *master, int link,
  226. uint8_t id, uint32_t addr, const void *val, size_t size)
  227. {
  228. struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
  229. int ret;
  230. if (id > 0x3)
  231. return -EINVAL;
  232. addr |= id << 21;
  233. addr += link * FSI_HUB_LINK_SIZE;
  234. mutex_lock(&aspeed->lock);
  235. switch (size) {
  236. case 1:
  237. ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val);
  238. break;
  239. case 2:
  240. ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val);
  241. break;
  242. case 4:
  243. ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val);
  244. break;
  245. default:
  246. ret = -EINVAL;
  247. goto done;
  248. }
  249. ret = check_errors(aspeed, ret);
  250. done:
  251. mutex_unlock(&aspeed->lock);
  252. return ret;
  253. }
  254. static int aspeed_master_link_enable(struct fsi_master *master, int link,
  255. bool enable)
  256. {
  257. struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
  258. int idx, bit, ret;
  259. __be32 reg;
  260. idx = link / 32;
  261. bit = link % 32;
  262. reg = cpu_to_be32(0x80000000 >> bit);
  263. mutex_lock(&aspeed->lock);
  264. if (!enable) {
  265. ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg);
  266. goto done;
  267. }
  268. ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);
  269. if (ret)
  270. goto done;
  271. mdelay(FSI_LINK_ENABLE_SETUP_TIME);
  272. done:
  273. mutex_unlock(&aspeed->lock);
  274. return ret;
  275. }
  276. static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id)
  277. {
  278. uint32_t addr;
  279. __be32 cmd;
  280. addr = 0x4;
  281. cmd = cpu_to_be32(0xecc00000);
  282. return aspeed_master_write(master, link, id, addr, &cmd, 4);
  283. }
  284. static int aspeed_master_break(struct fsi_master *master, int link)
  285. {
  286. uint32_t addr;
  287. __be32 cmd;
  288. addr = 0x0;
  289. cmd = cpu_to_be32(0xc0de0000);
  290. return aspeed_master_write(master, link, 0, addr, &cmd, 4);
  291. }
  292. static void aspeed_master_release(struct device *dev)
  293. {
  294. struct fsi_master_aspeed *aspeed =
  295. to_fsi_master_aspeed(dev_to_fsi_master(dev));
  296. kfree(aspeed);
  297. }
  298. /* mmode encoders */
  299. static inline u32 fsi_mmode_crs0(u32 x)
  300. {
  301. return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
  302. }
  303. static inline u32 fsi_mmode_crs1(u32 x)
  304. {
  305. return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
  306. }
  307. static int aspeed_master_init(struct fsi_master_aspeed *aspeed)
  308. {
  309. __be32 reg;
  310. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
  311. | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
  312. opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
  313. /* Initialize the MFSI (hub master) engine */
  314. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
  315. | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
  316. opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
  317. reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
  318. opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);
  319. reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA
  320. | fsi_mmode_crs0(aspeed_fsi_divisor)
  321. | fsi_mmode_crs1(aspeed_fsi_divisor)
  322. | FSI_MMODE_P8_TO_LSB);
  323. dev_info(aspeed->dev, "mmode set to %08x (divisor %d)\n",
  324. be32_to_cpu(reg), aspeed_fsi_divisor);
  325. opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);
  326. reg = cpu_to_be32(0xffff0000);
  327. opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);
  328. reg = cpu_to_be32(~0);
  329. opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);
  330. /* Leave enabled long enough for master logic to set up */
  331. mdelay(FSI_LINK_ENABLE_SETUP_TIME);
  332. opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);
  333. opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);
  334. reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
  335. opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
  336. opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);
  337. /* Reset the master bridge */
  338. reg = cpu_to_be32(FSI_MRESB_RST_GEN);
  339. opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
  340. reg = cpu_to_be32(FSI_MRESB_RST_ERR);
  341. opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
  342. return 0;
  343. }
  344. static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *attr,
  345. const char *buf, size_t count)
  346. {
  347. struct fsi_master_aspeed *aspeed = dev_get_drvdata(dev);
  348. mutex_lock(&aspeed->lock);
  349. gpiod_set_value(aspeed->cfam_reset_gpio, 1);
  350. usleep_range(900, 1000);
  351. gpiod_set_value(aspeed->cfam_reset_gpio, 0);
  352. mutex_unlock(&aspeed->lock);
  353. return count;
  354. }
  355. static DEVICE_ATTR(cfam_reset, 0200, NULL, cfam_reset_store);
  356. static int setup_cfam_reset(struct fsi_master_aspeed *aspeed)
  357. {
  358. struct device *dev = aspeed->dev;
  359. struct gpio_desc *gpio;
  360. int rc;
  361. gpio = devm_gpiod_get_optional(dev, "cfam-reset", GPIOD_OUT_LOW);
  362. if (IS_ERR(gpio))
  363. return PTR_ERR(gpio);
  364. if (!gpio)
  365. return 0;
  366. aspeed->cfam_reset_gpio = gpio;
  367. rc = device_create_file(dev, &dev_attr_cfam_reset);
  368. if (rc) {
  369. devm_gpiod_put(dev, gpio);
  370. return rc;
  371. }
  372. return 0;
  373. }
  374. static int tacoma_cabled_fsi_fixup(struct device *dev)
  375. {
  376. struct gpio_desc *routing_gpio, *mux_gpio;
  377. int gpio;
  378. /*
  379. * The routing GPIO is a jumper indicating we should mux for the
  380. * externally connected FSI cable.
  381. */
  382. routing_gpio = devm_gpiod_get_optional(dev, "fsi-routing",
  383. GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
  384. if (IS_ERR(routing_gpio))
  385. return PTR_ERR(routing_gpio);
  386. if (!routing_gpio)
  387. return 0;
  388. mux_gpio = devm_gpiod_get_optional(dev, "fsi-mux", GPIOD_ASIS);
  389. if (IS_ERR(mux_gpio))
  390. return PTR_ERR(mux_gpio);
  391. if (!mux_gpio)
  392. return 0;
  393. gpio = gpiod_get_value(routing_gpio);
  394. if (gpio < 0)
  395. return gpio;
  396. /* If the routing GPIO is high we should set the mux to low. */
  397. if (gpio) {
  398. /*
  399. * Cable signal integrity means we should run the bus
  400. * slightly slower. Do not override if a kernel param
  401. * has already overridden.
  402. */
  403. if (aspeed_fsi_divisor == FSI_DIVISOR_DEFAULT)
  404. aspeed_fsi_divisor = FSI_DIVISOR_CABLED;
  405. gpiod_direction_output(mux_gpio, 0);
  406. dev_info(dev, "FSI configured for external cable\n");
  407. } else {
  408. gpiod_direction_output(mux_gpio, 1);
  409. }
  410. devm_gpiod_put(dev, routing_gpio);
  411. return 0;
  412. }
  413. static int fsi_master_aspeed_probe(struct platform_device *pdev)
  414. {
  415. struct fsi_master_aspeed *aspeed;
  416. int rc, links, reg;
  417. __be32 raw;
  418. rc = tacoma_cabled_fsi_fixup(&pdev->dev);
  419. if (rc) {
  420. dev_err(&pdev->dev, "Tacoma FSI cable fixup failed\n");
  421. return rc;
  422. }
  423. aspeed = kzalloc(sizeof(*aspeed), GFP_KERNEL);
  424. if (!aspeed)
  425. return -ENOMEM;
  426. aspeed->dev = &pdev->dev;
  427. aspeed->base = devm_platform_ioremap_resource(pdev, 0);
  428. if (IS_ERR(aspeed->base)) {
  429. rc = PTR_ERR(aspeed->base);
  430. goto err_free_aspeed;
  431. }
  432. aspeed->clk = devm_clk_get(aspeed->dev, NULL);
  433. if (IS_ERR(aspeed->clk)) {
  434. dev_err(aspeed->dev, "couldn't get clock\n");
  435. rc = PTR_ERR(aspeed->clk);
  436. goto err_free_aspeed;
  437. }
  438. rc = clk_prepare_enable(aspeed->clk);
  439. if (rc) {
  440. dev_err(aspeed->dev, "couldn't enable clock\n");
  441. goto err_free_aspeed;
  442. }
  443. rc = setup_cfam_reset(aspeed);
  444. if (rc) {
  445. dev_err(&pdev->dev, "CFAM reset GPIO setup failed\n");
  446. }
  447. writel(0x1, aspeed->base + OPB_CLK_SYNC);
  448. writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN,
  449. aspeed->base + OPB_IRQ_MASK);
  450. /* TODO: determine an appropriate value */
  451. writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
  452. writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
  453. writel(fsi_base, aspeed->base + OPB_FSI_BASE);
  454. /* Set read data order */
  455. writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
  456. /* Set write data order */
  457. writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
  458. writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
  459. /*
  460. * Select OPB0 for all operations.
  461. * Will need to be reworked when enabling DMA or anything that uses
  462. * OPB1.
  463. */
  464. writel(0x1, aspeed->base + OPB0_SELECT);
  465. rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);
  466. if (rc) {
  467. dev_err(&pdev->dev, "failed to read hub version\n");
  468. goto err_release;
  469. }
  470. reg = be32_to_cpu(raw);
  471. links = (reg >> 8) & 0xff;
  472. dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links);
  473. aspeed->master.dev.parent = &pdev->dev;
  474. aspeed->master.dev.release = aspeed_master_release;
  475. aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev));
  476. aspeed->master.n_links = links;
  477. aspeed->master.read = aspeed_master_read;
  478. aspeed->master.write = aspeed_master_write;
  479. aspeed->master.send_break = aspeed_master_break;
  480. aspeed->master.term = aspeed_master_term;
  481. aspeed->master.link_enable = aspeed_master_link_enable;
  482. dev_set_drvdata(&pdev->dev, aspeed);
  483. mutex_init(&aspeed->lock);
  484. aspeed_master_init(aspeed);
  485. rc = fsi_master_register(&aspeed->master);
  486. if (rc)
  487. goto err_release;
  488. /* At this point, fsi_master_register performs the device_initialize(),
  489. * and holds the sole reference on master.dev. This means the device
  490. * will be freed (via ->release) during any subsequent call to
  491. * fsi_master_unregister. We add our own reference to it here, so we
  492. * can perform cleanup (in _remove()) without it being freed before
  493. * we're ready.
  494. */
  495. get_device(&aspeed->master.dev);
  496. return 0;
  497. err_release:
  498. clk_disable_unprepare(aspeed->clk);
  499. err_free_aspeed:
  500. kfree(aspeed);
  501. return rc;
  502. }
  503. static int fsi_master_aspeed_remove(struct platform_device *pdev)
  504. {
  505. struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev);
  506. fsi_master_unregister(&aspeed->master);
  507. clk_disable_unprepare(aspeed->clk);
  508. return 0;
  509. }
  510. static const struct of_device_id fsi_master_aspeed_match[] = {
  511. { .compatible = "aspeed,ast2600-fsi-master" },
  512. { },
  513. };
  514. MODULE_DEVICE_TABLE(of, fsi_master_aspeed_match);
  515. static struct platform_driver fsi_master_aspeed_driver = {
  516. .driver = {
  517. .name = "fsi-master-aspeed",
  518. .of_match_table = fsi_master_aspeed_match,
  519. },
  520. .probe = fsi_master_aspeed_probe,
  521. .remove = fsi_master_aspeed_remove,
  522. };
  523. module_platform_driver(fsi_master_aspeed_driver);
  524. MODULE_LICENSE("GPL");