zynqmp-fpga.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Xilinx, Inc.
  4. */
  5. #include <linux/dma-mapping.h>
  6. #include <linux/fpga/fpga-mgr.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_address.h>
  11. #include <linux/string.h>
  12. #include <linux/firmware/xlnx-zynqmp.h>
  13. /* Constant Definitions */
  14. #define IXR_FPGA_DONE_MASK BIT(3)
  15. /**
  16. * struct zynqmp_fpga_priv - Private data structure
  17. * @dev: Device data structure
  18. * @flags: flags which is used to identify the bitfile type
  19. */
  20. struct zynqmp_fpga_priv {
  21. struct device *dev;
  22. u32 flags;
  23. };
  24. static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
  25. struct fpga_image_info *info,
  26. const char *buf, size_t size)
  27. {
  28. struct zynqmp_fpga_priv *priv;
  29. priv = mgr->priv;
  30. priv->flags = info->flags;
  31. return 0;
  32. }
  33. static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
  34. const char *buf, size_t size)
  35. {
  36. struct zynqmp_fpga_priv *priv;
  37. dma_addr_t dma_addr;
  38. u32 eemi_flags = 0;
  39. char *kbuf;
  40. int ret;
  41. priv = mgr->priv;
  42. kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
  43. if (!kbuf)
  44. return -ENOMEM;
  45. memcpy(kbuf, buf, size);
  46. wmb(); /* ensure all writes are done before initiate FW call */
  47. if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
  48. eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
  49. ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags);
  50. dma_free_coherent(priv->dev, size, kbuf, dma_addr);
  51. return ret;
  52. }
  53. static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
  54. struct fpga_image_info *info)
  55. {
  56. return 0;
  57. }
  58. static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
  59. {
  60. u32 status = 0;
  61. zynqmp_pm_fpga_get_status(&status);
  62. if (status & IXR_FPGA_DONE_MASK)
  63. return FPGA_MGR_STATE_OPERATING;
  64. return FPGA_MGR_STATE_UNKNOWN;
  65. }
  66. static const struct fpga_manager_ops zynqmp_fpga_ops = {
  67. .state = zynqmp_fpga_ops_state,
  68. .write_init = zynqmp_fpga_ops_write_init,
  69. .write = zynqmp_fpga_ops_write,
  70. .write_complete = zynqmp_fpga_ops_write_complete,
  71. };
  72. static int zynqmp_fpga_probe(struct platform_device *pdev)
  73. {
  74. struct device *dev = &pdev->dev;
  75. struct zynqmp_fpga_priv *priv;
  76. struct fpga_manager *mgr;
  77. int ret;
  78. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  79. if (!priv)
  80. return -ENOMEM;
  81. priv->dev = dev;
  82. mgr = devm_fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
  83. &zynqmp_fpga_ops, priv);
  84. if (!mgr)
  85. return -ENOMEM;
  86. platform_set_drvdata(pdev, mgr);
  87. ret = fpga_mgr_register(mgr);
  88. if (ret) {
  89. dev_err(dev, "unable to register FPGA manager");
  90. return ret;
  91. }
  92. return 0;
  93. }
  94. static int zynqmp_fpga_remove(struct platform_device *pdev)
  95. {
  96. struct fpga_manager *mgr = platform_get_drvdata(pdev);
  97. fpga_mgr_unregister(mgr);
  98. return 0;
  99. }
  100. static const struct of_device_id zynqmp_fpga_of_match[] = {
  101. { .compatible = "xlnx,zynqmp-pcap-fpga", },
  102. {},
  103. };
  104. MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
  105. static struct platform_driver zynqmp_fpga_driver = {
  106. .probe = zynqmp_fpga_probe,
  107. .remove = zynqmp_fpga_remove,
  108. .driver = {
  109. .name = "zynqmp_fpga_manager",
  110. .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
  111. },
  112. };
  113. module_platform_driver(zynqmp_fpga_driver);
  114. MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
  115. MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
  116. MODULE_LICENSE("GPL");