xilinx-spi.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
  4. *
  5. * Copyright (C) 2017 DENX Software Engineering
  6. *
  7. * Anatolij Gustschin <agust@denx.de>
  8. *
  9. * Manage Xilinx FPGA firmware that is loaded over SPI using
  10. * the slave serial configuration interface.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/fpga/fpga-mgr.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/module.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/of.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/sizes.h>
  21. struct xilinx_spi_conf {
  22. struct spi_device *spi;
  23. struct gpio_desc *prog_b;
  24. struct gpio_desc *init_b;
  25. struct gpio_desc *done;
  26. };
  27. static int get_done_gpio(struct fpga_manager *mgr)
  28. {
  29. struct xilinx_spi_conf *conf = mgr->priv;
  30. int ret;
  31. ret = gpiod_get_value(conf->done);
  32. if (ret < 0)
  33. dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
  34. return ret;
  35. }
  36. static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
  37. {
  38. if (!get_done_gpio(mgr))
  39. return FPGA_MGR_STATE_RESET;
  40. return FPGA_MGR_STATE_UNKNOWN;
  41. }
  42. /**
  43. * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
  44. * a given delay if the pin is unavailable
  45. *
  46. * @mgr: The FPGA manager object
  47. * @value: Value INIT_B to wait for (1 = asserted = low)
  48. * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
  49. *
  50. * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
  51. * too much time passed waiting for that. If no INIT_B GPIO is available
  52. * then always return 0.
  53. */
  54. static int wait_for_init_b(struct fpga_manager *mgr, int value,
  55. unsigned long alt_udelay)
  56. {
  57. struct xilinx_spi_conf *conf = mgr->priv;
  58. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  59. if (conf->init_b) {
  60. while (time_before(jiffies, timeout)) {
  61. int ret = gpiod_get_value(conf->init_b);
  62. if (ret == value)
  63. return 0;
  64. if (ret < 0) {
  65. dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
  66. return ret;
  67. }
  68. usleep_range(100, 400);
  69. }
  70. dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
  71. value ? "assert" : "deassert");
  72. return -ETIMEDOUT;
  73. }
  74. udelay(alt_udelay);
  75. return 0;
  76. }
  77. static int xilinx_spi_write_init(struct fpga_manager *mgr,
  78. struct fpga_image_info *info,
  79. const char *buf, size_t count)
  80. {
  81. struct xilinx_spi_conf *conf = mgr->priv;
  82. int err;
  83. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
  84. dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
  85. return -EINVAL;
  86. }
  87. gpiod_set_value(conf->prog_b, 1);
  88. err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
  89. if (err) {
  90. gpiod_set_value(conf->prog_b, 0);
  91. return err;
  92. }
  93. gpiod_set_value(conf->prog_b, 0);
  94. err = wait_for_init_b(mgr, 0, 0);
  95. if (err)
  96. return err;
  97. if (get_done_gpio(mgr)) {
  98. dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
  99. return -EIO;
  100. }
  101. /* program latency */
  102. usleep_range(7500, 7600);
  103. return 0;
  104. }
  105. static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
  106. size_t count)
  107. {
  108. struct xilinx_spi_conf *conf = mgr->priv;
  109. const char *fw_data = buf;
  110. const char *fw_data_end = fw_data + count;
  111. while (fw_data < fw_data_end) {
  112. size_t remaining, stride;
  113. int ret;
  114. remaining = fw_data_end - fw_data;
  115. stride = min_t(size_t, remaining, SZ_4K);
  116. ret = spi_write(conf->spi, fw_data, stride);
  117. if (ret) {
  118. dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
  119. ret);
  120. return ret;
  121. }
  122. fw_data += stride;
  123. }
  124. return 0;
  125. }
  126. static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
  127. {
  128. struct spi_device *spi = conf->spi;
  129. const u8 din_data[1] = { 0xff };
  130. int ret;
  131. ret = spi_write(conf->spi, din_data, sizeof(din_data));
  132. if (ret)
  133. dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
  134. return ret;
  135. }
  136. static int xilinx_spi_write_complete(struct fpga_manager *mgr,
  137. struct fpga_image_info *info)
  138. {
  139. struct xilinx_spi_conf *conf = mgr->priv;
  140. unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
  141. bool expired = false;
  142. int done;
  143. int ret;
  144. /*
  145. * This loop is carefully written such that if the driver is
  146. * scheduled out for more than 'timeout', we still check for DONE
  147. * before giving up and we apply 8 extra CCLK cycles in all cases.
  148. */
  149. while (!expired) {
  150. expired = time_after(jiffies, timeout);
  151. done = get_done_gpio(mgr);
  152. if (done < 0)
  153. return done;
  154. ret = xilinx_spi_apply_cclk_cycles(conf);
  155. if (ret)
  156. return ret;
  157. if (done)
  158. return 0;
  159. }
  160. if (conf->init_b) {
  161. ret = gpiod_get_value(conf->init_b);
  162. if (ret < 0) {
  163. dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
  164. return ret;
  165. }
  166. dev_err(&mgr->dev,
  167. ret ? "CRC error or invalid device\n"
  168. : "Missing sync word or incomplete bitstream\n");
  169. } else {
  170. dev_err(&mgr->dev, "Timeout after config data transfer\n");
  171. }
  172. return -ETIMEDOUT;
  173. }
  174. static const struct fpga_manager_ops xilinx_spi_ops = {
  175. .state = xilinx_spi_state,
  176. .write_init = xilinx_spi_write_init,
  177. .write = xilinx_spi_write,
  178. .write_complete = xilinx_spi_write_complete,
  179. };
  180. static int xilinx_spi_probe(struct spi_device *spi)
  181. {
  182. struct xilinx_spi_conf *conf;
  183. struct fpga_manager *mgr;
  184. conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
  185. if (!conf)
  186. return -ENOMEM;
  187. conf->spi = spi;
  188. /* PROGRAM_B is active low */
  189. conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
  190. if (IS_ERR(conf->prog_b))
  191. return dev_err_probe(&spi->dev, PTR_ERR(conf->prog_b),
  192. "Failed to get PROGRAM_B gpio\n");
  193. conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
  194. if (IS_ERR(conf->init_b))
  195. return dev_err_probe(&spi->dev, PTR_ERR(conf->init_b),
  196. "Failed to get INIT_B gpio\n");
  197. conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
  198. if (IS_ERR(conf->done))
  199. return dev_err_probe(&spi->dev, PTR_ERR(conf->done),
  200. "Failed to get DONE gpio\n");
  201. mgr = devm_fpga_mgr_create(&spi->dev,
  202. "Xilinx Slave Serial FPGA Manager",
  203. &xilinx_spi_ops, conf);
  204. if (!mgr)
  205. return -ENOMEM;
  206. spi_set_drvdata(spi, mgr);
  207. return fpga_mgr_register(mgr);
  208. }
  209. static int xilinx_spi_remove(struct spi_device *spi)
  210. {
  211. struct fpga_manager *mgr = spi_get_drvdata(spi);
  212. fpga_mgr_unregister(mgr);
  213. return 0;
  214. }
  215. static const struct of_device_id xlnx_spi_of_match[] = {
  216. { .compatible = "xlnx,fpga-slave-serial", },
  217. {}
  218. };
  219. MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
  220. static struct spi_driver xilinx_slave_spi_driver = {
  221. .driver = {
  222. .name = "xlnx-slave-spi",
  223. .of_match_table = of_match_ptr(xlnx_spi_of_match),
  224. },
  225. .probe = xilinx_spi_probe,
  226. .remove = xilinx_spi_remove,
  227. };
  228. module_spi_driver(xilinx_slave_spi_driver)
  229. MODULE_LICENSE("GPL v2");
  230. MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
  231. MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");