socfpga-a10.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Manager Driver for Altera Arria10 SoCFPGA
  4. *
  5. * Copyright (C) 2015-2016 Altera Corporation
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/fpga/fpga-mgr.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of_address.h>
  14. #include <linux/regmap.h>
  15. #define A10_FPGAMGR_DCLKCNT_OFST 0x08
  16. #define A10_FPGAMGR_DCLKSTAT_OFST 0x0c
  17. #define A10_FPGAMGR_IMGCFG_CTL_00_OFST 0x70
  18. #define A10_FPGAMGR_IMGCFG_CTL_01_OFST 0x74
  19. #define A10_FPGAMGR_IMGCFG_CTL_02_OFST 0x78
  20. #define A10_FPGAMGR_IMGCFG_STAT_OFST 0x80
  21. #define A10_FPGAMGR_DCLKSTAT_DCLKDONE BIT(0)
  22. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG BIT(0)
  23. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS BIT(1)
  24. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE BIT(2)
  25. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG BIT(8)
  26. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE BIT(16)
  27. #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE BIT(24)
  28. #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG BIT(0)
  29. #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST BIT(16)
  30. #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE BIT(24)
  31. #define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL BIT(0)
  32. #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK (BIT(16) | BIT(17))
  33. #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT 16
  34. #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH BIT(24)
  35. #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT 24
  36. #define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR BIT(0)
  37. #define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE BIT(1)
  38. #define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE BIT(2)
  39. #define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN BIT(4)
  40. #define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN BIT(6)
  41. #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY BIT(9)
  42. #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE BIT(10)
  43. #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR BIT(11)
  44. #define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN BIT(12)
  45. #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK (BIT(16) | BIT(17) | BIT(18))
  46. #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT 16
  47. /* FPGA CD Ratio Value */
  48. #define CDRATIO_x1 0x0
  49. #define CDRATIO_x2 0x1
  50. #define CDRATIO_x4 0x2
  51. #define CDRATIO_x8 0x3
  52. /* Configuration width 16/32 bit */
  53. #define CFGWDTH_32 1
  54. #define CFGWDTH_16 0
  55. /*
  56. * struct a10_fpga_priv - private data for fpga manager
  57. * @regmap: regmap for register access
  58. * @fpga_data_addr: iomap for single address data register to FPGA
  59. * @clk: clock
  60. */
  61. struct a10_fpga_priv {
  62. struct regmap *regmap;
  63. void __iomem *fpga_data_addr;
  64. struct clk *clk;
  65. };
  66. static bool socfpga_a10_fpga_writeable_reg(struct device *dev, unsigned int reg)
  67. {
  68. switch (reg) {
  69. case A10_FPGAMGR_DCLKCNT_OFST:
  70. case A10_FPGAMGR_DCLKSTAT_OFST:
  71. case A10_FPGAMGR_IMGCFG_CTL_00_OFST:
  72. case A10_FPGAMGR_IMGCFG_CTL_01_OFST:
  73. case A10_FPGAMGR_IMGCFG_CTL_02_OFST:
  74. return true;
  75. }
  76. return false;
  77. }
  78. static bool socfpga_a10_fpga_readable_reg(struct device *dev, unsigned int reg)
  79. {
  80. switch (reg) {
  81. case A10_FPGAMGR_DCLKCNT_OFST:
  82. case A10_FPGAMGR_DCLKSTAT_OFST:
  83. case A10_FPGAMGR_IMGCFG_CTL_00_OFST:
  84. case A10_FPGAMGR_IMGCFG_CTL_01_OFST:
  85. case A10_FPGAMGR_IMGCFG_CTL_02_OFST:
  86. case A10_FPGAMGR_IMGCFG_STAT_OFST:
  87. return true;
  88. }
  89. return false;
  90. }
  91. static const struct regmap_config socfpga_a10_fpga_regmap_config = {
  92. .reg_bits = 32,
  93. .reg_stride = 4,
  94. .val_bits = 32,
  95. .writeable_reg = socfpga_a10_fpga_writeable_reg,
  96. .readable_reg = socfpga_a10_fpga_readable_reg,
  97. .max_register = A10_FPGAMGR_IMGCFG_STAT_OFST,
  98. .cache_type = REGCACHE_NONE,
  99. };
  100. /*
  101. * from the register map description of cdratio in imgcfg_ctrl_02:
  102. * Normal Configuration : 32bit Passive Parallel
  103. * Partial Reconfiguration : 16bit Passive Parallel
  104. */
  105. static void socfpga_a10_fpga_set_cfg_width(struct a10_fpga_priv *priv,
  106. int width)
  107. {
  108. width <<= A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT;
  109. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
  110. A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH, width);
  111. }
  112. static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv,
  113. u32 count)
  114. {
  115. u32 val;
  116. /* Clear any existing DONE status. */
  117. regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST,
  118. A10_FPGAMGR_DCLKSTAT_DCLKDONE);
  119. /* Issue the DCLK regmap. */
  120. regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count);
  121. /* wait till the dclkcnt done */
  122. regmap_read_poll_timeout(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, val,
  123. val, 1, 100);
  124. /* Clear DONE status. */
  125. regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST,
  126. A10_FPGAMGR_DCLKSTAT_DCLKDONE);
  127. }
  128. #define RBF_ENCRYPTION_MODE_OFFSET 69
  129. #define RBF_DECOMPRESS_OFFSET 229
  130. static int socfpga_a10_fpga_encrypted(u32 *buf32, size_t buf32_size)
  131. {
  132. if (buf32_size < RBF_ENCRYPTION_MODE_OFFSET + 1)
  133. return -EINVAL;
  134. /* Is the bitstream encrypted? */
  135. return ((buf32[RBF_ENCRYPTION_MODE_OFFSET] >> 2) & 3) != 0;
  136. }
  137. static int socfpga_a10_fpga_compressed(u32 *buf32, size_t buf32_size)
  138. {
  139. if (buf32_size < RBF_DECOMPRESS_OFFSET + 1)
  140. return -EINVAL;
  141. /* Is the bitstream compressed? */
  142. return !((buf32[RBF_DECOMPRESS_OFFSET] >> 1) & 1);
  143. }
  144. static unsigned int socfpga_a10_fpga_get_cd_ratio(unsigned int cfg_width,
  145. bool encrypt, bool compress)
  146. {
  147. unsigned int cd_ratio;
  148. /*
  149. * cd ratio is dependent on cfg width and whether the bitstream
  150. * is encrypted and/or compressed.
  151. *
  152. * | width | encr. | compr. | cd ratio |
  153. * | 16 | 0 | 0 | 1 |
  154. * | 16 | 0 | 1 | 4 |
  155. * | 16 | 1 | 0 | 2 |
  156. * | 16 | 1 | 1 | 4 |
  157. * | 32 | 0 | 0 | 1 |
  158. * | 32 | 0 | 1 | 8 |
  159. * | 32 | 1 | 0 | 4 |
  160. * | 32 | 1 | 1 | 8 |
  161. */
  162. if (!compress && !encrypt)
  163. return CDRATIO_x1;
  164. if (compress)
  165. cd_ratio = CDRATIO_x4;
  166. else
  167. cd_ratio = CDRATIO_x2;
  168. /* If 32 bit, double the cd ratio by incrementing the field */
  169. if (cfg_width == CFGWDTH_32)
  170. cd_ratio += 1;
  171. return cd_ratio;
  172. }
  173. static int socfpga_a10_fpga_set_cdratio(struct fpga_manager *mgr,
  174. unsigned int cfg_width,
  175. const char *buf, size_t count)
  176. {
  177. struct a10_fpga_priv *priv = mgr->priv;
  178. unsigned int cd_ratio;
  179. int encrypt, compress;
  180. encrypt = socfpga_a10_fpga_encrypted((u32 *)buf, count / 4);
  181. if (encrypt < 0)
  182. return -EINVAL;
  183. compress = socfpga_a10_fpga_compressed((u32 *)buf, count / 4);
  184. if (compress < 0)
  185. return -EINVAL;
  186. cd_ratio = socfpga_a10_fpga_get_cd_ratio(cfg_width, encrypt, compress);
  187. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
  188. A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK,
  189. cd_ratio << A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT);
  190. return 0;
  191. }
  192. static u32 socfpga_a10_fpga_read_stat(struct a10_fpga_priv *priv)
  193. {
  194. u32 val;
  195. regmap_read(priv->regmap, A10_FPGAMGR_IMGCFG_STAT_OFST, &val);
  196. return val;
  197. }
  198. static int socfpga_a10_fpga_wait_for_pr_ready(struct a10_fpga_priv *priv)
  199. {
  200. u32 reg, i;
  201. for (i = 0; i < 10 ; i++) {
  202. reg = socfpga_a10_fpga_read_stat(priv);
  203. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR)
  204. return -EINVAL;
  205. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY)
  206. return 0;
  207. }
  208. return -ETIMEDOUT;
  209. }
  210. static int socfpga_a10_fpga_wait_for_pr_done(struct a10_fpga_priv *priv)
  211. {
  212. u32 reg, i;
  213. for (i = 0; i < 10 ; i++) {
  214. reg = socfpga_a10_fpga_read_stat(priv);
  215. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR)
  216. return -EINVAL;
  217. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE)
  218. return 0;
  219. }
  220. return -ETIMEDOUT;
  221. }
  222. /* Start the FPGA programming by initialize the FPGA Manager */
  223. static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr,
  224. struct fpga_image_info *info,
  225. const char *buf, size_t count)
  226. {
  227. struct a10_fpga_priv *priv = mgr->priv;
  228. unsigned int cfg_width;
  229. u32 msel, stat, mask;
  230. int ret;
  231. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG)
  232. cfg_width = CFGWDTH_16;
  233. else
  234. return -EINVAL;
  235. /* Check for passive parallel (msel == 000 or 001) */
  236. msel = socfpga_a10_fpga_read_stat(priv);
  237. msel &= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK;
  238. msel >>= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT;
  239. if ((msel != 0) && (msel != 1)) {
  240. dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel);
  241. return -EINVAL;
  242. }
  243. /* Make sure no external devices are interfering */
  244. stat = socfpga_a10_fpga_read_stat(priv);
  245. mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN |
  246. A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
  247. if ((stat & mask) != mask)
  248. return -EINVAL;
  249. /* Set cfg width */
  250. socfpga_a10_fpga_set_cfg_width(priv, cfg_width);
  251. /* Determine cd ratio from bitstream header and set cd ratio */
  252. ret = socfpga_a10_fpga_set_cdratio(mgr, cfg_width, buf, count);
  253. if (ret)
  254. return ret;
  255. /*
  256. * Clear s2f_nce to enable chip select. Leave pr_request
  257. * unasserted and override disabled.
  258. */
  259. regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  260. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG);
  261. /* Set cfg_ctrl to enable s2f dclk and data */
  262. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
  263. A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL,
  264. A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL);
  265. /*
  266. * Disable overrides not needed for pr.
  267. * s2f_config==1 leaves reset deasseted.
  268. */
  269. regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_00_OFST,
  270. A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG |
  271. A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS |
  272. A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE |
  273. A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG);
  274. /* Enable override for data, dclk, nce, and pr_request to CSS */
  275. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  276. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG, 0);
  277. /* Send some clocks to clear out any errors */
  278. socfpga_a10_fpga_generate_dclks(priv, 256);
  279. /* Assert pr_request */
  280. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  281. A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST,
  282. A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST);
  283. /* Provide 2048 DCLKs before starting the config data streaming. */
  284. socfpga_a10_fpga_generate_dclks(priv, 0x7ff);
  285. /* Wait for pr_ready */
  286. return socfpga_a10_fpga_wait_for_pr_ready(priv);
  287. }
  288. /*
  289. * write data to the FPGA data register
  290. */
  291. static int socfpga_a10_fpga_write(struct fpga_manager *mgr, const char *buf,
  292. size_t count)
  293. {
  294. struct a10_fpga_priv *priv = mgr->priv;
  295. u32 *buffer_32 = (u32 *)buf;
  296. size_t i = 0;
  297. if (count <= 0)
  298. return -EINVAL;
  299. /* Write out the complete 32-bit chunks */
  300. while (count >= sizeof(u32)) {
  301. writel(buffer_32[i++], priv->fpga_data_addr);
  302. count -= sizeof(u32);
  303. }
  304. /* Write out remaining non 32-bit chunks */
  305. switch (count) {
  306. case 3:
  307. writel(buffer_32[i++] & 0x00ffffff, priv->fpga_data_addr);
  308. break;
  309. case 2:
  310. writel(buffer_32[i++] & 0x0000ffff, priv->fpga_data_addr);
  311. break;
  312. case 1:
  313. writel(buffer_32[i++] & 0x000000ff, priv->fpga_data_addr);
  314. break;
  315. case 0:
  316. break;
  317. default:
  318. /* This will never happen */
  319. return -EFAULT;
  320. }
  321. return 0;
  322. }
  323. static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr,
  324. struct fpga_image_info *info)
  325. {
  326. struct a10_fpga_priv *priv = mgr->priv;
  327. u32 reg;
  328. int ret;
  329. /* Wait for pr_done */
  330. ret = socfpga_a10_fpga_wait_for_pr_done(priv);
  331. /* Clear pr_request */
  332. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  333. A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST, 0);
  334. /* Send some clocks to clear out any errors */
  335. socfpga_a10_fpga_generate_dclks(priv, 256);
  336. /* Disable s2f dclk and data */
  337. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
  338. A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL, 0);
  339. /* Deassert chip select */
  340. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  341. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE,
  342. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE);
  343. /* Disable data, dclk, nce, and pr_request override to CSS */
  344. regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
  345. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG,
  346. A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG);
  347. /* Return any errors regarding pr_done or pr_error */
  348. if (ret)
  349. return ret;
  350. /* Final check */
  351. reg = socfpga_a10_fpga_read_stat(priv);
  352. if (((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) == 0) ||
  353. ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN) == 0) ||
  354. ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)) {
  355. dev_dbg(&mgr->dev,
  356. "Timeout in final check. Status=%08xf\n", reg);
  357. return -ETIMEDOUT;
  358. }
  359. return 0;
  360. }
  361. static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr)
  362. {
  363. struct a10_fpga_priv *priv = mgr->priv;
  364. u32 reg = socfpga_a10_fpga_read_stat(priv);
  365. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE)
  366. return FPGA_MGR_STATE_OPERATING;
  367. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY)
  368. return FPGA_MGR_STATE_WRITE;
  369. if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR)
  370. return FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
  371. if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)
  372. return FPGA_MGR_STATE_RESET;
  373. return FPGA_MGR_STATE_UNKNOWN;
  374. }
  375. static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = {
  376. .initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4,
  377. .state = socfpga_a10_fpga_state,
  378. .write_init = socfpga_a10_fpga_write_init,
  379. .write = socfpga_a10_fpga_write,
  380. .write_complete = socfpga_a10_fpga_write_complete,
  381. };
  382. static int socfpga_a10_fpga_probe(struct platform_device *pdev)
  383. {
  384. struct device *dev = &pdev->dev;
  385. struct a10_fpga_priv *priv;
  386. void __iomem *reg_base;
  387. struct fpga_manager *mgr;
  388. struct resource *res;
  389. int ret;
  390. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  391. if (!priv)
  392. return -ENOMEM;
  393. /* First mmio base is for register access */
  394. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  395. reg_base = devm_ioremap_resource(dev, res);
  396. if (IS_ERR(reg_base))
  397. return PTR_ERR(reg_base);
  398. /* Second mmio base is for writing FPGA image data */
  399. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  400. priv->fpga_data_addr = devm_ioremap_resource(dev, res);
  401. if (IS_ERR(priv->fpga_data_addr))
  402. return PTR_ERR(priv->fpga_data_addr);
  403. /* regmap for register access */
  404. priv->regmap = devm_regmap_init_mmio(dev, reg_base,
  405. &socfpga_a10_fpga_regmap_config);
  406. if (IS_ERR(priv->regmap))
  407. return -ENODEV;
  408. priv->clk = devm_clk_get(dev, NULL);
  409. if (IS_ERR(priv->clk)) {
  410. dev_err(dev, "no clock specified\n");
  411. return PTR_ERR(priv->clk);
  412. }
  413. ret = clk_prepare_enable(priv->clk);
  414. if (ret) {
  415. dev_err(dev, "could not enable clock\n");
  416. return -EBUSY;
  417. }
  418. mgr = devm_fpga_mgr_create(dev, "SoCFPGA Arria10 FPGA Manager",
  419. &socfpga_a10_fpga_mgr_ops, priv);
  420. if (!mgr)
  421. return -ENOMEM;
  422. platform_set_drvdata(pdev, mgr);
  423. ret = fpga_mgr_register(mgr);
  424. if (ret) {
  425. clk_disable_unprepare(priv->clk);
  426. return ret;
  427. }
  428. return 0;
  429. }
  430. static int socfpga_a10_fpga_remove(struct platform_device *pdev)
  431. {
  432. struct fpga_manager *mgr = platform_get_drvdata(pdev);
  433. struct a10_fpga_priv *priv = mgr->priv;
  434. fpga_mgr_unregister(mgr);
  435. clk_disable_unprepare(priv->clk);
  436. return 0;
  437. }
  438. static const struct of_device_id socfpga_a10_fpga_of_match[] = {
  439. { .compatible = "altr,socfpga-a10-fpga-mgr", },
  440. {},
  441. };
  442. MODULE_DEVICE_TABLE(of, socfpga_a10_fpga_of_match);
  443. static struct platform_driver socfpga_a10_fpga_driver = {
  444. .probe = socfpga_a10_fpga_probe,
  445. .remove = socfpga_a10_fpga_remove,
  446. .driver = {
  447. .name = "socfpga_a10_fpga_manager",
  448. .of_match_table = socfpga_a10_fpga_of_match,
  449. },
  450. };
  451. module_platform_driver(socfpga_a10_fpga_driver);
  452. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  453. MODULE_DESCRIPTION("SoCFPGA Arria10 FPGA Manager");
  454. MODULE_LICENSE("GPL v2");