dfl-fme-pr.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for FPGA Management Engine (FME) Partial Reconfiguration
  4. *
  5. * Copyright (C) 2017-2018 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Kang Luwei <luwei.kang@intel.com>
  9. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  10. * Wu Hao <hao.wu@intel.com>
  11. * Joseph Grecco <joe.grecco@intel.com>
  12. * Enno Luebbers <enno.luebbers@intel.com>
  13. * Tim Whisonant <tim.whisonant@intel.com>
  14. * Ananda Ravuri <ananda.ravuri@intel.com>
  15. * Christopher Rauer <christopher.rauer@intel.com>
  16. * Henry Mitchel <henry.mitchel@intel.com>
  17. */
  18. #include <linux/types.h>
  19. #include <linux/device.h>
  20. #include <linux/vmalloc.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/fpga/fpga-mgr.h>
  23. #include <linux/fpga/fpga-bridge.h>
  24. #include <linux/fpga/fpga-region.h>
  25. #include <linux/fpga-dfl.h>
  26. #include "dfl.h"
  27. #include "dfl-fme.h"
  28. #include "dfl-fme-pr.h"
  29. static struct dfl_fme_region *
  30. dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
  31. {
  32. struct dfl_fme_region *fme_region;
  33. list_for_each_entry(fme_region, &fme->region_list, node)
  34. if (fme_region->port_id == port_id)
  35. return fme_region;
  36. return NULL;
  37. }
  38. static int dfl_fme_region_match(struct device *dev, const void *data)
  39. {
  40. return dev->parent == data;
  41. }
  42. static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
  43. {
  44. struct dfl_fme_region *fme_region;
  45. struct fpga_region *region;
  46. fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
  47. if (!fme_region)
  48. return NULL;
  49. region = fpga_region_class_find(NULL, &fme_region->region->dev,
  50. dfl_fme_region_match);
  51. if (!region)
  52. return NULL;
  53. return region;
  54. }
  55. static int fme_pr(struct platform_device *pdev, unsigned long arg)
  56. {
  57. struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
  58. void __user *argp = (void __user *)arg;
  59. struct dfl_fpga_fme_port_pr port_pr;
  60. struct fpga_image_info *info;
  61. struct fpga_region *region;
  62. void __iomem *fme_hdr;
  63. struct dfl_fme *fme;
  64. unsigned long minsz;
  65. void *buf = NULL;
  66. size_t length;
  67. int ret = 0;
  68. u64 v;
  69. minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
  70. if (copy_from_user(&port_pr, argp, minsz))
  71. return -EFAULT;
  72. if (port_pr.argsz < minsz || port_pr.flags)
  73. return -EINVAL;
  74. /* get fme header region */
  75. fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
  76. FME_FEATURE_ID_HEADER);
  77. /* check port id */
  78. v = readq(fme_hdr + FME_HDR_CAP);
  79. if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
  80. dev_dbg(&pdev->dev, "port number more than maximum\n");
  81. return -EINVAL;
  82. }
  83. /*
  84. * align PR buffer per PR bandwidth, as HW ignores the extra padding
  85. * data automatically.
  86. */
  87. length = ALIGN(port_pr.buffer_size, 4);
  88. buf = vmalloc(length);
  89. if (!buf)
  90. return -ENOMEM;
  91. if (copy_from_user(buf,
  92. (void __user *)(unsigned long)port_pr.buffer_address,
  93. port_pr.buffer_size)) {
  94. ret = -EFAULT;
  95. goto free_exit;
  96. }
  97. /* prepare fpga_image_info for PR */
  98. info = fpga_image_info_alloc(&pdev->dev);
  99. if (!info) {
  100. ret = -ENOMEM;
  101. goto free_exit;
  102. }
  103. info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
  104. mutex_lock(&pdata->lock);
  105. fme = dfl_fpga_pdata_get_private(pdata);
  106. /* fme device has been unregistered. */
  107. if (!fme) {
  108. ret = -EINVAL;
  109. goto unlock_exit;
  110. }
  111. region = dfl_fme_region_find(fme, port_pr.port_id);
  112. if (!region) {
  113. ret = -EINVAL;
  114. goto unlock_exit;
  115. }
  116. fpga_image_info_free(region->info);
  117. info->buf = buf;
  118. info->count = length;
  119. info->region_id = port_pr.port_id;
  120. region->info = info;
  121. ret = fpga_region_program_fpga(region);
  122. /*
  123. * it allows userspace to reset the PR region's logic by disabling and
  124. * reenabling the bridge to clear things out between accleration runs.
  125. * so no need to hold the bridges after partial reconfiguration.
  126. */
  127. if (region->get_bridges)
  128. fpga_bridges_put(&region->bridge_list);
  129. put_device(&region->dev);
  130. unlock_exit:
  131. mutex_unlock(&pdata->lock);
  132. free_exit:
  133. vfree(buf);
  134. return ret;
  135. }
  136. /**
  137. * dfl_fme_create_mgr - create fpga mgr platform device as child device
  138. *
  139. * @pdata: fme platform_device's pdata
  140. *
  141. * Return: mgr platform device if successful, and error code otherwise.
  142. */
  143. static struct platform_device *
  144. dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
  145. struct dfl_feature *feature)
  146. {
  147. struct platform_device *mgr, *fme = pdata->dev;
  148. struct dfl_fme_mgr_pdata mgr_pdata;
  149. int ret = -ENOMEM;
  150. if (!feature->ioaddr)
  151. return ERR_PTR(-ENODEV);
  152. mgr_pdata.ioaddr = feature->ioaddr;
  153. /*
  154. * Each FME has only one fpga-mgr, so allocate platform device using
  155. * the same FME platform device id.
  156. */
  157. mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
  158. if (!mgr)
  159. return ERR_PTR(ret);
  160. mgr->dev.parent = &fme->dev;
  161. ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
  162. if (ret)
  163. goto create_mgr_err;
  164. ret = platform_device_add(mgr);
  165. if (ret)
  166. goto create_mgr_err;
  167. return mgr;
  168. create_mgr_err:
  169. platform_device_put(mgr);
  170. return ERR_PTR(ret);
  171. }
  172. /**
  173. * dfl_fme_destroy_mgr - destroy fpga mgr platform device
  174. * @pdata: fme platform device's pdata
  175. */
  176. static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
  177. {
  178. struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
  179. platform_device_unregister(priv->mgr);
  180. }
  181. /**
  182. * dfl_fme_create_bridge - create fme fpga bridge platform device as child
  183. *
  184. * @pdata: fme platform device's pdata
  185. * @port_id: port id for the bridge to be created.
  186. *
  187. * Return: bridge platform device if successful, and error code otherwise.
  188. */
  189. static struct dfl_fme_bridge *
  190. dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
  191. {
  192. struct device *dev = &pdata->dev->dev;
  193. struct dfl_fme_br_pdata br_pdata;
  194. struct dfl_fme_bridge *fme_br;
  195. int ret = -ENOMEM;
  196. fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
  197. if (!fme_br)
  198. return ERR_PTR(ret);
  199. br_pdata.cdev = pdata->dfl_cdev;
  200. br_pdata.port_id = port_id;
  201. fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
  202. PLATFORM_DEVID_AUTO);
  203. if (!fme_br->br)
  204. return ERR_PTR(ret);
  205. fme_br->br->dev.parent = dev;
  206. ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
  207. if (ret)
  208. goto create_br_err;
  209. ret = platform_device_add(fme_br->br);
  210. if (ret)
  211. goto create_br_err;
  212. return fme_br;
  213. create_br_err:
  214. platform_device_put(fme_br->br);
  215. return ERR_PTR(ret);
  216. }
  217. /**
  218. * dfl_fme_destroy_bridge - destroy fpga bridge platform device
  219. * @fme_br: fme bridge to destroy
  220. */
  221. static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
  222. {
  223. platform_device_unregister(fme_br->br);
  224. }
  225. /**
  226. * dfl_fme_destroy_bridge - destroy all fpga bridge platform device
  227. * @pdata: fme platform device's pdata
  228. */
  229. static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
  230. {
  231. struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
  232. struct dfl_fme_bridge *fbridge, *tmp;
  233. list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
  234. list_del(&fbridge->node);
  235. dfl_fme_destroy_bridge(fbridge);
  236. }
  237. }
  238. /**
  239. * dfl_fme_create_region - create fpga region platform device as child
  240. *
  241. * @pdata: fme platform device's pdata
  242. * @mgr: mgr platform device needed for region
  243. * @br: br platform device needed for region
  244. * @port_id: port id
  245. *
  246. * Return: fme region if successful, and error code otherwise.
  247. */
  248. static struct dfl_fme_region *
  249. dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
  250. struct platform_device *mgr,
  251. struct platform_device *br, int port_id)
  252. {
  253. struct dfl_fme_region_pdata region_pdata;
  254. struct device *dev = &pdata->dev->dev;
  255. struct dfl_fme_region *fme_region;
  256. int ret = -ENOMEM;
  257. fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
  258. if (!fme_region)
  259. return ERR_PTR(ret);
  260. region_pdata.mgr = mgr;
  261. region_pdata.br = br;
  262. /*
  263. * Each FPGA device may have more than one port, so allocate platform
  264. * device using the same port platform device id.
  265. */
  266. fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
  267. if (!fme_region->region)
  268. return ERR_PTR(ret);
  269. fme_region->region->dev.parent = dev;
  270. ret = platform_device_add_data(fme_region->region, &region_pdata,
  271. sizeof(region_pdata));
  272. if (ret)
  273. goto create_region_err;
  274. ret = platform_device_add(fme_region->region);
  275. if (ret)
  276. goto create_region_err;
  277. fme_region->port_id = port_id;
  278. return fme_region;
  279. create_region_err:
  280. platform_device_put(fme_region->region);
  281. return ERR_PTR(ret);
  282. }
  283. /**
  284. * dfl_fme_destroy_region - destroy fme region
  285. * @fme_region: fme region to destroy
  286. */
  287. static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
  288. {
  289. platform_device_unregister(fme_region->region);
  290. }
  291. /**
  292. * dfl_fme_destroy_regions - destroy all fme regions
  293. * @pdata: fme platform device's pdata
  294. */
  295. static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
  296. {
  297. struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
  298. struct dfl_fme_region *fme_region, *tmp;
  299. list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
  300. list_del(&fme_region->node);
  301. dfl_fme_destroy_region(fme_region);
  302. }
  303. }
  304. static int pr_mgmt_init(struct platform_device *pdev,
  305. struct dfl_feature *feature)
  306. {
  307. struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
  308. struct dfl_fme_region *fme_region;
  309. struct dfl_fme_bridge *fme_br;
  310. struct platform_device *mgr;
  311. struct dfl_fme *priv;
  312. void __iomem *fme_hdr;
  313. int ret = -ENODEV, i = 0;
  314. u64 fme_cap, port_offset;
  315. fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
  316. FME_FEATURE_ID_HEADER);
  317. mutex_lock(&pdata->lock);
  318. priv = dfl_fpga_pdata_get_private(pdata);
  319. /* Initialize the region and bridge sub device list */
  320. INIT_LIST_HEAD(&priv->region_list);
  321. INIT_LIST_HEAD(&priv->bridge_list);
  322. /* Create fpga mgr platform device */
  323. mgr = dfl_fme_create_mgr(pdata, feature);
  324. if (IS_ERR(mgr)) {
  325. dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
  326. goto unlock;
  327. }
  328. priv->mgr = mgr;
  329. /* Read capability register to check number of regions and bridges */
  330. fme_cap = readq(fme_hdr + FME_HDR_CAP);
  331. for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
  332. port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
  333. if (!(port_offset & FME_PORT_OFST_IMP))
  334. continue;
  335. /* Create bridge for each port */
  336. fme_br = dfl_fme_create_bridge(pdata, i);
  337. if (IS_ERR(fme_br)) {
  338. ret = PTR_ERR(fme_br);
  339. goto destroy_region;
  340. }
  341. list_add(&fme_br->node, &priv->bridge_list);
  342. /* Create region for each port */
  343. fme_region = dfl_fme_create_region(pdata, mgr,
  344. fme_br->br, i);
  345. if (IS_ERR(fme_region)) {
  346. ret = PTR_ERR(fme_region);
  347. goto destroy_region;
  348. }
  349. list_add(&fme_region->node, &priv->region_list);
  350. }
  351. mutex_unlock(&pdata->lock);
  352. return 0;
  353. destroy_region:
  354. dfl_fme_destroy_regions(pdata);
  355. dfl_fme_destroy_bridges(pdata);
  356. dfl_fme_destroy_mgr(pdata);
  357. unlock:
  358. mutex_unlock(&pdata->lock);
  359. return ret;
  360. }
  361. static void pr_mgmt_uinit(struct platform_device *pdev,
  362. struct dfl_feature *feature)
  363. {
  364. struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
  365. mutex_lock(&pdata->lock);
  366. dfl_fme_destroy_regions(pdata);
  367. dfl_fme_destroy_bridges(pdata);
  368. dfl_fme_destroy_mgr(pdata);
  369. mutex_unlock(&pdata->lock);
  370. }
  371. static long fme_pr_ioctl(struct platform_device *pdev,
  372. struct dfl_feature *feature,
  373. unsigned int cmd, unsigned long arg)
  374. {
  375. long ret;
  376. switch (cmd) {
  377. case DFL_FPGA_FME_PORT_PR:
  378. ret = fme_pr(pdev, arg);
  379. break;
  380. default:
  381. ret = -ENODEV;
  382. }
  383. return ret;
  384. }
  385. const struct dfl_feature_id fme_pr_mgmt_id_table[] = {
  386. {.id = FME_FEATURE_ID_PR_MGMT,},
  387. {0}
  388. };
  389. const struct dfl_feature_ops fme_pr_mgmt_ops = {
  390. .init = pr_mgmt_init,
  391. .uinit = pr_mgmt_uinit,
  392. .ioctl = fme_pr_ioctl,
  393. };