dfl-afu-error.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for FPGA Accelerated Function Unit (AFU) Error Reporting
  4. *
  5. * Copyright 2019 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Wu Hao <hao.wu@linux.intel.com>
  9. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  10. * Joseph Grecco <joe.grecco@intel.com>
  11. * Enno Luebbers <enno.luebbers@intel.com>
  12. * Tim Whisonant <tim.whisonant@intel.com>
  13. * Ananda Ravuri <ananda.ravuri@intel.com>
  14. * Mitchel Henry <henry.mitchel@intel.com>
  15. */
  16. #include <linux/fpga-dfl.h>
  17. #include <linux/uaccess.h>
  18. #include "dfl-afu.h"
  19. #define PORT_ERROR_MASK 0x8
  20. #define PORT_ERROR 0x10
  21. #define PORT_FIRST_ERROR 0x18
  22. #define PORT_MALFORMED_REQ0 0x20
  23. #define PORT_MALFORMED_REQ1 0x28
  24. #define ERROR_MASK GENMASK_ULL(63, 0)
  25. /* mask or unmask port errors by the error mask register. */
  26. static void __afu_port_err_mask(struct device *dev, bool mask)
  27. {
  28. void __iomem *base;
  29. base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
  30. writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK);
  31. }
  32. static void afu_port_err_mask(struct device *dev, bool mask)
  33. {
  34. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  35. mutex_lock(&pdata->lock);
  36. __afu_port_err_mask(dev, mask);
  37. mutex_unlock(&pdata->lock);
  38. }
  39. /* clear port errors. */
  40. static int afu_port_err_clear(struct device *dev, u64 err)
  41. {
  42. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  43. struct platform_device *pdev = to_platform_device(dev);
  44. void __iomem *base_err, *base_hdr;
  45. int ret = -EBUSY;
  46. u64 v;
  47. base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
  48. base_hdr = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
  49. mutex_lock(&pdata->lock);
  50. /*
  51. * clear Port Errors
  52. *
  53. * - Check for AP6 State
  54. * - Halt Port by keeping Port in reset
  55. * - Set PORT Error mask to all 1 to mask errors
  56. * - Clear all errors
  57. * - Set Port mask to all 0 to enable errors
  58. * - All errors start capturing new errors
  59. * - Enable Port by pulling the port out of reset
  60. */
  61. /* if device is still in AP6 power state, can not clear any error. */
  62. v = readq(base_hdr + PORT_HDR_STS);
  63. if (FIELD_GET(PORT_STS_PWR_STATE, v) == PORT_STS_PWR_STATE_AP6) {
  64. dev_err(dev, "Could not clear errors, device in AP6 state.\n");
  65. goto done;
  66. }
  67. /* Halt Port by keeping Port in reset */
  68. ret = __afu_port_disable(pdev);
  69. if (ret)
  70. goto done;
  71. /* Mask all errors */
  72. __afu_port_err_mask(dev, true);
  73. /* Clear errors if err input matches with current port errors.*/
  74. v = readq(base_err + PORT_ERROR);
  75. if (v == err) {
  76. writeq(v, base_err + PORT_ERROR);
  77. v = readq(base_err + PORT_FIRST_ERROR);
  78. writeq(v, base_err + PORT_FIRST_ERROR);
  79. } else {
  80. ret = -EINVAL;
  81. }
  82. /* Clear mask */
  83. __afu_port_err_mask(dev, false);
  84. /* Enable the Port by clear the reset */
  85. __afu_port_enable(pdev);
  86. done:
  87. mutex_unlock(&pdata->lock);
  88. return ret;
  89. }
  90. static ssize_t errors_show(struct device *dev, struct device_attribute *attr,
  91. char *buf)
  92. {
  93. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  94. void __iomem *base;
  95. u64 error;
  96. base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
  97. mutex_lock(&pdata->lock);
  98. error = readq(base + PORT_ERROR);
  99. mutex_unlock(&pdata->lock);
  100. return sprintf(buf, "0x%llx\n", (unsigned long long)error);
  101. }
  102. static ssize_t errors_store(struct device *dev, struct device_attribute *attr,
  103. const char *buff, size_t count)
  104. {
  105. u64 value;
  106. int ret;
  107. if (kstrtou64(buff, 0, &value))
  108. return -EINVAL;
  109. ret = afu_port_err_clear(dev, value);
  110. return ret ? ret : count;
  111. }
  112. static DEVICE_ATTR_RW(errors);
  113. static ssize_t first_error_show(struct device *dev,
  114. struct device_attribute *attr, char *buf)
  115. {
  116. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  117. void __iomem *base;
  118. u64 error;
  119. base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
  120. mutex_lock(&pdata->lock);
  121. error = readq(base + PORT_FIRST_ERROR);
  122. mutex_unlock(&pdata->lock);
  123. return sprintf(buf, "0x%llx\n", (unsigned long long)error);
  124. }
  125. static DEVICE_ATTR_RO(first_error);
  126. static ssize_t first_malformed_req_show(struct device *dev,
  127. struct device_attribute *attr,
  128. char *buf)
  129. {
  130. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  131. void __iomem *base;
  132. u64 req0, req1;
  133. base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
  134. mutex_lock(&pdata->lock);
  135. req0 = readq(base + PORT_MALFORMED_REQ0);
  136. req1 = readq(base + PORT_MALFORMED_REQ1);
  137. mutex_unlock(&pdata->lock);
  138. return sprintf(buf, "0x%016llx%016llx\n",
  139. (unsigned long long)req1, (unsigned long long)req0);
  140. }
  141. static DEVICE_ATTR_RO(first_malformed_req);
  142. static struct attribute *port_err_attrs[] = {
  143. &dev_attr_errors.attr,
  144. &dev_attr_first_error.attr,
  145. &dev_attr_first_malformed_req.attr,
  146. NULL,
  147. };
  148. static umode_t port_err_attrs_visible(struct kobject *kobj,
  149. struct attribute *attr, int n)
  150. {
  151. struct device *dev = kobj_to_dev(kobj);
  152. /*
  153. * sysfs entries are visible only if related private feature is
  154. * enumerated.
  155. */
  156. if (!dfl_get_feature_by_id(dev, PORT_FEATURE_ID_ERROR))
  157. return 0;
  158. return attr->mode;
  159. }
  160. const struct attribute_group port_err_group = {
  161. .name = "errors",
  162. .attrs = port_err_attrs,
  163. .is_visible = port_err_attrs_visible,
  164. };
  165. static int port_err_init(struct platform_device *pdev,
  166. struct dfl_feature *feature)
  167. {
  168. afu_port_err_mask(&pdev->dev, false);
  169. return 0;
  170. }
  171. static void port_err_uinit(struct platform_device *pdev,
  172. struct dfl_feature *feature)
  173. {
  174. afu_port_err_mask(&pdev->dev, true);
  175. }
  176. static long
  177. port_err_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
  178. unsigned int cmd, unsigned long arg)
  179. {
  180. switch (cmd) {
  181. case DFL_FPGA_PORT_ERR_GET_IRQ_NUM:
  182. return dfl_feature_ioctl_get_num_irqs(pdev, feature, arg);
  183. case DFL_FPGA_PORT_ERR_SET_IRQ:
  184. return dfl_feature_ioctl_set_irq(pdev, feature, arg);
  185. default:
  186. dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
  187. return -ENODEV;
  188. }
  189. }
  190. const struct dfl_feature_id port_err_id_table[] = {
  191. {.id = PORT_FEATURE_ID_ERROR,},
  192. {0,}
  193. };
  194. const struct dfl_feature_ops port_err_ops = {
  195. .init = port_err_init,
  196. .uinit = port_err_uinit,
  197. .ioctl = port_err_ioctl,
  198. };