altera-ps-spi.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Altera Passive Serial SPI Driver
  4. *
  5. * Copyright (c) 2017 United Western Technologies, Corporation
  6. *
  7. * Joshua Clayton <stillcompiling@gmail.com>
  8. *
  9. * Manage Altera FPGA firmware that is loaded over SPI using the passive
  10. * serial configuration method.
  11. * Firmware must be in binary "rbf" format.
  12. * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
  13. * May work on other Altera FPGAs.
  14. */
  15. #include <linux/bitrev.h>
  16. #include <linux/delay.h>
  17. #include <linux/fpga/fpga-mgr.h>
  18. #include <linux/gpio/consumer.h>
  19. #include <linux/module.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/of_device.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/sizes.h>
  24. enum altera_ps_devtype {
  25. CYCLONE5,
  26. ARRIA10,
  27. };
  28. struct altera_ps_data {
  29. enum altera_ps_devtype devtype;
  30. int status_wait_min_us;
  31. int status_wait_max_us;
  32. int t_cfg_us;
  33. int t_st2ck_us;
  34. };
  35. struct altera_ps_conf {
  36. struct gpio_desc *config;
  37. struct gpio_desc *confd;
  38. struct gpio_desc *status;
  39. struct spi_device *spi;
  40. const struct altera_ps_data *data;
  41. u32 info_flags;
  42. char mgr_name[64];
  43. };
  44. /* | Arria 10 | Cyclone5 | Stratix5 |
  45. * t_CF2ST0 | [; 600] | [; 600] | [; 600] |ns
  46. * t_CFG | [2;] | [2;] | [2;] |µs
  47. * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
  48. * t_CF2ST1 | [; 3000] | [; 1506] | [; 1506] |µs
  49. * t_CF2CK | [3010;] | [1506;] | [1506;] |µs
  50. * t_ST2CK | [10;] | [2;] | [2;] |µs
  51. * t_CD2UM | [175; 830] | [175; 437] | [175; 437] |µs
  52. */
  53. static struct altera_ps_data c5_data = {
  54. /* these values for Cyclone5 are compatible with Stratix5 */
  55. .devtype = CYCLONE5,
  56. .status_wait_min_us = 268,
  57. .status_wait_max_us = 1506,
  58. .t_cfg_us = 2,
  59. .t_st2ck_us = 2,
  60. };
  61. static struct altera_ps_data a10_data = {
  62. .devtype = ARRIA10,
  63. .status_wait_min_us = 268, /* min(t_STATUS) */
  64. .status_wait_max_us = 3000, /* max(t_CF2ST1) */
  65. .t_cfg_us = 2, /* max { min(t_CFG), max(tCF2ST0) } */
  66. .t_st2ck_us = 10, /* min(t_ST2CK) */
  67. };
  68. /* Array index is enum altera_ps_devtype */
  69. static const struct altera_ps_data *altera_ps_data_map[] = {
  70. &c5_data,
  71. &a10_data,
  72. };
  73. static const struct of_device_id of_ef_match[] = {
  74. { .compatible = "altr,fpga-passive-serial", .data = &c5_data },
  75. { .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
  76. {}
  77. };
  78. MODULE_DEVICE_TABLE(of, of_ef_match);
  79. static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
  80. {
  81. struct altera_ps_conf *conf = mgr->priv;
  82. if (gpiod_get_value_cansleep(conf->status))
  83. return FPGA_MGR_STATE_RESET;
  84. return FPGA_MGR_STATE_UNKNOWN;
  85. }
  86. static inline void altera_ps_delay(int delay_us)
  87. {
  88. if (delay_us > 10)
  89. usleep_range(delay_us, delay_us + 5);
  90. else
  91. udelay(delay_us);
  92. }
  93. static int altera_ps_write_init(struct fpga_manager *mgr,
  94. struct fpga_image_info *info,
  95. const char *buf, size_t count)
  96. {
  97. struct altera_ps_conf *conf = mgr->priv;
  98. int min, max, waits;
  99. int i;
  100. conf->info_flags = info->flags;
  101. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
  102. dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
  103. return -EINVAL;
  104. }
  105. gpiod_set_value_cansleep(conf->config, 1);
  106. /* wait min reset pulse time */
  107. altera_ps_delay(conf->data->t_cfg_us);
  108. if (!gpiod_get_value_cansleep(conf->status)) {
  109. dev_err(&mgr->dev, "Status pin failed to show a reset\n");
  110. return -EIO;
  111. }
  112. gpiod_set_value_cansleep(conf->config, 0);
  113. min = conf->data->status_wait_min_us;
  114. max = conf->data->status_wait_max_us;
  115. waits = max / min;
  116. if (max % min)
  117. waits++;
  118. /* wait for max { max(t_STATUS), max(t_CF2ST1) } */
  119. for (i = 0; i < waits; i++) {
  120. usleep_range(min, min + 10);
  121. if (!gpiod_get_value_cansleep(conf->status)) {
  122. /* wait for min(t_ST2CK)*/
  123. altera_ps_delay(conf->data->t_st2ck_us);
  124. return 0;
  125. }
  126. }
  127. dev_err(&mgr->dev, "Status pin not ready.\n");
  128. return -EIO;
  129. }
  130. static void rev_buf(char *buf, size_t len)
  131. {
  132. u32 *fw32 = (u32 *)buf;
  133. size_t extra_bytes = (len & 0x03);
  134. const u32 *fw_end = (u32 *)(buf + len - extra_bytes);
  135. /* set buffer to lsb first */
  136. while (fw32 < fw_end) {
  137. *fw32 = bitrev8x4(*fw32);
  138. fw32++;
  139. }
  140. if (extra_bytes) {
  141. buf = (char *)fw_end;
  142. while (extra_bytes) {
  143. *buf = bitrev8(*buf);
  144. buf++;
  145. extra_bytes--;
  146. }
  147. }
  148. }
  149. static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
  150. size_t count)
  151. {
  152. struct altera_ps_conf *conf = mgr->priv;
  153. const char *fw_data = buf;
  154. const char *fw_data_end = fw_data + count;
  155. while (fw_data < fw_data_end) {
  156. int ret;
  157. size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
  158. if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
  159. rev_buf((char *)fw_data, stride);
  160. ret = spi_write(conf->spi, fw_data, stride);
  161. if (ret) {
  162. dev_err(&mgr->dev, "spi error in firmware write: %d\n",
  163. ret);
  164. return ret;
  165. }
  166. fw_data += stride;
  167. }
  168. return 0;
  169. }
  170. static int altera_ps_write_complete(struct fpga_manager *mgr,
  171. struct fpga_image_info *info)
  172. {
  173. struct altera_ps_conf *conf = mgr->priv;
  174. static const char dummy[] = {0};
  175. int ret;
  176. if (gpiod_get_value_cansleep(conf->status)) {
  177. dev_err(&mgr->dev, "Error during configuration.\n");
  178. return -EIO;
  179. }
  180. if (conf->confd) {
  181. if (!gpiod_get_raw_value_cansleep(conf->confd)) {
  182. dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
  183. return -EIO;
  184. }
  185. }
  186. /*
  187. * After CONF_DONE goes high, send two additional falling edges on DCLK
  188. * to begin initialization and enter user mode
  189. */
  190. ret = spi_write(conf->spi, dummy, 1);
  191. if (ret) {
  192. dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
  193. return ret;
  194. }
  195. return 0;
  196. }
  197. static const struct fpga_manager_ops altera_ps_ops = {
  198. .state = altera_ps_state,
  199. .write_init = altera_ps_write_init,
  200. .write = altera_ps_write,
  201. .write_complete = altera_ps_write_complete,
  202. };
  203. static const struct altera_ps_data *id_to_data(const struct spi_device_id *id)
  204. {
  205. kernel_ulong_t devtype = id->driver_data;
  206. const struct altera_ps_data *data;
  207. /* someone added a altera_ps_devtype without adding to the map array */
  208. if (devtype >= ARRAY_SIZE(altera_ps_data_map))
  209. return NULL;
  210. data = altera_ps_data_map[devtype];
  211. if (!data || data->devtype != devtype)
  212. return NULL;
  213. return data;
  214. }
  215. static int altera_ps_probe(struct spi_device *spi)
  216. {
  217. struct altera_ps_conf *conf;
  218. const struct of_device_id *of_id;
  219. struct fpga_manager *mgr;
  220. conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
  221. if (!conf)
  222. return -ENOMEM;
  223. if (spi->dev.of_node) {
  224. of_id = of_match_device(of_ef_match, &spi->dev);
  225. if (!of_id)
  226. return -ENODEV;
  227. conf->data = of_id->data;
  228. } else {
  229. conf->data = id_to_data(spi_get_device_id(spi));
  230. if (!conf->data)
  231. return -ENODEV;
  232. }
  233. conf->spi = spi;
  234. conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_LOW);
  235. if (IS_ERR(conf->config)) {
  236. dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
  237. PTR_ERR(conf->config));
  238. return PTR_ERR(conf->config);
  239. }
  240. conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
  241. if (IS_ERR(conf->status)) {
  242. dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
  243. PTR_ERR(conf->status));
  244. return PTR_ERR(conf->status);
  245. }
  246. conf->confd = devm_gpiod_get_optional(&spi->dev, "confd", GPIOD_IN);
  247. if (IS_ERR(conf->confd)) {
  248. dev_err(&spi->dev, "Failed to get confd gpio: %ld\n",
  249. PTR_ERR(conf->confd));
  250. return PTR_ERR(conf->confd);
  251. } else if (!conf->confd) {
  252. dev_warn(&spi->dev, "Not using confd gpio");
  253. }
  254. /* Register manager with unique name */
  255. snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
  256. dev_driver_string(&spi->dev), dev_name(&spi->dev));
  257. mgr = devm_fpga_mgr_create(&spi->dev, conf->mgr_name,
  258. &altera_ps_ops, conf);
  259. if (!mgr)
  260. return -ENOMEM;
  261. spi_set_drvdata(spi, mgr);
  262. return fpga_mgr_register(mgr);
  263. }
  264. static int altera_ps_remove(struct spi_device *spi)
  265. {
  266. struct fpga_manager *mgr = spi_get_drvdata(spi);
  267. fpga_mgr_unregister(mgr);
  268. return 0;
  269. }
  270. static const struct spi_device_id altera_ps_spi_ids[] = {
  271. { "cyclone-ps-spi", CYCLONE5 },
  272. { "fpga-passive-serial", CYCLONE5 },
  273. { "fpga-arria10-passive-serial", ARRIA10 },
  274. {}
  275. };
  276. MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
  277. static struct spi_driver altera_ps_driver = {
  278. .driver = {
  279. .name = "altera-ps-spi",
  280. .owner = THIS_MODULE,
  281. .of_match_table = of_match_ptr(of_ef_match),
  282. },
  283. .id_table = altera_ps_spi_ids,
  284. .probe = altera_ps_probe,
  285. .remove = altera_ps_remove,
  286. };
  287. module_spi_driver(altera_ps_driver)
  288. MODULE_LICENSE("GPL v2");
  289. MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
  290. MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");