altera-freeze-bridge.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Freeze Bridge Controller
  4. *
  5. * Copyright (C) 2016 Altera Corporation. All rights reserved.
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/of_device.h>
  11. #include <linux/module.h>
  12. #include <linux/fpga/fpga-bridge.h>
  13. #define FREEZE_CSR_STATUS_OFFSET 0
  14. #define FREEZE_CSR_CTRL_OFFSET 4
  15. #define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8
  16. #define FREEZE_CSR_REG_VERSION 12
  17. #define FREEZE_CSR_SUPPORTED_VERSION 2
  18. #define FREEZE_CSR_OFFICIAL_VERSION 0xad000003
  19. #define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0)
  20. #define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
  21. #define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0)
  22. #define FREEZE_CSR_CTRL_RESET_REQ BIT(1)
  23. #define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2)
  24. #define FREEZE_BRIDGE_NAME "freeze"
  25. struct altera_freeze_br_data {
  26. struct device *dev;
  27. void __iomem *base_addr;
  28. bool enable;
  29. };
  30. /*
  31. * Poll status until status bit is set or we have a timeout.
  32. */
  33. static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
  34. u32 timeout, u32 req_ack)
  35. {
  36. struct device *dev = priv->dev;
  37. void __iomem *csr_illegal_req_addr = priv->base_addr +
  38. FREEZE_CSR_ILLEGAL_REQ_OFFSET;
  39. u32 status, illegal, ctrl;
  40. int ret = -ETIMEDOUT;
  41. do {
  42. illegal = readl(csr_illegal_req_addr);
  43. if (illegal) {
  44. dev_err(dev, "illegal request detected 0x%x", illegal);
  45. writel(1, csr_illegal_req_addr);
  46. illegal = readl(csr_illegal_req_addr);
  47. if (illegal)
  48. dev_err(dev, "illegal request not cleared 0x%x",
  49. illegal);
  50. ret = -EINVAL;
  51. break;
  52. }
  53. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  54. dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
  55. status &= req_ack;
  56. if (status) {
  57. ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
  58. dev_dbg(dev, "%s request %x acknowledged %x %x\n",
  59. __func__, req_ack, status, ctrl);
  60. ret = 0;
  61. break;
  62. }
  63. udelay(1);
  64. } while (timeout--);
  65. if (ret == -ETIMEDOUT)
  66. dev_err(dev, "%s timeout waiting for 0x%x\n",
  67. __func__, req_ack);
  68. return ret;
  69. }
  70. static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
  71. u32 timeout)
  72. {
  73. struct device *dev = priv->dev;
  74. void __iomem *csr_ctrl_addr = priv->base_addr +
  75. FREEZE_CSR_CTRL_OFFSET;
  76. u32 status;
  77. int ret;
  78. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  79. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  80. if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
  81. dev_dbg(dev, "%s bridge already disabled %d\n",
  82. __func__, status);
  83. return 0;
  84. } else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
  85. dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
  86. return -EINVAL;
  87. }
  88. writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
  89. ret = altera_freeze_br_req_ack(priv, timeout,
  90. FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
  91. if (ret)
  92. writel(0, csr_ctrl_addr);
  93. else
  94. writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
  95. return ret;
  96. }
  97. static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
  98. u32 timeout)
  99. {
  100. struct device *dev = priv->dev;
  101. void __iomem *csr_ctrl_addr = priv->base_addr +
  102. FREEZE_CSR_CTRL_OFFSET;
  103. u32 status;
  104. int ret;
  105. writel(0, csr_ctrl_addr);
  106. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  107. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  108. if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
  109. dev_dbg(dev, "%s bridge already enabled %d\n",
  110. __func__, status);
  111. return 0;
  112. } else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
  113. dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
  114. return -EINVAL;
  115. }
  116. writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
  117. ret = altera_freeze_br_req_ack(priv, timeout,
  118. FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
  119. status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
  120. dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
  121. writel(0, csr_ctrl_addr);
  122. return ret;
  123. }
  124. /*
  125. * enable = 1 : allow traffic through the bridge
  126. * enable = 0 : disable traffic through the bridge
  127. */
  128. static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
  129. bool enable)
  130. {
  131. struct altera_freeze_br_data *priv = bridge->priv;
  132. struct fpga_image_info *info = bridge->info;
  133. u32 timeout = 0;
  134. int ret;
  135. if (enable) {
  136. if (info)
  137. timeout = info->enable_timeout_us;
  138. ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
  139. } else {
  140. if (info)
  141. timeout = info->disable_timeout_us;
  142. ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
  143. }
  144. if (!ret)
  145. priv->enable = enable;
  146. return ret;
  147. }
  148. static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
  149. {
  150. struct altera_freeze_br_data *priv = bridge->priv;
  151. return priv->enable;
  152. }
  153. static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
  154. .enable_set = altera_freeze_br_enable_set,
  155. .enable_show = altera_freeze_br_enable_show,
  156. };
  157. static const struct of_device_id altera_freeze_br_of_match[] = {
  158. { .compatible = "altr,freeze-bridge-controller", },
  159. {},
  160. };
  161. MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
  162. static int altera_freeze_br_probe(struct platform_device *pdev)
  163. {
  164. struct device *dev = &pdev->dev;
  165. struct device_node *np = pdev->dev.of_node;
  166. void __iomem *base_addr;
  167. struct altera_freeze_br_data *priv;
  168. struct fpga_bridge *br;
  169. struct resource *res;
  170. u32 status, revision;
  171. if (!np)
  172. return -ENODEV;
  173. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  174. base_addr = devm_ioremap_resource(dev, res);
  175. if (IS_ERR(base_addr))
  176. return PTR_ERR(base_addr);
  177. revision = readl(base_addr + FREEZE_CSR_REG_VERSION);
  178. if ((revision != FREEZE_CSR_SUPPORTED_VERSION) &&
  179. (revision != FREEZE_CSR_OFFICIAL_VERSION)) {
  180. dev_err(dev,
  181. "%s unexpected revision 0x%x != 0x%x != 0x%x\n",
  182. __func__, revision, FREEZE_CSR_SUPPORTED_VERSION,
  183. FREEZE_CSR_OFFICIAL_VERSION);
  184. return -EINVAL;
  185. }
  186. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  187. if (!priv)
  188. return -ENOMEM;
  189. priv->dev = dev;
  190. status = readl(base_addr + FREEZE_CSR_STATUS_OFFSET);
  191. if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
  192. priv->enable = 1;
  193. priv->base_addr = base_addr;
  194. br = devm_fpga_bridge_create(dev, FREEZE_BRIDGE_NAME,
  195. &altera_freeze_br_br_ops, priv);
  196. if (!br)
  197. return -ENOMEM;
  198. platform_set_drvdata(pdev, br);
  199. return fpga_bridge_register(br);
  200. }
  201. static int altera_freeze_br_remove(struct platform_device *pdev)
  202. {
  203. struct fpga_bridge *br = platform_get_drvdata(pdev);
  204. fpga_bridge_unregister(br);
  205. return 0;
  206. }
  207. static struct platform_driver altera_freeze_br_driver = {
  208. .probe = altera_freeze_br_probe,
  209. .remove = altera_freeze_br_remove,
  210. .driver = {
  211. .name = "altera_freeze_br",
  212. .of_match_table = of_match_ptr(altera_freeze_br_of_match),
  213. },
  214. };
  215. module_platform_driver(altera_freeze_br_driver);
  216. MODULE_DESCRIPTION("Altera Freeze Bridge");
  217. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  218. MODULE_LICENSE("GPL v2");