altera-fpga2sdram.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
  4. *
  5. * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
  6. */
  7. /*
  8. * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
  9. * host processor system (HPS).
  10. *
  11. * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
  12. * Reconfiguring these ports requires that no SDRAM transactions occur during
  13. * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM
  14. * nor can the FPGA access the SDRAM during reconfiguration. This driver does
  15. * not support reconfiguring the ports. The ports are configured by code
  16. * running out of on chip ram before Linux is started and the configuration
  17. * is passed in a handoff register in the system manager.
  18. *
  19. * This driver supports enabling and disabling of the configured ports, which
  20. * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
  21. * uses the same port configuration. Bridges must be disabled before
  22. * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
  23. */
  24. #include <linux/fpga/fpga-bridge.h>
  25. #include <linux/kernel.h>
  26. #include <linux/mfd/syscon.h>
  27. #include <linux/module.h>
  28. #include <linux/of_platform.h>
  29. #include <linux/regmap.h>
  30. #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
  31. #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK 0x00003fff
  32. #define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT 0
  33. #define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT 4
  34. #define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT 8
  35. /*
  36. * From the Cyclone V HPS Memory Map document:
  37. * These registers are used to store handoff information between the
  38. * preloader and the OS. These 8 registers can be used to store any
  39. * information. The contents of these registers have no impact on
  40. * the state of the HPS hardware.
  41. */
  42. #define SYSMGR_ISWGRP_HANDOFF3 (0x8C)
  43. #define F2S_BRIDGE_NAME "fpga2sdram"
  44. struct alt_fpga2sdram_data {
  45. struct device *dev;
  46. struct regmap *sdrctl;
  47. int mask;
  48. };
  49. static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge)
  50. {
  51. struct alt_fpga2sdram_data *priv = bridge->priv;
  52. int value;
  53. regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value);
  54. return (value & priv->mask) == priv->mask;
  55. }
  56. static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv,
  57. bool enable)
  58. {
  59. return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST,
  60. priv->mask, enable ? priv->mask : 0);
  61. }
  62. static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable)
  63. {
  64. return _alt_fpga2sdram_enable_set(bridge->priv, enable);
  65. }
  66. struct prop_map {
  67. char *prop_name;
  68. u32 *prop_value;
  69. u32 prop_max;
  70. };
  71. static const struct fpga_bridge_ops altera_fpga2sdram_br_ops = {
  72. .enable_set = alt_fpga2sdram_enable_set,
  73. .enable_show = alt_fpga2sdram_enable_show,
  74. };
  75. static const struct of_device_id altera_fpga_of_match[] = {
  76. { .compatible = "altr,socfpga-fpga2sdram-bridge" },
  77. {},
  78. };
  79. static int alt_fpga_bridge_probe(struct platform_device *pdev)
  80. {
  81. struct device *dev = &pdev->dev;
  82. struct alt_fpga2sdram_data *priv;
  83. struct fpga_bridge *br;
  84. u32 enable;
  85. struct regmap *sysmgr;
  86. int ret = 0;
  87. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  88. if (!priv)
  89. return -ENOMEM;
  90. priv->dev = dev;
  91. priv->sdrctl = syscon_regmap_lookup_by_compatible("altr,sdr-ctl");
  92. if (IS_ERR(priv->sdrctl)) {
  93. dev_err(dev, "regmap for altr,sdr-ctl lookup failed.\n");
  94. return PTR_ERR(priv->sdrctl);
  95. }
  96. sysmgr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
  97. if (IS_ERR(sysmgr)) {
  98. dev_err(dev, "regmap for altr,sys-mgr lookup failed.\n");
  99. return PTR_ERR(sysmgr);
  100. }
  101. /* Get f2s bridge configuration saved in handoff register */
  102. regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask);
  103. br = devm_fpga_bridge_create(dev, F2S_BRIDGE_NAME,
  104. &altera_fpga2sdram_br_ops, priv);
  105. if (!br)
  106. return -ENOMEM;
  107. platform_set_drvdata(pdev, br);
  108. ret = fpga_bridge_register(br);
  109. if (ret)
  110. return ret;
  111. dev_info(dev, "driver initialized with handoff %08x\n", priv->mask);
  112. if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
  113. if (enable > 1) {
  114. dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
  115. } else {
  116. dev_info(dev, "%s bridge\n",
  117. (enable ? "enabling" : "disabling"));
  118. ret = _alt_fpga2sdram_enable_set(priv, enable);
  119. if (ret) {
  120. fpga_bridge_unregister(br);
  121. return ret;
  122. }
  123. }
  124. }
  125. return ret;
  126. }
  127. static int alt_fpga_bridge_remove(struct platform_device *pdev)
  128. {
  129. struct fpga_bridge *br = platform_get_drvdata(pdev);
  130. fpga_bridge_unregister(br);
  131. return 0;
  132. }
  133. MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
  134. static struct platform_driver altera_fpga_driver = {
  135. .probe = alt_fpga_bridge_probe,
  136. .remove = alt_fpga_bridge_remove,
  137. .driver = {
  138. .name = "altera_fpga2sdram_bridge",
  139. .of_match_table = of_match_ptr(altera_fpga_of_match),
  140. },
  141. };
  142. module_platform_driver(altera_fpga_driver);
  143. MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
  144. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  145. MODULE_LICENSE("GPL v2");