ti_sci.h 53 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Texas Instruments System Control Interface (TISCI) Protocol
  4. *
  5. * Communication protocol with TI SCI hardware
  6. * The system works in a message response protocol
  7. * See: http://processors.wiki.ti.com/index.php/TISCI for details
  8. *
  9. * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  10. */
  11. #ifndef __TI_SCI_H
  12. #define __TI_SCI_H
  13. /* Generic Messages */
  14. #define TI_SCI_MSG_ENABLE_WDT 0x0000
  15. #define TI_SCI_MSG_WAKE_RESET 0x0001
  16. #define TI_SCI_MSG_VERSION 0x0002
  17. #define TI_SCI_MSG_WAKE_REASON 0x0003
  18. #define TI_SCI_MSG_GOODBYE 0x0004
  19. #define TI_SCI_MSG_SYS_RESET 0x0005
  20. /* Device requests */
  21. #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
  22. #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
  23. #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
  24. /* Clock requests */
  25. #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
  26. #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
  27. #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
  28. #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
  29. #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
  30. #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
  31. #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
  32. #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
  33. /* Resource Management Requests */
  34. #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
  35. /* IRQ requests */
  36. #define TI_SCI_MSG_SET_IRQ 0x1000
  37. #define TI_SCI_MSG_FREE_IRQ 0x1001
  38. /* NAVSS resource management */
  39. /* Ringacc requests */
  40. #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
  41. #define TI_SCI_MSG_RM_RING_FREE 0x1101
  42. #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
  43. #define TI_SCI_MSG_RM_RING_RESET 0x1103
  44. #define TI_SCI_MSG_RM_RING_CFG 0x1110
  45. #define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
  46. /* PSI-L requests */
  47. #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
  48. #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
  49. #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
  50. #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
  51. #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
  52. #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
  53. #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
  54. #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
  55. #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
  56. #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
  57. #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
  58. #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
  59. #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
  60. #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
  61. #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
  62. #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
  63. /* Processor Control requests */
  64. #define TI_SCI_MSG_PROC_REQUEST 0xc000
  65. #define TI_SCI_MSG_PROC_RELEASE 0xc001
  66. #define TI_SCI_MSG_PROC_HANDOVER 0xc005
  67. #define TI_SCI_MSG_SET_CONFIG 0xc100
  68. #define TI_SCI_MSG_SET_CTRL 0xc101
  69. #define TI_SCI_MSG_GET_STATUS 0xc400
  70. /**
  71. * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
  72. * @type: Type of messages: One of TI_SCI_MSG* values
  73. * @host: Host of the message
  74. * @seq: Message identifier indicating a transfer sequence
  75. * @flags: Flag for the message
  76. */
  77. struct ti_sci_msg_hdr {
  78. u16 type;
  79. u8 host;
  80. u8 seq;
  81. #define TI_SCI_MSG_FLAG(val) (1 << (val))
  82. #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
  83. #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
  84. #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
  85. #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
  86. #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
  87. /* Additional Flags */
  88. u32 flags;
  89. } __packed;
  90. /**
  91. * struct ti_sci_msg_resp_version - Response for a message
  92. * @hdr: Generic header
  93. * @firmware_description: String describing the firmware
  94. * @firmware_revision: Firmware revision
  95. * @abi_major: Major version of the ABI that firmware supports
  96. * @abi_minor: Minor version of the ABI that firmware supports
  97. *
  98. * In general, ABI version changes follow the rule that minor version increments
  99. * are backward compatible. Major revision changes in ABI may not be
  100. * backward compatible.
  101. *
  102. * Response to a generic message with message type TI_SCI_MSG_VERSION
  103. */
  104. struct ti_sci_msg_resp_version {
  105. struct ti_sci_msg_hdr hdr;
  106. char firmware_description[32];
  107. u16 firmware_revision;
  108. u8 abi_major;
  109. u8 abi_minor;
  110. } __packed;
  111. /**
  112. * struct ti_sci_msg_req_reboot - Reboot the SoC
  113. * @hdr: Generic Header
  114. *
  115. * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
  116. * ACK/NACK message.
  117. */
  118. struct ti_sci_msg_req_reboot {
  119. struct ti_sci_msg_hdr hdr;
  120. } __packed;
  121. /**
  122. * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
  123. * @hdr: Generic header
  124. * @id: Indicates which device to modify
  125. * @reserved: Reserved space in message, must be 0 for backward compatibility
  126. * @state: The desired state of the device.
  127. *
  128. * Certain flags can also be set to alter the device state:
  129. * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
  130. * The meaning of this flag will vary slightly from device to device and from
  131. * SoC to SoC but it generally allows the device to wake the SoC out of deep
  132. * suspend states.
  133. * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
  134. * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
  135. * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
  136. * If another host already has this device set to STATE_RETENTION or STATE_ON,
  137. * the message will fail. Once successful, other hosts attempting to set
  138. * STATE_RETENTION or STATE_ON will fail.
  139. *
  140. * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
  141. * ACK/NACK message.
  142. */
  143. struct ti_sci_msg_req_set_device_state {
  144. /* Additional hdr->flags options */
  145. #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
  146. #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
  147. #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
  148. struct ti_sci_msg_hdr hdr;
  149. u32 id;
  150. u32 reserved;
  151. #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
  152. #define MSG_DEVICE_SW_STATE_RETENTION 1
  153. #define MSG_DEVICE_SW_STATE_ON 2
  154. u8 state;
  155. } __packed;
  156. /**
  157. * struct ti_sci_msg_req_get_device_state - Request to get device.
  158. * @hdr: Generic header
  159. * @id: Device Identifier
  160. *
  161. * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
  162. * information
  163. */
  164. struct ti_sci_msg_req_get_device_state {
  165. struct ti_sci_msg_hdr hdr;
  166. u32 id;
  167. } __packed;
  168. /**
  169. * struct ti_sci_msg_resp_get_device_state - Response to get device request.
  170. * @hdr: Generic header
  171. * @context_loss_count: Indicates how many times the device has lost context. A
  172. * driver can use this monotonic counter to determine if the device has
  173. * lost context since the last time this message was exchanged.
  174. * @resets: Programmed state of the reset lines.
  175. * @programmed_state: The state as programmed by set_device.
  176. * - Uses the MSG_DEVICE_SW_* macros
  177. * @current_state: The actual state of the hardware.
  178. *
  179. * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
  180. */
  181. struct ti_sci_msg_resp_get_device_state {
  182. struct ti_sci_msg_hdr hdr;
  183. u32 context_loss_count;
  184. u32 resets;
  185. u8 programmed_state;
  186. #define MSG_DEVICE_HW_STATE_OFF 0
  187. #define MSG_DEVICE_HW_STATE_ON 1
  188. #define MSG_DEVICE_HW_STATE_TRANS 2
  189. u8 current_state;
  190. } __packed;
  191. /**
  192. * struct ti_sci_msg_req_set_device_resets - Set the desired resets
  193. * configuration of the device
  194. * @hdr: Generic header
  195. * @id: Indicates which device to modify
  196. * @resets: A bit field of resets for the device. The meaning, behavior,
  197. * and usage of the reset flags are device specific. 0 for a bit
  198. * indicates releasing the reset represented by that bit while 1
  199. * indicates keeping it held.
  200. *
  201. * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
  202. * ACK/NACK message.
  203. */
  204. struct ti_sci_msg_req_set_device_resets {
  205. struct ti_sci_msg_hdr hdr;
  206. u32 id;
  207. u32 resets;
  208. } __packed;
  209. /**
  210. * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
  211. * @hdr: Generic Header, Certain flags can be set specific to the clocks:
  212. * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
  213. * via spread spectrum clocking.
  214. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
  215. * frequency to be changed while it is running so long as it
  216. * is within the min/max limits.
  217. * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
  218. * is only applicable to clock inputs on the SoC pseudo-device.
  219. * @dev_id: Device identifier this request is for
  220. * @clk_id: Clock identifier for the device for this request.
  221. * Each device has it's own set of clock inputs. This indexes
  222. * which clock input to modify. Set to 255 if clock ID is
  223. * greater than or equal to 255.
  224. * @request_state: Request the state for the clock to be set to.
  225. * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
  226. * it can be disabled, regardless of the state of the device
  227. * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
  228. * automatically manage the state of this clock. If the device
  229. * is enabled, then the clock is enabled. If the device is set
  230. * to off or retention, then the clock is internally set as not
  231. * being required by the device.(default)
  232. * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
  233. * regardless of the state of the device.
  234. * @clk_id_32: Clock identifier for the device for this request.
  235. * Only to be used if the clock ID is greater than or equal to
  236. * 255.
  237. *
  238. * Normally, all required clocks are managed by TISCI entity, this is used
  239. * only for specific control *IF* required. Auto managed state is
  240. * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
  241. * will explicitly control.
  242. *
  243. * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
  244. * ACK or NACK message.
  245. */
  246. struct ti_sci_msg_req_set_clock_state {
  247. /* Additional hdr->flags options */
  248. #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
  249. #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
  250. #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
  251. struct ti_sci_msg_hdr hdr;
  252. u32 dev_id;
  253. u8 clk_id;
  254. #define MSG_CLOCK_SW_STATE_UNREQ 0
  255. #define MSG_CLOCK_SW_STATE_AUTO 1
  256. #define MSG_CLOCK_SW_STATE_REQ 2
  257. u8 request_state;
  258. u32 clk_id_32;
  259. } __packed;
  260. /**
  261. * struct ti_sci_msg_req_get_clock_state - Request for clock state
  262. * @hdr: Generic Header
  263. * @dev_id: Device identifier this request is for
  264. * @clk_id: Clock identifier for the device for this request.
  265. * Each device has it's own set of clock inputs. This indexes
  266. * which clock input to get state of. Set to 255 if the clock
  267. * ID is greater than or equal to 255.
  268. * @clk_id_32: Clock identifier for the device for the request.
  269. * Only to be used if the clock ID is greater than or equal to
  270. * 255.
  271. *
  272. * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
  273. * of the clock
  274. */
  275. struct ti_sci_msg_req_get_clock_state {
  276. struct ti_sci_msg_hdr hdr;
  277. u32 dev_id;
  278. u8 clk_id;
  279. u32 clk_id_32;
  280. } __packed;
  281. /**
  282. * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
  283. * @hdr: Generic Header
  284. * @programmed_state: Any programmed state of the clock. This is one of
  285. * MSG_CLOCK_SW_STATE* values.
  286. * @current_state: Current state of the clock. This is one of:
  287. * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
  288. * MSG_CLOCK_HW_STATE_READY: Clock is ready
  289. *
  290. * Response to TI_SCI_MSG_GET_CLOCK_STATE.
  291. */
  292. struct ti_sci_msg_resp_get_clock_state {
  293. struct ti_sci_msg_hdr hdr;
  294. u8 programmed_state;
  295. #define MSG_CLOCK_HW_STATE_NOT_READY 0
  296. #define MSG_CLOCK_HW_STATE_READY 1
  297. u8 current_state;
  298. } __packed;
  299. /**
  300. * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
  301. * @hdr: Generic Header
  302. * @dev_id: Device identifier this request is for
  303. * @clk_id: Clock identifier for the device for this request.
  304. * Each device has it's own set of clock inputs. This indexes
  305. * which clock input to modify. Set to 255 if clock ID is
  306. * greater than or equal to 255.
  307. * @parent_id: The new clock parent is selectable by an index via this
  308. * parameter. Set to 255 if clock ID is greater than or
  309. * equal to 255.
  310. * @clk_id_32: Clock identifier if @clk_id field is 255.
  311. * @parent_id_32: Parent identifier if @parent_id is 255.
  312. *
  313. * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
  314. * ACK / NACK message.
  315. */
  316. struct ti_sci_msg_req_set_clock_parent {
  317. struct ti_sci_msg_hdr hdr;
  318. u32 dev_id;
  319. u8 clk_id;
  320. u8 parent_id;
  321. u32 clk_id_32;
  322. u32 parent_id_32;
  323. } __packed;
  324. /**
  325. * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
  326. * @hdr: Generic Header
  327. * @dev_id: Device identifier this request is for
  328. * @clk_id: Clock identifier for the device for this request.
  329. * Each device has it's own set of clock inputs. This indexes
  330. * which clock input to get the parent for. If this field
  331. * contains 255, the actual clock identifier is stored in
  332. * @clk_id_32.
  333. * @clk_id_32: Clock identifier if the @clk_id field contains 255.
  334. *
  335. * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
  336. */
  337. struct ti_sci_msg_req_get_clock_parent {
  338. struct ti_sci_msg_hdr hdr;
  339. u32 dev_id;
  340. u8 clk_id;
  341. u32 clk_id_32;
  342. } __packed;
  343. /**
  344. * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
  345. * @hdr: Generic Header
  346. * @parent_id: The current clock parent. If set to 255, the current parent
  347. * ID can be found from the @parent_id_32 field.
  348. * @parent_id_32: Current clock parent if @parent_id field is set to
  349. * 255.
  350. *
  351. * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
  352. */
  353. struct ti_sci_msg_resp_get_clock_parent {
  354. struct ti_sci_msg_hdr hdr;
  355. u8 parent_id;
  356. u32 parent_id_32;
  357. } __packed;
  358. /**
  359. * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
  360. * @hdr: Generic header
  361. * @dev_id: Device identifier this request is for
  362. * @clk_id: Clock identifier for the device for this request. Set to
  363. * 255 if clock ID is greater than or equal to 255.
  364. * @clk_id_32: Clock identifier if the @clk_id field contains 255.
  365. *
  366. * This request provides information about how many clock parent options
  367. * are available for a given clock to a device. This is typically used
  368. * for input clocks.
  369. *
  370. * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
  371. * message, or NACK in case of inability to satisfy request.
  372. */
  373. struct ti_sci_msg_req_get_clock_num_parents {
  374. struct ti_sci_msg_hdr hdr;
  375. u32 dev_id;
  376. u8 clk_id;
  377. u32 clk_id_32;
  378. } __packed;
  379. /**
  380. * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
  381. * @hdr: Generic header
  382. * @num_parents: Number of clock parents. If set to 255, the actual
  383. * number of parents is stored into @num_parents_32
  384. * field instead.
  385. * @num_parents_32: Number of clock parents if @num_parents field is
  386. * set to 255.
  387. *
  388. * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
  389. */
  390. struct ti_sci_msg_resp_get_clock_num_parents {
  391. struct ti_sci_msg_hdr hdr;
  392. u8 num_parents;
  393. u32 num_parents_32;
  394. } __packed;
  395. /**
  396. * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
  397. * @hdr: Generic Header
  398. * @dev_id: Device identifier this request is for
  399. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  400. * allowable programmed frequency and does not account for clock
  401. * tolerances and jitter.
  402. * @target_freq_hz: The target clock frequency. A frequency will be found
  403. * as close to this target frequency as possible.
  404. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  405. * allowable programmed frequency and does not account for clock
  406. * tolerances and jitter.
  407. * @clk_id: Clock identifier for the device for this request. Set to
  408. * 255 if clock identifier is greater than or equal to 255.
  409. * @clk_id_32: Clock identifier if @clk_id is set to 255.
  410. *
  411. * NOTE: Normally clock frequency management is automatically done by TISCI
  412. * entity. In case of specific requests, TISCI evaluates capability to achieve
  413. * requested frequency within provided range and responds with
  414. * result message.
  415. *
  416. * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
  417. * or NACK in case of inability to satisfy request.
  418. */
  419. struct ti_sci_msg_req_query_clock_freq {
  420. struct ti_sci_msg_hdr hdr;
  421. u32 dev_id;
  422. u64 min_freq_hz;
  423. u64 target_freq_hz;
  424. u64 max_freq_hz;
  425. u8 clk_id;
  426. u32 clk_id_32;
  427. } __packed;
  428. /**
  429. * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
  430. * @hdr: Generic Header
  431. * @freq_hz: Frequency that is the best match in Hz.
  432. *
  433. * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
  434. * cannot be satisfied, the message will be of type NACK.
  435. */
  436. struct ti_sci_msg_resp_query_clock_freq {
  437. struct ti_sci_msg_hdr hdr;
  438. u64 freq_hz;
  439. } __packed;
  440. /**
  441. * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
  442. * @hdr: Generic Header
  443. * @dev_id: Device identifier this request is for
  444. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  445. * allowable programmed frequency and does not account for clock
  446. * tolerances and jitter.
  447. * @target_freq_hz: The target clock frequency. The clock will be programmed
  448. * at a rate as close to this target frequency as possible.
  449. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  450. * allowable programmed frequency and does not account for clock
  451. * tolerances and jitter.
  452. * @clk_id: Clock identifier for the device for this request. Set to
  453. * 255 if clock ID is greater than or equal to 255.
  454. * @clk_id_32: Clock identifier if @clk_id field is set to 255.
  455. *
  456. * NOTE: Normally clock frequency management is automatically done by TISCI
  457. * entity. In case of specific requests, TISCI evaluates capability to achieve
  458. * requested range and responds with success/failure message.
  459. *
  460. * This sets the desired frequency for a clock within an allowable
  461. * range. This message will fail on an enabled clock unless
  462. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
  463. * if other clocks have their frequency modified due to this message,
  464. * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
  465. *
  466. * Calling set frequency on a clock input to the SoC pseudo-device will
  467. * inform the PMMC of that clock's frequency. Setting a frequency of
  468. * zero will indicate the clock is disabled.
  469. *
  470. * Calling set frequency on clock outputs from the SoC pseudo-device will
  471. * function similarly to setting the clock frequency on a device.
  472. *
  473. * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
  474. * message.
  475. */
  476. struct ti_sci_msg_req_set_clock_freq {
  477. struct ti_sci_msg_hdr hdr;
  478. u32 dev_id;
  479. u64 min_freq_hz;
  480. u64 target_freq_hz;
  481. u64 max_freq_hz;
  482. u8 clk_id;
  483. u32 clk_id_32;
  484. } __packed;
  485. /**
  486. * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
  487. * @hdr: Generic Header
  488. * @dev_id: Device identifier this request is for
  489. * @clk_id: Clock identifier for the device for this request. Set to
  490. * 255 if clock ID is greater than or equal to 255.
  491. * @clk_id_32: Clock identifier if @clk_id field is set to 255.
  492. *
  493. * NOTE: Normally clock frequency management is automatically done by TISCI
  494. * entity. In some cases, clock frequencies are configured by host.
  495. *
  496. * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
  497. * that the clock is currently at.
  498. */
  499. struct ti_sci_msg_req_get_clock_freq {
  500. struct ti_sci_msg_hdr hdr;
  501. u32 dev_id;
  502. u8 clk_id;
  503. u32 clk_id_32;
  504. } __packed;
  505. /**
  506. * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
  507. * @hdr: Generic Header
  508. * @freq_hz: Frequency that the clock is currently on, in Hz.
  509. *
  510. * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
  511. */
  512. struct ti_sci_msg_resp_get_clock_freq {
  513. struct ti_sci_msg_hdr hdr;
  514. u64 freq_hz;
  515. } __packed;
  516. #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
  517. /**
  518. * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
  519. * range of resources.
  520. * @hdr: Generic Header
  521. * @type: Unique resource assignment type
  522. * @subtype: Resource assignment subtype within the resource type.
  523. * @secondary_host: Host processing entity to which the resources are
  524. * allocated. This is required only when the destination
  525. * host id id different from ti sci interface host id,
  526. * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
  527. *
  528. * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
  529. * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
  530. */
  531. struct ti_sci_msg_req_get_resource_range {
  532. struct ti_sci_msg_hdr hdr;
  533. #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
  534. #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
  535. u16 type;
  536. u8 subtype;
  537. u8 secondary_host;
  538. } __packed;
  539. /**
  540. * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
  541. * @hdr: Generic Header
  542. * @range_start: Start index of the resource range.
  543. * @range_num: Number of resources in the range.
  544. *
  545. * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
  546. */
  547. struct ti_sci_msg_resp_get_resource_range {
  548. struct ti_sci_msg_hdr hdr;
  549. u16 range_start;
  550. u16 range_num;
  551. } __packed;
  552. /**
  553. * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
  554. * between the dev and the host.
  555. * @hdr: Generic Header
  556. * @valid_params: Bit fields defining the validity of interrupt source
  557. * parameters. If a bit is not set, then corresponding
  558. * field is not valid and will not be used for route set.
  559. * Bit field definitions:
  560. * 0 - Valid bit for @dst_id
  561. * 1 - Valid bit for @dst_host_irq
  562. * 2 - Valid bit for @ia_id
  563. * 3 - Valid bit for @vint
  564. * 4 - Valid bit for @global_event
  565. * 5 - Valid bit for @vint_status_bit_index
  566. * 31 - Valid bit for @secondary_host
  567. * @src_id: IRQ source peripheral ID.
  568. * @src_index: IRQ source index within the peripheral
  569. * @dst_id: IRQ Destination ID. Based on the architecture it can be
  570. * IRQ controller or host processor ID.
  571. * @dst_host_irq: IRQ number of the destination host IRQ controller
  572. * @ia_id: Device ID of the interrupt aggregator in which the
  573. * vint resides.
  574. * @vint: Virtual interrupt number if the interrupt route
  575. * is through an interrupt aggregator.
  576. * @global_event: Global event that is to be mapped to interrupt
  577. * aggregator virtual interrupt status bit.
  578. * @vint_status_bit: Virtual interrupt status bit if the interrupt route
  579. * utilizes an interrupt aggregator status bit.
  580. * @secondary_host: Host ID of the IRQ destination computing entity. This is
  581. * required only when destination host id is different
  582. * from ti sci interface host id.
  583. *
  584. * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.
  585. * Response is generic ACK / NACK message.
  586. */
  587. struct ti_sci_msg_req_manage_irq {
  588. struct ti_sci_msg_hdr hdr;
  589. #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)
  590. #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1)
  591. #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)
  592. #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3)
  593. #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4)
  594. #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5)
  595. #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31)
  596. u32 valid_params;
  597. u16 src_id;
  598. u16 src_index;
  599. u16 dst_id;
  600. u16 dst_host_irq;
  601. u16 ia_id;
  602. u16 vint;
  603. u16 global_event;
  604. u8 vint_status_bit;
  605. u8 secondary_host;
  606. } __packed;
  607. /**
  608. * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
  609. *
  610. * Configures the non-real-time registers of a Navigator Subsystem ring.
  611. * @hdr: Generic Header
  612. * @valid_params: Bitfield defining validity of ring configuration parameters.
  613. * The ring configuration fields are not valid, and will not be used for
  614. * ring configuration, if their corresponding valid bit is zero.
  615. * Valid bit usage:
  616. * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
  617. * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
  618. * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
  619. * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
  620. * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
  621. * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
  622. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  623. * @index: ring index to be configured.
  624. * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
  625. * RING_BA_LO register
  626. * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
  627. * RING_BA_HI register.
  628. * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
  629. * modes.
  630. * @mode: Specifies the mode the ring is to be configured.
  631. * @size: Specifies encoded ring element size. To calculate the encoded size use
  632. * the formula (log2(size_bytes) - 2), where size_bytes cannot be
  633. * greater than 256.
  634. * @order_id: Specifies the ring's bus order ID.
  635. */
  636. struct ti_sci_msg_rm_ring_cfg_req {
  637. struct ti_sci_msg_hdr hdr;
  638. u32 valid_params;
  639. u16 nav_id;
  640. u16 index;
  641. u32 addr_lo;
  642. u32 addr_hi;
  643. u32 count;
  644. u8 mode;
  645. u8 size;
  646. u8 order_id;
  647. } __packed;
  648. /**
  649. * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
  650. *
  651. * Gets the configuration of the non-real-time register fields of a ring. The
  652. * host, or a supervisor of the host, who owns the ring must be the requesting
  653. * host. The values of the non-real-time registers are returned in
  654. * @ti_sci_msg_rm_ring_get_cfg_resp.
  655. *
  656. * @hdr: Generic Header
  657. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  658. * @index: ring index.
  659. */
  660. struct ti_sci_msg_rm_ring_get_cfg_req {
  661. struct ti_sci_msg_hdr hdr;
  662. u16 nav_id;
  663. u16 index;
  664. } __packed;
  665. /**
  666. * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
  667. *
  668. * Response received by host processor after RM has handled
  669. * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
  670. * non-real-time register values.
  671. *
  672. * @hdr: Generic Header
  673. * @addr_lo: Ring 32 LSBs of base address
  674. * @addr_hi: Ring 16 MSBs of base address.
  675. * @count: Ring number of elements.
  676. * @mode: Ring mode.
  677. * @size: encoded Ring element size
  678. * @order_id: ing order ID.
  679. */
  680. struct ti_sci_msg_rm_ring_get_cfg_resp {
  681. struct ti_sci_msg_hdr hdr;
  682. u32 addr_lo;
  683. u32 addr_hi;
  684. u32 count;
  685. u8 mode;
  686. u8 size;
  687. u8 order_id;
  688. } __packed;
  689. /**
  690. * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
  691. * thread
  692. * @hdr: Generic Header
  693. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  694. * used to pair the source and destination threads.
  695. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  696. *
  697. * UDMAP transmit channels mapped to source threads will have their
  698. * TCHAN_THRD_ID register programmed with the destination thread if the pairing
  699. * is successful.
  700. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  701. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  702. * the destination thread is not greater than or equal to 0x8000.
  703. *
  704. * UDMAP receive channels mapped to destination threads will have their
  705. * RCHAN_THRD_ID register programmed with the source thread if the pairing
  706. * is successful.
  707. *
  708. * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
  709. * message.
  710. */
  711. struct ti_sci_msg_psil_pair {
  712. struct ti_sci_msg_hdr hdr;
  713. u32 nav_id;
  714. u32 src_thread;
  715. u32 dst_thread;
  716. } __packed;
  717. /**
  718. * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
  719. * destination thread
  720. * @hdr: Generic Header
  721. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  722. * used to unpair the source and destination threads.
  723. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  724. *
  725. * UDMAP transmit channels mapped to source threads will have their
  726. * TCHAN_THRD_ID register cleared if the unpairing is successful.
  727. *
  728. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  729. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  730. * the destination thread is not greater than or equal to 0x8000.
  731. *
  732. * UDMAP receive channels mapped to destination threads will have their
  733. * RCHAN_THRD_ID register cleared if the unpairing is successful.
  734. *
  735. * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
  736. * message.
  737. */
  738. struct ti_sci_msg_psil_unpair {
  739. struct ti_sci_msg_hdr hdr;
  740. u32 nav_id;
  741. u32 src_thread;
  742. u32 dst_thread;
  743. } __packed;
  744. /**
  745. * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
  746. * message
  747. * @hdr: Generic Header
  748. * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
  749. * allocated
  750. * @flow_index: UDMAP receive flow index for non-optional configuration.
  751. * @rx_ch_index: Specifies the index of the receive channel using the flow_index
  752. * @rx_einfo_present: UDMAP receive flow extended packet info present.
  753. * @rx_psinfo_present: UDMAP receive flow PS words present.
  754. * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
  755. * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
  756. * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
  757. * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
  758. * @rx_sop_offset: UDMAP receive flow start of packet offset.
  759. * @rx_dest_qnum: UDMAP receive flow destination queue number.
  760. * @rx_ps_location: UDMAP receive flow PS words location.
  761. * 0 - end of packet descriptor
  762. * 1 - Beginning of the data buffer
  763. * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
  764. * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
  765. * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
  766. * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
  767. * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
  768. * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
  769. * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
  770. * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
  771. * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
  772. * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
  773. * configured and sent.
  774. * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
  775. * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
  776. * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
  777. * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
  778. *
  779. * For detailed information on the settings, see the UDMAP section of the TRM.
  780. */
  781. struct ti_sci_msg_udmap_rx_flow_cfg {
  782. struct ti_sci_msg_hdr hdr;
  783. u32 nav_id;
  784. u32 flow_index;
  785. u32 rx_ch_index;
  786. u8 rx_einfo_present;
  787. u8 rx_psinfo_present;
  788. u8 rx_error_handling;
  789. u8 rx_desc_type;
  790. u16 rx_sop_offset;
  791. u16 rx_dest_qnum;
  792. u8 rx_ps_location;
  793. u8 rx_src_tag_hi;
  794. u8 rx_src_tag_lo;
  795. u8 rx_dest_tag_hi;
  796. u8 rx_dest_tag_lo;
  797. u8 rx_src_tag_hi_sel;
  798. u8 rx_src_tag_lo_sel;
  799. u8 rx_dest_tag_hi_sel;
  800. u8 rx_dest_tag_lo_sel;
  801. u8 rx_size_thresh_en;
  802. u16 rx_fdq0_sz0_qnum;
  803. u16 rx_fdq1_qnum;
  804. u16 rx_fdq2_qnum;
  805. u16 rx_fdq3_qnum;
  806. } __packed;
  807. /**
  808. * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
  809. * flow optional configuration
  810. * @hdr: Generic Header
  811. * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
  812. * allocated
  813. * @flow_index: UDMAP receive flow index for optional configuration.
  814. * @rx_ch_index: Specifies the index of the receive channel using the flow_index
  815. * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
  816. * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
  817. * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
  818. * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
  819. * threshold 1.
  820. * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
  821. * threshold 2.
  822. * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
  823. * threshold 3.
  824. *
  825. * For detailed information on the settings, see the UDMAP section of the TRM.
  826. */
  827. struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
  828. struct ti_sci_msg_hdr hdr;
  829. u32 nav_id;
  830. u32 flow_index;
  831. u32 rx_ch_index;
  832. u16 rx_size_thresh0;
  833. u16 rx_size_thresh1;
  834. u16 rx_size_thresh2;
  835. u16 rx_fdq0_sz1_qnum;
  836. u16 rx_fdq0_sz2_qnum;
  837. u16 rx_fdq0_sz3_qnum;
  838. } __packed;
  839. /**
  840. * Configures a Navigator Subsystem UDMAP transmit channel
  841. *
  842. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  843. * transmit channel. The channel index must be assigned to the host defined
  844. * in the TISCI header via the RM board configuration resource assignment
  845. * range list.
  846. *
  847. * @hdr: Generic Header
  848. *
  849. * @valid_params: Bitfield defining validity of tx channel configuration
  850. * parameters. The tx channel configuration fields are not valid, and will not
  851. * be used for ch configuration, if their corresponding valid bit is zero.
  852. * Valid bit usage:
  853. * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
  854. * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
  855. * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
  856. * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
  857. * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
  858. * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
  859. * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
  860. * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
  861. * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
  862. * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
  863. * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
  864. * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
  865. * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
  866. * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
  867. * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
  868. *
  869. * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
  870. *
  871. * @index: UDMAP transmit channel index.
  872. *
  873. * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
  874. * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
  875. * register.
  876. *
  877. * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
  878. * configuration to be programmed into the tx_filt_einfo field of the
  879. * channel's TCHAN_TCFG register.
  880. *
  881. * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
  882. * configuration to be programmed into the tx_filt_pswords field of the
  883. * channel's TCHAN_TCFG register.
  884. *
  885. * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
  886. * interpretation configuration to be programmed into the tx_atype field of
  887. * the channel's TCHAN_TCFG register.
  888. *
  889. * @tx_chan_type: UDMAP transmit channel functional channel type and work
  890. * passing mechanism configuration to be programmed into the tx_chan_type
  891. * field of the channel's TCHAN_TCFG register.
  892. *
  893. * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
  894. * configuration to be programmed into the tx_supr_tdpkt field of the channel's
  895. * TCHAN_TCFG register.
  896. *
  897. * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
  898. * fetch configuration to be programmed into the tx_fetch_size field of the
  899. * channel's TCHAN_TCFG register. The user must make sure to set the maximum
  900. * word count that can pass through the channel for any allowed descriptor type.
  901. *
  902. * @tx_credit_count: UDMAP transmit channel transfer request credit count
  903. * configuration to be programmed into the count field of the TCHAN_TCREDIT
  904. * register. Specifies how many credits for complete TRs are available.
  905. *
  906. * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
  907. * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
  908. * completion queue must be assigned to the host, or a subordinate of the host,
  909. * requesting configuration of the transmit channel.
  910. *
  911. * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
  912. * into the priority field of the channel's TCHAN_TPRI_CTRL register.
  913. *
  914. * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
  915. * qos field of the channel's TCHAN_TPRI_CTRL register.
  916. *
  917. * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
  918. * the orderid field of the channel's TCHAN_TPRI_CTRL register.
  919. *
  920. * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
  921. * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
  922. * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
  923. * section of the TRM for restrictions regarding this parameter.
  924. *
  925. * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
  926. * configuration to be programmed into the priority field of the channel's
  927. * TCHAN_TST_SCHED register.
  928. *
  929. * @tx_burst_size: UDMAP transmit channel burst size configuration to be
  930. * programmed into the tx_burst_size field of the TCHAN_TCFG register.
  931. */
  932. struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
  933. struct ti_sci_msg_hdr hdr;
  934. u32 valid_params;
  935. u16 nav_id;
  936. u16 index;
  937. u8 tx_pause_on_err;
  938. u8 tx_filt_einfo;
  939. u8 tx_filt_pswords;
  940. u8 tx_atype;
  941. u8 tx_chan_type;
  942. u8 tx_supr_tdpkt;
  943. u16 tx_fetch_size;
  944. u8 tx_credit_count;
  945. u16 txcq_qnum;
  946. u8 tx_priority;
  947. u8 tx_qos;
  948. u8 tx_orderid;
  949. u16 fdepth;
  950. u8 tx_sched_priority;
  951. u8 tx_burst_size;
  952. } __packed;
  953. /**
  954. * Configures a Navigator Subsystem UDMAP receive channel
  955. *
  956. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  957. * receive channel. The channel index must be assigned to the host defined
  958. * in the TISCI header via the RM board configuration resource assignment
  959. * range list.
  960. *
  961. * @hdr: Generic Header
  962. *
  963. * @valid_params: Bitfield defining validity of rx channel configuration
  964. * parameters.
  965. * The rx channel configuration fields are not valid, and will not be used for
  966. * ch configuration, if their corresponding valid bit is zero.
  967. * Valid bit usage:
  968. * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
  969. * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
  970. * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
  971. * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
  972. * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
  973. * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
  974. * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
  975. * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
  976. * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
  977. * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
  978. * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
  979. * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
  980. * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
  981. * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
  982. *
  983. * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
  984. *
  985. * @index: UDMAP receive channel index.
  986. *
  987. * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
  988. * fetch configuration to be programmed into the rx_fetch_size field of the
  989. * channel's RCHAN_RCFG register.
  990. *
  991. * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
  992. * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
  993. * The specified completion queue must be assigned to the host, or a subordinate
  994. * of the host, requesting configuration of the receive channel.
  995. *
  996. * @rx_priority: UDMAP receive channel receive priority value to be programmed
  997. * into the priority field of the channel's RCHAN_RPRI_CTRL register.
  998. *
  999. * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
  1000. * qos field of the channel's RCHAN_RPRI_CTRL register.
  1001. *
  1002. * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
  1003. * the orderid field of the channel's RCHAN_RPRI_CTRL register.
  1004. *
  1005. * @rx_sched_priority: UDMAP receive channel rx scheduling priority
  1006. * configuration to be programmed into the priority field of the channel's
  1007. * RCHAN_RST_SCHED register.
  1008. *
  1009. * @flowid_start: UDMAP receive channel additional flows starting index
  1010. * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
  1011. * register. Specifies the starting index for flow IDs the receive channel is to
  1012. * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
  1013. * set as valid and configured together. The starting flow ID set by
  1014. * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
  1015. * of flows beyond the default flows statically mapped to receive channels.
  1016. * The additional flows must be assigned to the host, or a subordinate of the
  1017. * host, requesting configuration of the receive channel.
  1018. *
  1019. * @flowid_cnt: UDMAP receive channel additional flows count configuration to
  1020. * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
  1021. * This field specifies how many flow IDs are in the additional contiguous range
  1022. * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
  1023. * set as valid and configured together. Disabling the valid_params field bit
  1024. * for flowid_cnt indicates no flow IDs other than the default are to be
  1025. * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
  1026. * cannot be greater than the number of receive flows in the receive channel's
  1027. * Navigator Subsystem. The additional flows must be assigned to the host, or a
  1028. * subordinate of the host, requesting configuration of the receive channel.
  1029. *
  1030. * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
  1031. * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
  1032. * register.
  1033. *
  1034. * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
  1035. * interpretation configuration to be programmed into the rx_atype field of the
  1036. * channel's RCHAN_RCFG register.
  1037. *
  1038. * @rx_chan_type: UDMAP receive channel functional channel type and work passing
  1039. * mechanism configuration to be programmed into the rx_chan_type field of the
  1040. * channel's RCHAN_RCFG register.
  1041. *
  1042. * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
  1043. * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
  1044. *
  1045. * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
  1046. * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
  1047. *
  1048. * @rx_burst_size: UDMAP receive channel burst size configuration to be
  1049. * programmed into the rx_burst_size field of the RCHAN_RCFG register.
  1050. */
  1051. struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
  1052. struct ti_sci_msg_hdr hdr;
  1053. u32 valid_params;
  1054. u16 nav_id;
  1055. u16 index;
  1056. u16 rx_fetch_size;
  1057. u16 rxcq_qnum;
  1058. u8 rx_priority;
  1059. u8 rx_qos;
  1060. u8 rx_orderid;
  1061. u8 rx_sched_priority;
  1062. u16 flowid_start;
  1063. u16 flowid_cnt;
  1064. u8 rx_pause_on_err;
  1065. u8 rx_atype;
  1066. u8 rx_chan_type;
  1067. u8 rx_ignore_short;
  1068. u8 rx_ignore_long;
  1069. u8 rx_burst_size;
  1070. } __packed;
  1071. /**
  1072. * Configures a Navigator Subsystem UDMAP receive flow
  1073. *
  1074. * Configures a Navigator Subsystem UDMAP receive flow's registers.
  1075. * Configuration does not include the flow registers which handle size-based
  1076. * free descriptor queue routing.
  1077. *
  1078. * The flow index must be assigned to the host defined in the TISCI header via
  1079. * the RM board configuration resource assignment range list.
  1080. *
  1081. * @hdr: Standard TISCI header
  1082. *
  1083. * @valid_params
  1084. * Bitfield defining validity of rx flow configuration parameters. The
  1085. * rx flow configuration fields are not valid, and will not be used for flow
  1086. * configuration, if their corresponding valid bit is zero. Valid bit usage:
  1087. * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
  1088. * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
  1089. * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
  1090. * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
  1091. * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
  1092. * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
  1093. * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
  1094. * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
  1095. * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
  1096. * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
  1097. * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
  1098. * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
  1099. * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
  1100. * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
  1101. * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
  1102. * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
  1103. * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
  1104. * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
  1105. * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
  1106. *
  1107. * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
  1108. * allocated
  1109. *
  1110. * @flow_index: UDMAP receive flow index for non-optional configuration.
  1111. *
  1112. * @rx_einfo_present:
  1113. * UDMAP receive flow extended packet info present configuration to be
  1114. * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
  1115. *
  1116. * @rx_psinfo_present:
  1117. * UDMAP receive flow PS words present configuration to be programmed into the
  1118. * rx_psinfo_present field of the flow's RFLOW_RFA register.
  1119. *
  1120. * @rx_error_handling:
  1121. * UDMAP receive flow error handling configuration to be programmed into the
  1122. * rx_error_handling field of the flow's RFLOW_RFA register.
  1123. *
  1124. * @rx_desc_type:
  1125. * UDMAP receive flow descriptor type configuration to be programmed into the
  1126. * rx_desc_type field field of the flow's RFLOW_RFA register.
  1127. *
  1128. * @rx_sop_offset:
  1129. * UDMAP receive flow start of packet offset configuration to be programmed
  1130. * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
  1131. * section of the TRM for more information on this setting. Valid values for
  1132. * this field are 0-255 bytes.
  1133. *
  1134. * @rx_dest_qnum:
  1135. * UDMAP receive flow destination queue configuration to be programmed into the
  1136. * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
  1137. * destination queue must be valid within the Navigator Subsystem and must be
  1138. * owned by the host, or a subordinate of the host, requesting allocation and
  1139. * configuration of the receive flow.
  1140. *
  1141. * @rx_src_tag_hi:
  1142. * UDMAP receive flow source tag high byte constant configuration to be
  1143. * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
  1144. * See the UDMAP section of the TRM for more information on this setting.
  1145. *
  1146. * @rx_src_tag_lo:
  1147. * UDMAP receive flow source tag low byte constant configuration to be
  1148. * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
  1149. * See the UDMAP section of the TRM for more information on this setting.
  1150. *
  1151. * @rx_dest_tag_hi:
  1152. * UDMAP receive flow destination tag high byte constant configuration to be
  1153. * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
  1154. * See the UDMAP section of the TRM for more information on this setting.
  1155. *
  1156. * @rx_dest_tag_lo:
  1157. * UDMAP receive flow destination tag low byte constant configuration to be
  1158. * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
  1159. * See the UDMAP section of the TRM for more information on this setting.
  1160. *
  1161. * @rx_src_tag_hi_sel:
  1162. * UDMAP receive flow source tag high byte selector configuration to be
  1163. * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
  1164. * the UDMAP section of the TRM for more information on this setting.
  1165. *
  1166. * @rx_src_tag_lo_sel:
  1167. * UDMAP receive flow source tag low byte selector configuration to be
  1168. * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
  1169. * the UDMAP section of the TRM for more information on this setting.
  1170. *
  1171. * @rx_dest_tag_hi_sel:
  1172. * UDMAP receive flow destination tag high byte selector configuration to be
  1173. * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
  1174. * the UDMAP section of the TRM for more information on this setting.
  1175. *
  1176. * @rx_dest_tag_lo_sel:
  1177. * UDMAP receive flow destination tag low byte selector configuration to be
  1178. * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
  1179. * the UDMAP section of the TRM for more information on this setting.
  1180. *
  1181. * @rx_fdq0_sz0_qnum:
  1182. * UDMAP receive flow free descriptor queue 0 configuration to be programmed
  1183. * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
  1184. * UDMAP section of the TRM for more information on this setting. The specified
  1185. * free queue must be valid within the Navigator Subsystem and must be owned
  1186. * by the host, or a subordinate of the host, requesting allocation and
  1187. * configuration of the receive flow.
  1188. *
  1189. * @rx_fdq1_qnum:
  1190. * UDMAP receive flow free descriptor queue 1 configuration to be programmed
  1191. * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
  1192. * UDMAP section of the TRM for more information on this setting. The specified
  1193. * free queue must be valid within the Navigator Subsystem and must be owned
  1194. * by the host, or a subordinate of the host, requesting allocation and
  1195. * configuration of the receive flow.
  1196. *
  1197. * @rx_fdq2_qnum:
  1198. * UDMAP receive flow free descriptor queue 2 configuration to be programmed
  1199. * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
  1200. * UDMAP section of the TRM for more information on this setting. The specified
  1201. * free queue must be valid within the Navigator Subsystem and must be owned
  1202. * by the host, or a subordinate of the host, requesting allocation and
  1203. * configuration of the receive flow.
  1204. *
  1205. * @rx_fdq3_qnum:
  1206. * UDMAP receive flow free descriptor queue 3 configuration to be programmed
  1207. * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
  1208. * UDMAP section of the TRM for more information on this setting. The specified
  1209. * free queue must be valid within the Navigator Subsystem and must be owned
  1210. * by the host, or a subordinate of the host, requesting allocation and
  1211. * configuration of the receive flow.
  1212. *
  1213. * @rx_ps_location:
  1214. * UDMAP receive flow PS words location configuration to be programmed into the
  1215. * rx_ps_location field of the flow's RFLOW_RFA register.
  1216. */
  1217. struct ti_sci_msg_rm_udmap_flow_cfg_req {
  1218. struct ti_sci_msg_hdr hdr;
  1219. u32 valid_params;
  1220. u16 nav_id;
  1221. u16 flow_index;
  1222. u8 rx_einfo_present;
  1223. u8 rx_psinfo_present;
  1224. u8 rx_error_handling;
  1225. u8 rx_desc_type;
  1226. u16 rx_sop_offset;
  1227. u16 rx_dest_qnum;
  1228. u8 rx_src_tag_hi;
  1229. u8 rx_src_tag_lo;
  1230. u8 rx_dest_tag_hi;
  1231. u8 rx_dest_tag_lo;
  1232. u8 rx_src_tag_hi_sel;
  1233. u8 rx_src_tag_lo_sel;
  1234. u8 rx_dest_tag_hi_sel;
  1235. u8 rx_dest_tag_lo_sel;
  1236. u16 rx_fdq0_sz0_qnum;
  1237. u16 rx_fdq1_qnum;
  1238. u16 rx_fdq2_qnum;
  1239. u16 rx_fdq3_qnum;
  1240. u8 rx_ps_location;
  1241. } __packed;
  1242. /**
  1243. * struct ti_sci_msg_req_proc_request - Request a processor
  1244. * @hdr: Generic Header
  1245. * @processor_id: ID of processor being requested
  1246. *
  1247. * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
  1248. * message.
  1249. */
  1250. struct ti_sci_msg_req_proc_request {
  1251. struct ti_sci_msg_hdr hdr;
  1252. u8 processor_id;
  1253. } __packed;
  1254. /**
  1255. * struct ti_sci_msg_req_proc_release - Release a processor
  1256. * @hdr: Generic Header
  1257. * @processor_id: ID of processor being released
  1258. *
  1259. * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
  1260. * message.
  1261. */
  1262. struct ti_sci_msg_req_proc_release {
  1263. struct ti_sci_msg_hdr hdr;
  1264. u8 processor_id;
  1265. } __packed;
  1266. /**
  1267. * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
  1268. * @hdr: Generic Header
  1269. * @processor_id: ID of processor being handed over
  1270. * @host_id: Host ID the control needs to be transferred to
  1271. *
  1272. * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
  1273. * message.
  1274. */
  1275. struct ti_sci_msg_req_proc_handover {
  1276. struct ti_sci_msg_hdr hdr;
  1277. u8 processor_id;
  1278. u8 host_id;
  1279. } __packed;
  1280. /* Boot Vector masks */
  1281. #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
  1282. #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
  1283. #define TI_SCI_ADDR_HIGH_SHIFT 32
  1284. /**
  1285. * struct ti_sci_msg_req_set_config - Set Processor boot configuration
  1286. * @hdr: Generic Header
  1287. * @processor_id: ID of processor being configured
  1288. * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
  1289. * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
  1290. * @config_flags_set: Optional Processor specific Config Flags to set.
  1291. * Setting a bit here implies the corresponding mode
  1292. * will be set
  1293. * @config_flags_clear: Optional Processor specific Config Flags to clear.
  1294. * Setting a bit here implies the corresponding mode
  1295. * will be cleared
  1296. *
  1297. * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
  1298. * message.
  1299. */
  1300. struct ti_sci_msg_req_set_config {
  1301. struct ti_sci_msg_hdr hdr;
  1302. u8 processor_id;
  1303. u32 bootvector_low;
  1304. u32 bootvector_high;
  1305. u32 config_flags_set;
  1306. u32 config_flags_clear;
  1307. } __packed;
  1308. /**
  1309. * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
  1310. * @hdr: Generic Header
  1311. * @processor_id: ID of processor being configured
  1312. * @control_flags_set: Optional Processor specific Control Flags to set.
  1313. * Setting a bit here implies the corresponding mode
  1314. * will be set
  1315. * @control_flags_clear:Optional Processor specific Control Flags to clear.
  1316. * Setting a bit here implies the corresponding mode
  1317. * will be cleared
  1318. *
  1319. * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
  1320. * message.
  1321. */
  1322. struct ti_sci_msg_req_set_ctrl {
  1323. struct ti_sci_msg_hdr hdr;
  1324. u8 processor_id;
  1325. u32 control_flags_set;
  1326. u32 control_flags_clear;
  1327. } __packed;
  1328. /**
  1329. * struct ti_sci_msg_req_get_status - Processor boot status request
  1330. * @hdr: Generic Header
  1331. * @processor_id: ID of processor whose status is being requested
  1332. *
  1333. * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate
  1334. * message, or NACK in case of inability to satisfy request.
  1335. */
  1336. struct ti_sci_msg_req_get_status {
  1337. struct ti_sci_msg_hdr hdr;
  1338. u8 processor_id;
  1339. } __packed;
  1340. /**
  1341. * struct ti_sci_msg_resp_get_status - Processor boot status response
  1342. * @hdr: Generic Header
  1343. * @processor_id: ID of processor whose status is returned
  1344. * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
  1345. * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
  1346. * @config_flags: Optional Processor specific Config Flags set currently
  1347. * @control_flags: Optional Processor specific Control Flags set currently
  1348. * @status_flags: Optional Processor specific Status Flags set currently
  1349. *
  1350. * Response structure to a TI_SCI_MSG_GET_STATUS request.
  1351. */
  1352. struct ti_sci_msg_resp_get_status {
  1353. struct ti_sci_msg_hdr hdr;
  1354. u8 processor_id;
  1355. u32 bootvector_low;
  1356. u32 bootvector_high;
  1357. u32 config_flags;
  1358. u32 control_flags;
  1359. u32 status_flags;
  1360. } __packed;
  1361. #endif /* __TI_SCI_H */