qcom_scm.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2015 Linaro Ltd.
  4. */
  5. #include <linux/platform_device.h>
  6. #include <linux/init.h>
  7. #include <linux/cpumask.h>
  8. #include <linux/export.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/module.h>
  11. #include <linux/types.h>
  12. #include <linux/qcom_scm.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/clk.h>
  17. #include <linux/reset-controller.h>
  18. #include <linux/arm-smccc.h>
  19. #include "qcom_scm.h"
  20. static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
  21. module_param(download_mode, bool, 0);
  22. #define SCM_HAS_CORE_CLK BIT(0)
  23. #define SCM_HAS_IFACE_CLK BIT(1)
  24. #define SCM_HAS_BUS_CLK BIT(2)
  25. struct qcom_scm {
  26. struct device *dev;
  27. struct clk *core_clk;
  28. struct clk *iface_clk;
  29. struct clk *bus_clk;
  30. struct reset_controller_dev reset;
  31. u64 dload_mode_addr;
  32. };
  33. struct qcom_scm_current_perm_info {
  34. __le32 vmid;
  35. __le32 perm;
  36. __le64 ctx;
  37. __le32 ctx_size;
  38. __le32 unused;
  39. };
  40. struct qcom_scm_mem_map_info {
  41. __le64 mem_addr;
  42. __le64 mem_size;
  43. };
  44. #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
  45. #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
  46. #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
  47. #define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
  48. #define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
  49. #define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
  50. #define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
  51. #define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
  52. struct qcom_scm_wb_entry {
  53. int flag;
  54. void *entry;
  55. };
  56. static struct qcom_scm_wb_entry qcom_scm_wb[] = {
  57. { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
  58. { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
  59. { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
  60. { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
  61. };
  62. static const char *qcom_scm_convention_names[] = {
  63. [SMC_CONVENTION_UNKNOWN] = "unknown",
  64. [SMC_CONVENTION_ARM_32] = "smc arm 32",
  65. [SMC_CONVENTION_ARM_64] = "smc arm 64",
  66. [SMC_CONVENTION_LEGACY] = "smc legacy",
  67. };
  68. static struct qcom_scm *__scm;
  69. static int qcom_scm_clk_enable(void)
  70. {
  71. int ret;
  72. ret = clk_prepare_enable(__scm->core_clk);
  73. if (ret)
  74. goto bail;
  75. ret = clk_prepare_enable(__scm->iface_clk);
  76. if (ret)
  77. goto disable_core;
  78. ret = clk_prepare_enable(__scm->bus_clk);
  79. if (ret)
  80. goto disable_iface;
  81. return 0;
  82. disable_iface:
  83. clk_disable_unprepare(__scm->iface_clk);
  84. disable_core:
  85. clk_disable_unprepare(__scm->core_clk);
  86. bail:
  87. return ret;
  88. }
  89. static void qcom_scm_clk_disable(void)
  90. {
  91. clk_disable_unprepare(__scm->core_clk);
  92. clk_disable_unprepare(__scm->iface_clk);
  93. clk_disable_unprepare(__scm->bus_clk);
  94. }
  95. enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN;
  96. static DEFINE_SPINLOCK(scm_query_lock);
  97. static enum qcom_scm_convention __get_convention(void)
  98. {
  99. unsigned long flags;
  100. struct qcom_scm_desc desc = {
  101. .svc = QCOM_SCM_SVC_INFO,
  102. .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
  103. .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
  104. QCOM_SCM_INFO_IS_CALL_AVAIL) |
  105. (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
  106. .arginfo = QCOM_SCM_ARGS(1),
  107. .owner = ARM_SMCCC_OWNER_SIP,
  108. };
  109. struct qcom_scm_res res;
  110. enum qcom_scm_convention probed_convention;
  111. int ret;
  112. bool forced = false;
  113. if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN))
  114. return qcom_scm_convention;
  115. /*
  116. * Device isn't required as there is only one argument - no device
  117. * needed to dma_map_single to secure world
  118. */
  119. probed_convention = SMC_CONVENTION_ARM_64;
  120. ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true);
  121. if (!ret && res.result[0] == 1)
  122. goto found;
  123. /*
  124. * Some SC7180 firmwares didn't implement the
  125. * QCOM_SCM_INFO_IS_CALL_AVAIL call, so we fallback to forcing ARM_64
  126. * calling conventions on these firmwares. Luckily we don't make any
  127. * early calls into the firmware on these SoCs so the device pointer
  128. * will be valid here to check if the compatible matches.
  129. */
  130. if (of_device_is_compatible(__scm ? __scm->dev->of_node : NULL, "qcom,scm-sc7180")) {
  131. forced = true;
  132. goto found;
  133. }
  134. probed_convention = SMC_CONVENTION_ARM_32;
  135. ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true);
  136. if (!ret && res.result[0] == 1)
  137. goto found;
  138. probed_convention = SMC_CONVENTION_LEGACY;
  139. found:
  140. spin_lock_irqsave(&scm_query_lock, flags);
  141. if (probed_convention != qcom_scm_convention) {
  142. qcom_scm_convention = probed_convention;
  143. pr_info("qcom_scm: convention: %s%s\n",
  144. qcom_scm_convention_names[qcom_scm_convention],
  145. forced ? " (forced)" : "");
  146. }
  147. spin_unlock_irqrestore(&scm_query_lock, flags);
  148. return qcom_scm_convention;
  149. }
  150. /**
  151. * qcom_scm_call() - Invoke a syscall in the secure world
  152. * @dev: device
  153. * @svc_id: service identifier
  154. * @cmd_id: command identifier
  155. * @desc: Descriptor structure containing arguments and return values
  156. *
  157. * Sends a command to the SCM and waits for the command to finish processing.
  158. * This should *only* be called in pre-emptible context.
  159. */
  160. static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
  161. struct qcom_scm_res *res)
  162. {
  163. might_sleep();
  164. switch (__get_convention()) {
  165. case SMC_CONVENTION_ARM_32:
  166. case SMC_CONVENTION_ARM_64:
  167. return scm_smc_call(dev, desc, res, false);
  168. case SMC_CONVENTION_LEGACY:
  169. return scm_legacy_call(dev, desc, res);
  170. default:
  171. pr_err("Unknown current SCM calling convention.\n");
  172. return -EINVAL;
  173. }
  174. }
  175. /**
  176. * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
  177. * @dev: device
  178. * @svc_id: service identifier
  179. * @cmd_id: command identifier
  180. * @desc: Descriptor structure containing arguments and return values
  181. * @res: Structure containing results from SMC/HVC call
  182. *
  183. * Sends a command to the SCM and waits for the command to finish processing.
  184. * This can be called in atomic context.
  185. */
  186. static int qcom_scm_call_atomic(struct device *dev,
  187. const struct qcom_scm_desc *desc,
  188. struct qcom_scm_res *res)
  189. {
  190. switch (__get_convention()) {
  191. case SMC_CONVENTION_ARM_32:
  192. case SMC_CONVENTION_ARM_64:
  193. return scm_smc_call(dev, desc, res, true);
  194. case SMC_CONVENTION_LEGACY:
  195. return scm_legacy_call_atomic(dev, desc, res);
  196. default:
  197. pr_err("Unknown current SCM calling convention.\n");
  198. return -EINVAL;
  199. }
  200. }
  201. static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
  202. u32 cmd_id)
  203. {
  204. int ret;
  205. struct qcom_scm_desc desc = {
  206. .svc = QCOM_SCM_SVC_INFO,
  207. .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
  208. .owner = ARM_SMCCC_OWNER_SIP,
  209. };
  210. struct qcom_scm_res res;
  211. desc.arginfo = QCOM_SCM_ARGS(1);
  212. switch (__get_convention()) {
  213. case SMC_CONVENTION_ARM_32:
  214. case SMC_CONVENTION_ARM_64:
  215. desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
  216. (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
  217. break;
  218. case SMC_CONVENTION_LEGACY:
  219. desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
  220. break;
  221. default:
  222. pr_err("Unknown SMC convention being used\n");
  223. return false;
  224. }
  225. ret = qcom_scm_call(dev, &desc, &res);
  226. return ret ? false : !!res.result[0];
  227. }
  228. /**
  229. * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
  230. * @entry: Entry point function for the cpus
  231. * @cpus: The cpumask of cpus that will use the entry point
  232. *
  233. * Set the Linux entry point for the SCM to transfer control to when coming
  234. * out of a power down. CPU power down may be executed on cpuidle or hotplug.
  235. */
  236. int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
  237. {
  238. int ret;
  239. int flags = 0;
  240. int cpu;
  241. struct qcom_scm_desc desc = {
  242. .svc = QCOM_SCM_SVC_BOOT,
  243. .cmd = QCOM_SCM_BOOT_SET_ADDR,
  244. .arginfo = QCOM_SCM_ARGS(2),
  245. };
  246. /*
  247. * Reassign only if we are switching from hotplug entry point
  248. * to cpuidle entry point or vice versa.
  249. */
  250. for_each_cpu(cpu, cpus) {
  251. if (entry == qcom_scm_wb[cpu].entry)
  252. continue;
  253. flags |= qcom_scm_wb[cpu].flag;
  254. }
  255. /* No change in entry function */
  256. if (!flags)
  257. return 0;
  258. desc.args[0] = flags;
  259. desc.args[1] = virt_to_phys(entry);
  260. ret = qcom_scm_call(__scm->dev, &desc, NULL);
  261. if (!ret) {
  262. for_each_cpu(cpu, cpus)
  263. qcom_scm_wb[cpu].entry = entry;
  264. }
  265. return ret;
  266. }
  267. EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
  268. /**
  269. * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
  270. * @entry: Entry point function for the cpus
  271. * @cpus: The cpumask of cpus that will use the entry point
  272. *
  273. * Set the cold boot address of the cpus. Any cpu outside the supported
  274. * range would be removed from the cpu present mask.
  275. */
  276. int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
  277. {
  278. int flags = 0;
  279. int cpu;
  280. int scm_cb_flags[] = {
  281. QCOM_SCM_FLAG_COLDBOOT_CPU0,
  282. QCOM_SCM_FLAG_COLDBOOT_CPU1,
  283. QCOM_SCM_FLAG_COLDBOOT_CPU2,
  284. QCOM_SCM_FLAG_COLDBOOT_CPU3,
  285. };
  286. struct qcom_scm_desc desc = {
  287. .svc = QCOM_SCM_SVC_BOOT,
  288. .cmd = QCOM_SCM_BOOT_SET_ADDR,
  289. .arginfo = QCOM_SCM_ARGS(2),
  290. .owner = ARM_SMCCC_OWNER_SIP,
  291. };
  292. if (!cpus || (cpus && cpumask_empty(cpus)))
  293. return -EINVAL;
  294. for_each_cpu(cpu, cpus) {
  295. if (cpu < ARRAY_SIZE(scm_cb_flags))
  296. flags |= scm_cb_flags[cpu];
  297. else
  298. set_cpu_present(cpu, false);
  299. }
  300. desc.args[0] = flags;
  301. desc.args[1] = virt_to_phys(entry);
  302. return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
  303. }
  304. EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
  305. /**
  306. * qcom_scm_cpu_power_down() - Power down the cpu
  307. * @flags - Flags to flush cache
  308. *
  309. * This is an end point to power down cpu. If there was a pending interrupt,
  310. * the control would return from this function, otherwise, the cpu jumps to the
  311. * warm boot entry point set for this cpu upon reset.
  312. */
  313. void qcom_scm_cpu_power_down(u32 flags)
  314. {
  315. struct qcom_scm_desc desc = {
  316. .svc = QCOM_SCM_SVC_BOOT,
  317. .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
  318. .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
  319. .arginfo = QCOM_SCM_ARGS(1),
  320. .owner = ARM_SMCCC_OWNER_SIP,
  321. };
  322. qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
  323. }
  324. EXPORT_SYMBOL(qcom_scm_cpu_power_down);
  325. int qcom_scm_set_remote_state(u32 state, u32 id)
  326. {
  327. struct qcom_scm_desc desc = {
  328. .svc = QCOM_SCM_SVC_BOOT,
  329. .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
  330. .arginfo = QCOM_SCM_ARGS(2),
  331. .args[0] = state,
  332. .args[1] = id,
  333. .owner = ARM_SMCCC_OWNER_SIP,
  334. };
  335. struct qcom_scm_res res;
  336. int ret;
  337. ret = qcom_scm_call(__scm->dev, &desc, &res);
  338. return ret ? : res.result[0];
  339. }
  340. EXPORT_SYMBOL(qcom_scm_set_remote_state);
  341. static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
  342. {
  343. struct qcom_scm_desc desc = {
  344. .svc = QCOM_SCM_SVC_BOOT,
  345. .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
  346. .arginfo = QCOM_SCM_ARGS(2),
  347. .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
  348. .owner = ARM_SMCCC_OWNER_SIP,
  349. };
  350. desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
  351. return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
  352. }
  353. static void qcom_scm_set_download_mode(bool enable)
  354. {
  355. bool avail;
  356. int ret = 0;
  357. avail = __qcom_scm_is_call_available(__scm->dev,
  358. QCOM_SCM_SVC_BOOT,
  359. QCOM_SCM_BOOT_SET_DLOAD_MODE);
  360. if (avail) {
  361. ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
  362. } else if (__scm->dload_mode_addr) {
  363. ret = qcom_scm_io_writel(__scm->dload_mode_addr,
  364. enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
  365. } else {
  366. dev_err(__scm->dev,
  367. "No available mechanism for setting download mode\n");
  368. }
  369. if (ret)
  370. dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
  371. }
  372. /**
  373. * qcom_scm_pas_init_image() - Initialize peripheral authentication service
  374. * state machine for a given peripheral, using the
  375. * metadata
  376. * @peripheral: peripheral id
  377. * @metadata: pointer to memory containing ELF header, program header table
  378. * and optional blob of data used for authenticating the metadata
  379. * and the rest of the firmware
  380. * @size: size of the metadata
  381. *
  382. * Returns 0 on success.
  383. */
  384. int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
  385. {
  386. dma_addr_t mdata_phys;
  387. void *mdata_buf;
  388. int ret;
  389. struct qcom_scm_desc desc = {
  390. .svc = QCOM_SCM_SVC_PIL,
  391. .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
  392. .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
  393. .args[0] = peripheral,
  394. .owner = ARM_SMCCC_OWNER_SIP,
  395. };
  396. struct qcom_scm_res res;
  397. /*
  398. * During the scm call memory protection will be enabled for the meta
  399. * data blob, so make sure it's physically contiguous, 4K aligned and
  400. * non-cachable to avoid XPU violations.
  401. */
  402. mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
  403. GFP_KERNEL);
  404. if (!mdata_buf) {
  405. dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
  406. return -ENOMEM;
  407. }
  408. memcpy(mdata_buf, metadata, size);
  409. ret = qcom_scm_clk_enable();
  410. if (ret)
  411. goto free_metadata;
  412. desc.args[1] = mdata_phys;
  413. ret = qcom_scm_call(__scm->dev, &desc, &res);
  414. qcom_scm_clk_disable();
  415. free_metadata:
  416. dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
  417. return ret ? : res.result[0];
  418. }
  419. EXPORT_SYMBOL(qcom_scm_pas_init_image);
  420. /**
  421. * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
  422. * for firmware loading
  423. * @peripheral: peripheral id
  424. * @addr: start address of memory area to prepare
  425. * @size: size of the memory area to prepare
  426. *
  427. * Returns 0 on success.
  428. */
  429. int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
  430. {
  431. int ret;
  432. struct qcom_scm_desc desc = {
  433. .svc = QCOM_SCM_SVC_PIL,
  434. .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
  435. .arginfo = QCOM_SCM_ARGS(3),
  436. .args[0] = peripheral,
  437. .args[1] = addr,
  438. .args[2] = size,
  439. .owner = ARM_SMCCC_OWNER_SIP,
  440. };
  441. struct qcom_scm_res res;
  442. ret = qcom_scm_clk_enable();
  443. if (ret)
  444. return ret;
  445. ret = qcom_scm_call(__scm->dev, &desc, &res);
  446. qcom_scm_clk_disable();
  447. return ret ? : res.result[0];
  448. }
  449. EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
  450. /**
  451. * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
  452. * and reset the remote processor
  453. * @peripheral: peripheral id
  454. *
  455. * Return 0 on success.
  456. */
  457. int qcom_scm_pas_auth_and_reset(u32 peripheral)
  458. {
  459. int ret;
  460. struct qcom_scm_desc desc = {
  461. .svc = QCOM_SCM_SVC_PIL,
  462. .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
  463. .arginfo = QCOM_SCM_ARGS(1),
  464. .args[0] = peripheral,
  465. .owner = ARM_SMCCC_OWNER_SIP,
  466. };
  467. struct qcom_scm_res res;
  468. ret = qcom_scm_clk_enable();
  469. if (ret)
  470. return ret;
  471. ret = qcom_scm_call(__scm->dev, &desc, &res);
  472. qcom_scm_clk_disable();
  473. return ret ? : res.result[0];
  474. }
  475. EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
  476. /**
  477. * qcom_scm_pas_shutdown() - Shut down the remote processor
  478. * @peripheral: peripheral id
  479. *
  480. * Returns 0 on success.
  481. */
  482. int qcom_scm_pas_shutdown(u32 peripheral)
  483. {
  484. int ret;
  485. struct qcom_scm_desc desc = {
  486. .svc = QCOM_SCM_SVC_PIL,
  487. .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
  488. .arginfo = QCOM_SCM_ARGS(1),
  489. .args[0] = peripheral,
  490. .owner = ARM_SMCCC_OWNER_SIP,
  491. };
  492. struct qcom_scm_res res;
  493. ret = qcom_scm_clk_enable();
  494. if (ret)
  495. return ret;
  496. ret = qcom_scm_call(__scm->dev, &desc, &res);
  497. qcom_scm_clk_disable();
  498. return ret ? : res.result[0];
  499. }
  500. EXPORT_SYMBOL(qcom_scm_pas_shutdown);
  501. /**
  502. * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  503. * available for the given peripherial
  504. * @peripheral: peripheral id
  505. *
  506. * Returns true if PAS is supported for this peripheral, otherwise false.
  507. */
  508. bool qcom_scm_pas_supported(u32 peripheral)
  509. {
  510. int ret;
  511. struct qcom_scm_desc desc = {
  512. .svc = QCOM_SCM_SVC_PIL,
  513. .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
  514. .arginfo = QCOM_SCM_ARGS(1),
  515. .args[0] = peripheral,
  516. .owner = ARM_SMCCC_OWNER_SIP,
  517. };
  518. struct qcom_scm_res res;
  519. if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
  520. QCOM_SCM_PIL_PAS_IS_SUPPORTED))
  521. return false;
  522. ret = qcom_scm_call(__scm->dev, &desc, &res);
  523. return ret ? false : !!res.result[0];
  524. }
  525. EXPORT_SYMBOL(qcom_scm_pas_supported);
  526. static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
  527. {
  528. struct qcom_scm_desc desc = {
  529. .svc = QCOM_SCM_SVC_PIL,
  530. .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
  531. .arginfo = QCOM_SCM_ARGS(2),
  532. .args[0] = reset,
  533. .args[1] = 0,
  534. .owner = ARM_SMCCC_OWNER_SIP,
  535. };
  536. struct qcom_scm_res res;
  537. int ret;
  538. ret = qcom_scm_call(__scm->dev, &desc, &res);
  539. return ret ? : res.result[0];
  540. }
  541. static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
  542. unsigned long idx)
  543. {
  544. if (idx != 0)
  545. return -EINVAL;
  546. return __qcom_scm_pas_mss_reset(__scm->dev, 1);
  547. }
  548. static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
  549. unsigned long idx)
  550. {
  551. if (idx != 0)
  552. return -EINVAL;
  553. return __qcom_scm_pas_mss_reset(__scm->dev, 0);
  554. }
  555. static const struct reset_control_ops qcom_scm_pas_reset_ops = {
  556. .assert = qcom_scm_pas_reset_assert,
  557. .deassert = qcom_scm_pas_reset_deassert,
  558. };
  559. int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
  560. {
  561. struct qcom_scm_desc desc = {
  562. .svc = QCOM_SCM_SVC_IO,
  563. .cmd = QCOM_SCM_IO_READ,
  564. .arginfo = QCOM_SCM_ARGS(1),
  565. .args[0] = addr,
  566. .owner = ARM_SMCCC_OWNER_SIP,
  567. };
  568. struct qcom_scm_res res;
  569. int ret;
  570. ret = qcom_scm_call_atomic(__scm->dev, &desc, &res);
  571. if (ret >= 0)
  572. *val = res.result[0];
  573. return ret < 0 ? ret : 0;
  574. }
  575. EXPORT_SYMBOL(qcom_scm_io_readl);
  576. int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
  577. {
  578. struct qcom_scm_desc desc = {
  579. .svc = QCOM_SCM_SVC_IO,
  580. .cmd = QCOM_SCM_IO_WRITE,
  581. .arginfo = QCOM_SCM_ARGS(2),
  582. .args[0] = addr,
  583. .args[1] = val,
  584. .owner = ARM_SMCCC_OWNER_SIP,
  585. };
  586. return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
  587. }
  588. EXPORT_SYMBOL(qcom_scm_io_writel);
  589. /**
  590. * qcom_scm_restore_sec_cfg_available() - Check if secure environment
  591. * supports restore security config interface.
  592. *
  593. * Return true if restore-cfg interface is supported, false if not.
  594. */
  595. bool qcom_scm_restore_sec_cfg_available(void)
  596. {
  597. return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
  598. QCOM_SCM_MP_RESTORE_SEC_CFG);
  599. }
  600. EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
  601. int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
  602. {
  603. struct qcom_scm_desc desc = {
  604. .svc = QCOM_SCM_SVC_MP,
  605. .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
  606. .arginfo = QCOM_SCM_ARGS(2),
  607. .args[0] = device_id,
  608. .args[1] = spare,
  609. .owner = ARM_SMCCC_OWNER_SIP,
  610. };
  611. struct qcom_scm_res res;
  612. int ret;
  613. ret = qcom_scm_call(__scm->dev, &desc, &res);
  614. return ret ? : res.result[0];
  615. }
  616. EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
  617. int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
  618. {
  619. struct qcom_scm_desc desc = {
  620. .svc = QCOM_SCM_SVC_MP,
  621. .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
  622. .arginfo = QCOM_SCM_ARGS(1),
  623. .args[0] = spare,
  624. .owner = ARM_SMCCC_OWNER_SIP,
  625. };
  626. struct qcom_scm_res res;
  627. int ret;
  628. ret = qcom_scm_call(__scm->dev, &desc, &res);
  629. if (size)
  630. *size = res.result[0];
  631. return ret ? : res.result[1];
  632. }
  633. EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
  634. int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
  635. {
  636. struct qcom_scm_desc desc = {
  637. .svc = QCOM_SCM_SVC_MP,
  638. .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
  639. .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
  640. QCOM_SCM_VAL),
  641. .args[0] = addr,
  642. .args[1] = size,
  643. .args[2] = spare,
  644. .owner = ARM_SMCCC_OWNER_SIP,
  645. };
  646. int ret;
  647. ret = qcom_scm_call(__scm->dev, &desc, NULL);
  648. /* the pg table has been initialized already, ignore the error */
  649. if (ret == -EPERM)
  650. ret = 0;
  651. return ret;
  652. }
  653. EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
  654. int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
  655. u32 cp_nonpixel_start,
  656. u32 cp_nonpixel_size)
  657. {
  658. int ret;
  659. struct qcom_scm_desc desc = {
  660. .svc = QCOM_SCM_SVC_MP,
  661. .cmd = QCOM_SCM_MP_VIDEO_VAR,
  662. .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL,
  663. QCOM_SCM_VAL, QCOM_SCM_VAL),
  664. .args[0] = cp_start,
  665. .args[1] = cp_size,
  666. .args[2] = cp_nonpixel_start,
  667. .args[3] = cp_nonpixel_size,
  668. .owner = ARM_SMCCC_OWNER_SIP,
  669. };
  670. struct qcom_scm_res res;
  671. ret = qcom_scm_call(__scm->dev, &desc, &res);
  672. return ret ? : res.result[0];
  673. }
  674. EXPORT_SYMBOL(qcom_scm_mem_protect_video_var);
  675. static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
  676. size_t mem_sz, phys_addr_t src, size_t src_sz,
  677. phys_addr_t dest, size_t dest_sz)
  678. {
  679. int ret;
  680. struct qcom_scm_desc desc = {
  681. .svc = QCOM_SCM_SVC_MP,
  682. .cmd = QCOM_SCM_MP_ASSIGN,
  683. .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
  684. QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
  685. QCOM_SCM_VAL, QCOM_SCM_VAL),
  686. .args[0] = mem_region,
  687. .args[1] = mem_sz,
  688. .args[2] = src,
  689. .args[3] = src_sz,
  690. .args[4] = dest,
  691. .args[5] = dest_sz,
  692. .args[6] = 0,
  693. .owner = ARM_SMCCC_OWNER_SIP,
  694. };
  695. struct qcom_scm_res res;
  696. ret = qcom_scm_call(dev, &desc, &res);
  697. return ret ? : res.result[0];
  698. }
  699. /**
  700. * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
  701. * @mem_addr: mem region whose ownership need to be reassigned
  702. * @mem_sz: size of the region.
  703. * @srcvm: vmid for current set of owners, each set bit in
  704. * flag indicate a unique owner
  705. * @newvm: array having new owners and corresponding permission
  706. * flags
  707. * @dest_cnt: number of owners in next set.
  708. *
  709. * Return negative errno on failure or 0 on success with @srcvm updated.
  710. */
  711. int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
  712. unsigned int *srcvm,
  713. const struct qcom_scm_vmperm *newvm,
  714. unsigned int dest_cnt)
  715. {
  716. struct qcom_scm_current_perm_info *destvm;
  717. struct qcom_scm_mem_map_info *mem_to_map;
  718. phys_addr_t mem_to_map_phys;
  719. phys_addr_t dest_phys;
  720. dma_addr_t ptr_phys;
  721. size_t mem_to_map_sz;
  722. size_t dest_sz;
  723. size_t src_sz;
  724. size_t ptr_sz;
  725. int next_vm;
  726. __le32 *src;
  727. void *ptr;
  728. int ret, i, b;
  729. unsigned long srcvm_bits = *srcvm;
  730. src_sz = hweight_long(srcvm_bits) * sizeof(*src);
  731. mem_to_map_sz = sizeof(*mem_to_map);
  732. dest_sz = dest_cnt * sizeof(*destvm);
  733. ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
  734. ALIGN(dest_sz, SZ_64);
  735. ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
  736. if (!ptr)
  737. return -ENOMEM;
  738. /* Fill source vmid detail */
  739. src = ptr;
  740. i = 0;
  741. for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
  742. src[i++] = cpu_to_le32(b);
  743. /* Fill details of mem buff to map */
  744. mem_to_map = ptr + ALIGN(src_sz, SZ_64);
  745. mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
  746. mem_to_map->mem_addr = cpu_to_le64(mem_addr);
  747. mem_to_map->mem_size = cpu_to_le64(mem_sz);
  748. next_vm = 0;
  749. /* Fill details of next vmid detail */
  750. destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
  751. dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
  752. for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
  753. destvm->vmid = cpu_to_le32(newvm->vmid);
  754. destvm->perm = cpu_to_le32(newvm->perm);
  755. destvm->ctx = 0;
  756. destvm->ctx_size = 0;
  757. next_vm |= BIT(newvm->vmid);
  758. }
  759. ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
  760. ptr_phys, src_sz, dest_phys, dest_sz);
  761. dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
  762. if (ret) {
  763. dev_err(__scm->dev,
  764. "Assign memory protection call failed %d\n", ret);
  765. return -EINVAL;
  766. }
  767. *srcvm = next_vm;
  768. return 0;
  769. }
  770. EXPORT_SYMBOL(qcom_scm_assign_mem);
  771. /**
  772. * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
  773. */
  774. bool qcom_scm_ocmem_lock_available(void)
  775. {
  776. return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
  777. QCOM_SCM_OCMEM_LOCK_CMD);
  778. }
  779. EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
  780. /**
  781. * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
  782. * region to the specified initiator
  783. *
  784. * @id: tz initiator id
  785. * @offset: OCMEM offset
  786. * @size: OCMEM size
  787. * @mode: access mode (WIDE/NARROW)
  788. */
  789. int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
  790. u32 mode)
  791. {
  792. struct qcom_scm_desc desc = {
  793. .svc = QCOM_SCM_SVC_OCMEM,
  794. .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
  795. .args[0] = id,
  796. .args[1] = offset,
  797. .args[2] = size,
  798. .args[3] = mode,
  799. .arginfo = QCOM_SCM_ARGS(4),
  800. };
  801. return qcom_scm_call(__scm->dev, &desc, NULL);
  802. }
  803. EXPORT_SYMBOL(qcom_scm_ocmem_lock);
  804. /**
  805. * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
  806. * region from the specified initiator
  807. *
  808. * @id: tz initiator id
  809. * @offset: OCMEM offset
  810. * @size: OCMEM size
  811. */
  812. int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
  813. {
  814. struct qcom_scm_desc desc = {
  815. .svc = QCOM_SCM_SVC_OCMEM,
  816. .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
  817. .args[0] = id,
  818. .args[1] = offset,
  819. .args[2] = size,
  820. .arginfo = QCOM_SCM_ARGS(3),
  821. };
  822. return qcom_scm_call(__scm->dev, &desc, NULL);
  823. }
  824. EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
  825. /**
  826. * qcom_scm_ice_available() - Is the ICE key programming interface available?
  827. *
  828. * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and
  829. * qcom_scm_ice_set_key() are available.
  830. */
  831. bool qcom_scm_ice_available(void)
  832. {
  833. return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
  834. QCOM_SCM_ES_INVALIDATE_ICE_KEY) &&
  835. __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
  836. QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
  837. }
  838. EXPORT_SYMBOL(qcom_scm_ice_available);
  839. /**
  840. * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
  841. * @index: the keyslot to invalidate
  842. *
  843. * The UFSHCI and eMMC standards define a standard way to do this, but it
  844. * doesn't work on these SoCs; only this SCM call does.
  845. *
  846. * It is assumed that the SoC has only one ICE instance being used, as this SCM
  847. * call doesn't specify which ICE instance the keyslot belongs to.
  848. *
  849. * Return: 0 on success; -errno on failure.
  850. */
  851. int qcom_scm_ice_invalidate_key(u32 index)
  852. {
  853. struct qcom_scm_desc desc = {
  854. .svc = QCOM_SCM_SVC_ES,
  855. .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY,
  856. .arginfo = QCOM_SCM_ARGS(1),
  857. .args[0] = index,
  858. .owner = ARM_SMCCC_OWNER_SIP,
  859. };
  860. return qcom_scm_call(__scm->dev, &desc, NULL);
  861. }
  862. EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
  863. /**
  864. * qcom_scm_ice_set_key() - Set an inline encryption key
  865. * @index: the keyslot into which to set the key
  866. * @key: the key to program
  867. * @key_size: the size of the key in bytes
  868. * @cipher: the encryption algorithm the key is for
  869. * @data_unit_size: the encryption data unit size, i.e. the size of each
  870. * individual plaintext and ciphertext. Given in 512-byte
  871. * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
  872. *
  873. * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
  874. * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline.
  875. *
  876. * The UFSHCI and eMMC standards define a standard way to do this, but it
  877. * doesn't work on these SoCs; only this SCM call does.
  878. *
  879. * It is assumed that the SoC has only one ICE instance being used, as this SCM
  880. * call doesn't specify which ICE instance the keyslot belongs to.
  881. *
  882. * Return: 0 on success; -errno on failure.
  883. */
  884. int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
  885. enum qcom_scm_ice_cipher cipher, u32 data_unit_size)
  886. {
  887. struct qcom_scm_desc desc = {
  888. .svc = QCOM_SCM_SVC_ES,
  889. .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY,
  890. .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW,
  891. QCOM_SCM_VAL, QCOM_SCM_VAL,
  892. QCOM_SCM_VAL),
  893. .args[0] = index,
  894. .args[2] = key_size,
  895. .args[3] = cipher,
  896. .args[4] = data_unit_size,
  897. .owner = ARM_SMCCC_OWNER_SIP,
  898. };
  899. void *keybuf;
  900. dma_addr_t key_phys;
  901. int ret;
  902. /*
  903. * 'key' may point to vmalloc()'ed memory, but we need to pass a
  904. * physical address that's been properly flushed. The sanctioned way to
  905. * do this is by using the DMA API. But as is best practice for crypto
  906. * keys, we also must wipe the key after use. This makes kmemdup() +
  907. * dma_map_single() not clearly correct, since the DMA API can use
  908. * bounce buffers. Instead, just use dma_alloc_coherent(). Programming
  909. * keys is normally rare and thus not performance-critical.
  910. */
  911. keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys,
  912. GFP_KERNEL);
  913. if (!keybuf)
  914. return -ENOMEM;
  915. memcpy(keybuf, key, key_size);
  916. desc.args[1] = key_phys;
  917. ret = qcom_scm_call(__scm->dev, &desc, NULL);
  918. memzero_explicit(keybuf, key_size);
  919. dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
  920. return ret;
  921. }
  922. EXPORT_SYMBOL(qcom_scm_ice_set_key);
  923. /**
  924. * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
  925. *
  926. * Return true if HDCP is supported, false if not.
  927. */
  928. bool qcom_scm_hdcp_available(void)
  929. {
  930. bool avail;
  931. int ret = qcom_scm_clk_enable();
  932. if (ret)
  933. return ret;
  934. avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
  935. QCOM_SCM_HDCP_INVOKE);
  936. qcom_scm_clk_disable();
  937. return avail;
  938. }
  939. EXPORT_SYMBOL(qcom_scm_hdcp_available);
  940. /**
  941. * qcom_scm_hdcp_req() - Send HDCP request.
  942. * @req: HDCP request array
  943. * @req_cnt: HDCP request array count
  944. * @resp: response buffer passed to SCM
  945. *
  946. * Write HDCP register(s) through SCM.
  947. */
  948. int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
  949. {
  950. int ret;
  951. struct qcom_scm_desc desc = {
  952. .svc = QCOM_SCM_SVC_HDCP,
  953. .cmd = QCOM_SCM_HDCP_INVOKE,
  954. .arginfo = QCOM_SCM_ARGS(10),
  955. .args = {
  956. req[0].addr,
  957. req[0].val,
  958. req[1].addr,
  959. req[1].val,
  960. req[2].addr,
  961. req[2].val,
  962. req[3].addr,
  963. req[3].val,
  964. req[4].addr,
  965. req[4].val
  966. },
  967. .owner = ARM_SMCCC_OWNER_SIP,
  968. };
  969. struct qcom_scm_res res;
  970. if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
  971. return -ERANGE;
  972. ret = qcom_scm_clk_enable();
  973. if (ret)
  974. return ret;
  975. ret = qcom_scm_call(__scm->dev, &desc, &res);
  976. *resp = res.result[0];
  977. qcom_scm_clk_disable();
  978. return ret;
  979. }
  980. EXPORT_SYMBOL(qcom_scm_hdcp_req);
  981. int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
  982. {
  983. struct qcom_scm_desc desc = {
  984. .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
  985. .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
  986. .arginfo = QCOM_SCM_ARGS(2),
  987. .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
  988. .args[1] = en,
  989. .owner = ARM_SMCCC_OWNER_SIP,
  990. };
  991. return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
  992. }
  993. EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
  994. static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
  995. {
  996. struct device_node *tcsr;
  997. struct device_node *np = dev->of_node;
  998. struct resource res;
  999. u32 offset;
  1000. int ret;
  1001. tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
  1002. if (!tcsr)
  1003. return 0;
  1004. ret = of_address_to_resource(tcsr, 0, &res);
  1005. of_node_put(tcsr);
  1006. if (ret)
  1007. return ret;
  1008. ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
  1009. if (ret < 0)
  1010. return ret;
  1011. *addr = res.start + offset;
  1012. return 0;
  1013. }
  1014. /**
  1015. * qcom_scm_is_available() - Checks if SCM is available
  1016. */
  1017. bool qcom_scm_is_available(void)
  1018. {
  1019. return !!__scm;
  1020. }
  1021. EXPORT_SYMBOL(qcom_scm_is_available);
  1022. static int qcom_scm_probe(struct platform_device *pdev)
  1023. {
  1024. struct qcom_scm *scm;
  1025. unsigned long clks;
  1026. int ret;
  1027. scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
  1028. if (!scm)
  1029. return -ENOMEM;
  1030. ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
  1031. if (ret < 0)
  1032. return ret;
  1033. clks = (unsigned long)of_device_get_match_data(&pdev->dev);
  1034. scm->core_clk = devm_clk_get(&pdev->dev, "core");
  1035. if (IS_ERR(scm->core_clk)) {
  1036. if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
  1037. return PTR_ERR(scm->core_clk);
  1038. if (clks & SCM_HAS_CORE_CLK) {
  1039. dev_err(&pdev->dev, "failed to acquire core clk\n");
  1040. return PTR_ERR(scm->core_clk);
  1041. }
  1042. scm->core_clk = NULL;
  1043. }
  1044. scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
  1045. if (IS_ERR(scm->iface_clk)) {
  1046. if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
  1047. return PTR_ERR(scm->iface_clk);
  1048. if (clks & SCM_HAS_IFACE_CLK) {
  1049. dev_err(&pdev->dev, "failed to acquire iface clk\n");
  1050. return PTR_ERR(scm->iface_clk);
  1051. }
  1052. scm->iface_clk = NULL;
  1053. }
  1054. scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
  1055. if (IS_ERR(scm->bus_clk)) {
  1056. if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
  1057. return PTR_ERR(scm->bus_clk);
  1058. if (clks & SCM_HAS_BUS_CLK) {
  1059. dev_err(&pdev->dev, "failed to acquire bus clk\n");
  1060. return PTR_ERR(scm->bus_clk);
  1061. }
  1062. scm->bus_clk = NULL;
  1063. }
  1064. scm->reset.ops = &qcom_scm_pas_reset_ops;
  1065. scm->reset.nr_resets = 1;
  1066. scm->reset.of_node = pdev->dev.of_node;
  1067. ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
  1068. if (ret)
  1069. return ret;
  1070. /* vote for max clk rate for highest performance */
  1071. ret = clk_set_rate(scm->core_clk, INT_MAX);
  1072. if (ret)
  1073. return ret;
  1074. __scm = scm;
  1075. __scm->dev = &pdev->dev;
  1076. __get_convention();
  1077. /*
  1078. * If requested enable "download mode", from this point on warmboot
  1079. * will cause the the boot stages to enter download mode, unless
  1080. * disabled below by a clean shutdown/reboot.
  1081. */
  1082. if (download_mode)
  1083. qcom_scm_set_download_mode(true);
  1084. return 0;
  1085. }
  1086. static void qcom_scm_shutdown(struct platform_device *pdev)
  1087. {
  1088. /* Clean shutdown, disable download mode to allow normal restart */
  1089. if (download_mode)
  1090. qcom_scm_set_download_mode(false);
  1091. }
  1092. static const struct of_device_id qcom_scm_dt_match[] = {
  1093. { .compatible = "qcom,scm-apq8064",
  1094. /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
  1095. },
  1096. { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
  1097. SCM_HAS_IFACE_CLK |
  1098. SCM_HAS_BUS_CLK)
  1099. },
  1100. { .compatible = "qcom,scm-ipq4019" },
  1101. { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
  1102. { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
  1103. { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
  1104. SCM_HAS_IFACE_CLK |
  1105. SCM_HAS_BUS_CLK)
  1106. },
  1107. { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
  1108. SCM_HAS_IFACE_CLK |
  1109. SCM_HAS_BUS_CLK)
  1110. },
  1111. { .compatible = "qcom,scm-msm8994" },
  1112. { .compatible = "qcom,scm-msm8996" },
  1113. { .compatible = "qcom,scm" },
  1114. {}
  1115. };
  1116. MODULE_DEVICE_TABLE(of, qcom_scm_dt_match);
  1117. static struct platform_driver qcom_scm_driver = {
  1118. .driver = {
  1119. .name = "qcom_scm",
  1120. .of_match_table = qcom_scm_dt_match,
  1121. },
  1122. .probe = qcom_scm_probe,
  1123. .shutdown = qcom_scm_shutdown,
  1124. };
  1125. static int __init qcom_scm_init(void)
  1126. {
  1127. return platform_driver_register(&qcom_scm_driver);
  1128. }
  1129. subsys_initcall(qcom_scm_init);
  1130. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver");
  1131. MODULE_LICENSE("GPL v2");