txx9dmac.h 7.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Driver for the TXx9 SoC DMA Controller
  4. *
  5. * Copyright (C) 2009 Atsushi Nemoto
  6. */
  7. #ifndef TXX9DMAC_H
  8. #define TXX9DMAC_H
  9. #include <linux/dmaengine.h>
  10. #include <asm/txx9/dmac.h>
  11. /*
  12. * Design Notes:
  13. *
  14. * This DMAC have four channels and one FIFO buffer. Each channel can
  15. * be configured for memory-memory or device-memory transfer, but only
  16. * one channel can do alignment-free memory-memory transfer at a time
  17. * while the channel should occupy the FIFO buffer for effective
  18. * transfers.
  19. *
  20. * Instead of dynamically assign the FIFO buffer to channels, I chose
  21. * make one dedicated channel for memory-memory transfer. The
  22. * dedicated channel is public. Other channels are private and used
  23. * for slave transfer. Some devices in the SoC are wired to certain
  24. * DMA channel.
  25. */
  26. #ifdef CONFIG_MACH_TX49XX
  27. static inline bool txx9_dma_have_SMPCHN(void)
  28. {
  29. return true;
  30. }
  31. #define TXX9_DMA_USE_SIMPLE_CHAIN
  32. #else
  33. static inline bool txx9_dma_have_SMPCHN(void)
  34. {
  35. return false;
  36. }
  37. #endif
  38. #ifdef __LITTLE_ENDIAN
  39. #ifdef CONFIG_MACH_TX49XX
  40. #define CCR_LE TXX9_DMA_CCR_LE
  41. #define MCR_LE 0
  42. #else
  43. #define CCR_LE 0
  44. #define MCR_LE TXX9_DMA_MCR_LE
  45. #endif
  46. #else
  47. #define CCR_LE 0
  48. #define MCR_LE 0
  49. #endif
  50. /*
  51. * Redefine this macro to handle differences between 32- and 64-bit
  52. * addressing, big vs. little endian, etc.
  53. */
  54. #ifdef __BIG_ENDIAN
  55. #define TXX9_DMA_REG32(name) u32 __pad_##name; u32 name
  56. #else
  57. #define TXX9_DMA_REG32(name) u32 name; u32 __pad_##name
  58. #endif
  59. /* Hardware register definitions. */
  60. struct txx9dmac_cregs {
  61. #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
  62. TXX9_DMA_REG32(CHAR); /* Chain Address Register */
  63. #else
  64. u64 CHAR; /* Chain Address Register */
  65. #endif
  66. u64 SAR; /* Source Address Register */
  67. u64 DAR; /* Destination Address Register */
  68. TXX9_DMA_REG32(CNTR); /* Count Register */
  69. TXX9_DMA_REG32(SAIR); /* Source Address Increment Register */
  70. TXX9_DMA_REG32(DAIR); /* Destination Address Increment Register */
  71. TXX9_DMA_REG32(CCR); /* Channel Control Register */
  72. TXX9_DMA_REG32(CSR); /* Channel Status Register */
  73. };
  74. struct txx9dmac_cregs32 {
  75. u32 CHAR;
  76. u32 SAR;
  77. u32 DAR;
  78. u32 CNTR;
  79. u32 SAIR;
  80. u32 DAIR;
  81. u32 CCR;
  82. u32 CSR;
  83. };
  84. struct txx9dmac_regs {
  85. /* per-channel registers */
  86. struct txx9dmac_cregs CHAN[TXX9_DMA_MAX_NR_CHANNELS];
  87. u64 __pad[9];
  88. u64 MFDR; /* Memory Fill Data Register */
  89. TXX9_DMA_REG32(MCR); /* Master Control Register */
  90. };
  91. struct txx9dmac_regs32 {
  92. struct txx9dmac_cregs32 CHAN[TXX9_DMA_MAX_NR_CHANNELS];
  93. u32 __pad[9];
  94. u32 MFDR;
  95. u32 MCR;
  96. };
  97. /* bits for MCR */
  98. #define TXX9_DMA_MCR_EIS(ch) (0x10000000<<(ch))
  99. #define TXX9_DMA_MCR_DIS(ch) (0x01000000<<(ch))
  100. #define TXX9_DMA_MCR_RSFIF 0x00000080
  101. #define TXX9_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
  102. #define TXX9_DMA_MCR_LE 0x00000004
  103. #define TXX9_DMA_MCR_RPRT 0x00000002
  104. #define TXX9_DMA_MCR_MSTEN 0x00000001
  105. /* bits for CCRn */
  106. #define TXX9_DMA_CCR_IMMCHN 0x20000000
  107. #define TXX9_DMA_CCR_USEXFSZ 0x10000000
  108. #define TXX9_DMA_CCR_LE 0x08000000
  109. #define TXX9_DMA_CCR_DBINH 0x04000000
  110. #define TXX9_DMA_CCR_SBINH 0x02000000
  111. #define TXX9_DMA_CCR_CHRST 0x01000000
  112. #define TXX9_DMA_CCR_RVBYTE 0x00800000
  113. #define TXX9_DMA_CCR_ACKPOL 0x00400000
  114. #define TXX9_DMA_CCR_REQPL 0x00200000
  115. #define TXX9_DMA_CCR_EGREQ 0x00100000
  116. #define TXX9_DMA_CCR_CHDN 0x00080000
  117. #define TXX9_DMA_CCR_DNCTL 0x00060000
  118. #define TXX9_DMA_CCR_EXTRQ 0x00010000
  119. #define TXX9_DMA_CCR_INTRQD 0x0000e000
  120. #define TXX9_DMA_CCR_INTENE 0x00001000
  121. #define TXX9_DMA_CCR_INTENC 0x00000800
  122. #define TXX9_DMA_CCR_INTENT 0x00000400
  123. #define TXX9_DMA_CCR_CHNEN 0x00000200
  124. #define TXX9_DMA_CCR_XFACT 0x00000100
  125. #define TXX9_DMA_CCR_SMPCHN 0x00000020
  126. #define TXX9_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
  127. #define TXX9_DMA_CCR_XFSZ_1 TXX9_DMA_CCR_XFSZ(0)
  128. #define TXX9_DMA_CCR_XFSZ_2 TXX9_DMA_CCR_XFSZ(1)
  129. #define TXX9_DMA_CCR_XFSZ_4 TXX9_DMA_CCR_XFSZ(2)
  130. #define TXX9_DMA_CCR_XFSZ_8 TXX9_DMA_CCR_XFSZ(3)
  131. #define TXX9_DMA_CCR_XFSZ_X4 TXX9_DMA_CCR_XFSZ(4)
  132. #define TXX9_DMA_CCR_XFSZ_X8 TXX9_DMA_CCR_XFSZ(5)
  133. #define TXX9_DMA_CCR_XFSZ_X16 TXX9_DMA_CCR_XFSZ(6)
  134. #define TXX9_DMA_CCR_XFSZ_X32 TXX9_DMA_CCR_XFSZ(7)
  135. #define TXX9_DMA_CCR_MEMIO 0x00000002
  136. #define TXX9_DMA_CCR_SNGAD 0x00000001
  137. /* bits for CSRn */
  138. #define TXX9_DMA_CSR_CHNEN 0x00000400
  139. #define TXX9_DMA_CSR_STLXFER 0x00000200
  140. #define TXX9_DMA_CSR_XFACT 0x00000100
  141. #define TXX9_DMA_CSR_ABCHC 0x00000080
  142. #define TXX9_DMA_CSR_NCHNC 0x00000040
  143. #define TXX9_DMA_CSR_NTRNFC 0x00000020
  144. #define TXX9_DMA_CSR_EXTDN 0x00000010
  145. #define TXX9_DMA_CSR_CFERR 0x00000008
  146. #define TXX9_DMA_CSR_CHERR 0x00000004
  147. #define TXX9_DMA_CSR_DESERR 0x00000002
  148. #define TXX9_DMA_CSR_SORERR 0x00000001
  149. struct txx9dmac_chan {
  150. struct dma_chan chan;
  151. struct dma_device dma;
  152. struct txx9dmac_dev *ddev;
  153. void __iomem *ch_regs;
  154. struct tasklet_struct tasklet;
  155. int irq;
  156. u32 ccr;
  157. spinlock_t lock;
  158. /* these other elements are all protected by lock */
  159. struct list_head active_list;
  160. struct list_head queue;
  161. struct list_head free_list;
  162. unsigned int descs_allocated;
  163. };
  164. struct txx9dmac_dev {
  165. void __iomem *regs;
  166. struct tasklet_struct tasklet;
  167. int irq;
  168. struct txx9dmac_chan *chan[TXX9_DMA_MAX_NR_CHANNELS];
  169. bool have_64bit_regs;
  170. unsigned int descsize;
  171. };
  172. static inline bool __is_dmac64(const struct txx9dmac_dev *ddev)
  173. {
  174. return ddev->have_64bit_regs;
  175. }
  176. static inline bool is_dmac64(const struct txx9dmac_chan *dc)
  177. {
  178. return __is_dmac64(dc->ddev);
  179. }
  180. #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
  181. /* Hardware descriptor definition. (for simple-chain) */
  182. struct txx9dmac_hwdesc {
  183. #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
  184. TXX9_DMA_REG32(CHAR);
  185. #else
  186. u64 CHAR;
  187. #endif
  188. u64 SAR;
  189. u64 DAR;
  190. TXX9_DMA_REG32(CNTR);
  191. };
  192. struct txx9dmac_hwdesc32 {
  193. u32 CHAR;
  194. u32 SAR;
  195. u32 DAR;
  196. u32 CNTR;
  197. };
  198. #else
  199. #define txx9dmac_hwdesc txx9dmac_cregs
  200. #define txx9dmac_hwdesc32 txx9dmac_cregs32
  201. #endif
  202. struct txx9dmac_desc {
  203. /* FIRST values the hardware uses */
  204. union {
  205. struct txx9dmac_hwdesc hwdesc;
  206. struct txx9dmac_hwdesc32 hwdesc32;
  207. };
  208. /* THEN values for driver housekeeping */
  209. struct list_head desc_node ____cacheline_aligned;
  210. struct list_head tx_list;
  211. struct dma_async_tx_descriptor txd;
  212. size_t len;
  213. };
  214. #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
  215. static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
  216. {
  217. return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;
  218. }
  219. static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
  220. {
  221. dc->ccr |= TXX9_DMA_CCR_INTENT;
  222. }
  223. static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
  224. struct txx9dmac_desc *desc)
  225. {
  226. }
  227. static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
  228. {
  229. dc->ccr |= TXX9_DMA_CCR_SMPCHN;
  230. }
  231. static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
  232. struct txx9dmac_desc *desc,
  233. u32 sair, u32 dair, u32 ccr)
  234. {
  235. }
  236. #else /* TXX9_DMA_USE_SIMPLE_CHAIN */
  237. static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
  238. {
  239. return true;
  240. }
  241. static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
  242. {
  243. }
  244. static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
  245. struct txx9dmac_desc *desc)
  246. {
  247. if (__is_dmac64(ddev))
  248. desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT;
  249. else
  250. desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT;
  251. }
  252. static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
  253. {
  254. }
  255. static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
  256. struct txx9dmac_desc *desc,
  257. u32 sai, u32 dai, u32 ccr)
  258. {
  259. if (__is_dmac64(ddev)) {
  260. desc->hwdesc.SAIR = sai;
  261. desc->hwdesc.DAIR = dai;
  262. desc->hwdesc.CCR = ccr;
  263. } else {
  264. desc->hwdesc32.SAIR = sai;
  265. desc->hwdesc32.DAIR = dai;
  266. desc->hwdesc32.CCR = ccr;
  267. }
  268. }
  269. #endif /* TXX9_DMA_USE_SIMPLE_CHAIN */
  270. #endif /* TXX9DMAC_H */