txx9dmac.c 34 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the TXx9 SoC DMA Controller
  4. *
  5. * Copyright (C) 2009 Atsushi Nemoto
  6. */
  7. #include <linux/dma-mapping.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/scatterlist.h>
  15. #include "dmaengine.h"
  16. #include "txx9dmac.h"
  17. static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
  18. {
  19. return container_of(chan, struct txx9dmac_chan, chan);
  20. }
  21. static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
  22. {
  23. return dc->ch_regs;
  24. }
  25. static struct txx9dmac_cregs32 __iomem *__dma_regs32(
  26. const struct txx9dmac_chan *dc)
  27. {
  28. return dc->ch_regs;
  29. }
  30. #define channel64_readq(dc, name) \
  31. __raw_readq(&(__dma_regs(dc)->name))
  32. #define channel64_writeq(dc, name, val) \
  33. __raw_writeq((val), &(__dma_regs(dc)->name))
  34. #define channel64_readl(dc, name) \
  35. __raw_readl(&(__dma_regs(dc)->name))
  36. #define channel64_writel(dc, name, val) \
  37. __raw_writel((val), &(__dma_regs(dc)->name))
  38. #define channel32_readl(dc, name) \
  39. __raw_readl(&(__dma_regs32(dc)->name))
  40. #define channel32_writel(dc, name, val) \
  41. __raw_writel((val), &(__dma_regs32(dc)->name))
  42. #define channel_readq(dc, name) channel64_readq(dc, name)
  43. #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
  44. #define channel_readl(dc, name) \
  45. (is_dmac64(dc) ? \
  46. channel64_readl(dc, name) : channel32_readl(dc, name))
  47. #define channel_writel(dc, name, val) \
  48. (is_dmac64(dc) ? \
  49. channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
  50. static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
  51. {
  52. if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
  53. return channel64_readq(dc, CHAR);
  54. else
  55. return channel64_readl(dc, CHAR);
  56. }
  57. static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
  58. {
  59. if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
  60. channel64_writeq(dc, CHAR, val);
  61. else
  62. channel64_writel(dc, CHAR, val);
  63. }
  64. static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
  65. {
  66. #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
  67. channel64_writel(dc, CHAR, 0);
  68. channel64_writel(dc, __pad_CHAR, 0);
  69. #else
  70. channel64_writeq(dc, CHAR, 0);
  71. #endif
  72. }
  73. static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
  74. {
  75. if (is_dmac64(dc))
  76. return channel64_read_CHAR(dc);
  77. else
  78. return channel32_readl(dc, CHAR);
  79. }
  80. static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
  81. {
  82. if (is_dmac64(dc))
  83. channel64_write_CHAR(dc, val);
  84. else
  85. channel32_writel(dc, CHAR, val);
  86. }
  87. static struct txx9dmac_regs __iomem *__txx9dmac_regs(
  88. const struct txx9dmac_dev *ddev)
  89. {
  90. return ddev->regs;
  91. }
  92. static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
  93. const struct txx9dmac_dev *ddev)
  94. {
  95. return ddev->regs;
  96. }
  97. #define dma64_readl(ddev, name) \
  98. __raw_readl(&(__txx9dmac_regs(ddev)->name))
  99. #define dma64_writel(ddev, name, val) \
  100. __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
  101. #define dma32_readl(ddev, name) \
  102. __raw_readl(&(__txx9dmac_regs32(ddev)->name))
  103. #define dma32_writel(ddev, name, val) \
  104. __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
  105. #define dma_readl(ddev, name) \
  106. (__is_dmac64(ddev) ? \
  107. dma64_readl(ddev, name) : dma32_readl(ddev, name))
  108. #define dma_writel(ddev, name, val) \
  109. (__is_dmac64(ddev) ? \
  110. dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
  111. static struct device *chan2dev(struct dma_chan *chan)
  112. {
  113. return &chan->dev->device;
  114. }
  115. static struct device *chan2parent(struct dma_chan *chan)
  116. {
  117. return chan->dev->device.parent;
  118. }
  119. static struct txx9dmac_desc *
  120. txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
  121. {
  122. return container_of(txd, struct txx9dmac_desc, txd);
  123. }
  124. static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
  125. const struct txx9dmac_desc *desc)
  126. {
  127. return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
  128. }
  129. static void desc_write_CHAR(const struct txx9dmac_chan *dc,
  130. struct txx9dmac_desc *desc, dma_addr_t val)
  131. {
  132. if (is_dmac64(dc))
  133. desc->hwdesc.CHAR = val;
  134. else
  135. desc->hwdesc32.CHAR = val;
  136. }
  137. #define TXX9_DMA_MAX_COUNT 0x04000000
  138. #define TXX9_DMA_INITIAL_DESC_COUNT 64
  139. static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
  140. {
  141. return list_entry(dc->active_list.next,
  142. struct txx9dmac_desc, desc_node);
  143. }
  144. static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
  145. {
  146. return list_entry(dc->active_list.prev,
  147. struct txx9dmac_desc, desc_node);
  148. }
  149. static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
  150. {
  151. return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
  152. }
  153. static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
  154. {
  155. if (!list_empty(&desc->tx_list))
  156. desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
  157. return desc;
  158. }
  159. static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
  160. static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
  161. gfp_t flags)
  162. {
  163. struct txx9dmac_dev *ddev = dc->ddev;
  164. struct txx9dmac_desc *desc;
  165. desc = kzalloc(sizeof(*desc), flags);
  166. if (!desc)
  167. return NULL;
  168. INIT_LIST_HEAD(&desc->tx_list);
  169. dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
  170. desc->txd.tx_submit = txx9dmac_tx_submit;
  171. /* txd.flags will be overwritten in prep funcs */
  172. desc->txd.flags = DMA_CTRL_ACK;
  173. desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
  174. ddev->descsize, DMA_TO_DEVICE);
  175. return desc;
  176. }
  177. static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
  178. {
  179. struct txx9dmac_desc *desc, *_desc;
  180. struct txx9dmac_desc *ret = NULL;
  181. unsigned int i = 0;
  182. spin_lock_bh(&dc->lock);
  183. list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
  184. if (async_tx_test_ack(&desc->txd)) {
  185. list_del(&desc->desc_node);
  186. ret = desc;
  187. break;
  188. }
  189. dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
  190. i++;
  191. }
  192. spin_unlock_bh(&dc->lock);
  193. dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
  194. i);
  195. if (!ret) {
  196. ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
  197. if (ret) {
  198. spin_lock_bh(&dc->lock);
  199. dc->descs_allocated++;
  200. spin_unlock_bh(&dc->lock);
  201. } else
  202. dev_err(chan2dev(&dc->chan),
  203. "not enough descriptors available\n");
  204. }
  205. return ret;
  206. }
  207. static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
  208. struct txx9dmac_desc *desc)
  209. {
  210. struct txx9dmac_dev *ddev = dc->ddev;
  211. struct txx9dmac_desc *child;
  212. list_for_each_entry(child, &desc->tx_list, desc_node)
  213. dma_sync_single_for_cpu(chan2parent(&dc->chan),
  214. child->txd.phys, ddev->descsize,
  215. DMA_TO_DEVICE);
  216. dma_sync_single_for_cpu(chan2parent(&dc->chan),
  217. desc->txd.phys, ddev->descsize,
  218. DMA_TO_DEVICE);
  219. }
  220. /*
  221. * Move a descriptor, including any children, to the free list.
  222. * `desc' must not be on any lists.
  223. */
  224. static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
  225. struct txx9dmac_desc *desc)
  226. {
  227. if (desc) {
  228. struct txx9dmac_desc *child;
  229. txx9dmac_sync_desc_for_cpu(dc, desc);
  230. spin_lock_bh(&dc->lock);
  231. list_for_each_entry(child, &desc->tx_list, desc_node)
  232. dev_vdbg(chan2dev(&dc->chan),
  233. "moving child desc %p to freelist\n",
  234. child);
  235. list_splice_init(&desc->tx_list, &dc->free_list);
  236. dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
  237. desc);
  238. list_add(&desc->desc_node, &dc->free_list);
  239. spin_unlock_bh(&dc->lock);
  240. }
  241. }
  242. /*----------------------------------------------------------------------*/
  243. static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
  244. {
  245. if (is_dmac64(dc))
  246. dev_err(chan2dev(&dc->chan),
  247. " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
  248. " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
  249. (u64)channel64_read_CHAR(dc),
  250. channel64_readq(dc, SAR),
  251. channel64_readq(dc, DAR),
  252. channel64_readl(dc, CNTR),
  253. channel64_readl(dc, SAIR),
  254. channel64_readl(dc, DAIR),
  255. channel64_readl(dc, CCR),
  256. channel64_readl(dc, CSR));
  257. else
  258. dev_err(chan2dev(&dc->chan),
  259. " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
  260. " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
  261. channel32_readl(dc, CHAR),
  262. channel32_readl(dc, SAR),
  263. channel32_readl(dc, DAR),
  264. channel32_readl(dc, CNTR),
  265. channel32_readl(dc, SAIR),
  266. channel32_readl(dc, DAIR),
  267. channel32_readl(dc, CCR),
  268. channel32_readl(dc, CSR));
  269. }
  270. static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
  271. {
  272. channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
  273. if (is_dmac64(dc)) {
  274. channel64_clear_CHAR(dc);
  275. channel_writeq(dc, SAR, 0);
  276. channel_writeq(dc, DAR, 0);
  277. } else {
  278. channel_writel(dc, CHAR, 0);
  279. channel_writel(dc, SAR, 0);
  280. channel_writel(dc, DAR, 0);
  281. }
  282. channel_writel(dc, CNTR, 0);
  283. channel_writel(dc, SAIR, 0);
  284. channel_writel(dc, DAIR, 0);
  285. channel_writel(dc, CCR, 0);
  286. }
  287. /* Called with dc->lock held and bh disabled */
  288. static void txx9dmac_dostart(struct txx9dmac_chan *dc,
  289. struct txx9dmac_desc *first)
  290. {
  291. struct txx9dmac_slave *ds = dc->chan.private;
  292. u32 sai, dai;
  293. dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
  294. first->txd.cookie, first);
  295. /* ASSERT: channel is idle */
  296. if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
  297. dev_err(chan2dev(&dc->chan),
  298. "BUG: Attempted to start non-idle channel\n");
  299. txx9dmac_dump_regs(dc);
  300. /* The tasklet will hopefully advance the queue... */
  301. return;
  302. }
  303. if (is_dmac64(dc)) {
  304. channel64_writel(dc, CNTR, 0);
  305. channel64_writel(dc, CSR, 0xffffffff);
  306. if (ds) {
  307. if (ds->tx_reg) {
  308. sai = ds->reg_width;
  309. dai = 0;
  310. } else {
  311. sai = 0;
  312. dai = ds->reg_width;
  313. }
  314. } else {
  315. sai = 8;
  316. dai = 8;
  317. }
  318. channel64_writel(dc, SAIR, sai);
  319. channel64_writel(dc, DAIR, dai);
  320. /* All 64-bit DMAC supports SMPCHN */
  321. channel64_writel(dc, CCR, dc->ccr);
  322. /* Writing a non zero value to CHAR will assert XFACT */
  323. channel64_write_CHAR(dc, first->txd.phys);
  324. } else {
  325. channel32_writel(dc, CNTR, 0);
  326. channel32_writel(dc, CSR, 0xffffffff);
  327. if (ds) {
  328. if (ds->tx_reg) {
  329. sai = ds->reg_width;
  330. dai = 0;
  331. } else {
  332. sai = 0;
  333. dai = ds->reg_width;
  334. }
  335. } else {
  336. sai = 4;
  337. dai = 4;
  338. }
  339. channel32_writel(dc, SAIR, sai);
  340. channel32_writel(dc, DAIR, dai);
  341. if (txx9_dma_have_SMPCHN()) {
  342. channel32_writel(dc, CCR, dc->ccr);
  343. /* Writing a non zero value to CHAR will assert XFACT */
  344. channel32_writel(dc, CHAR, first->txd.phys);
  345. } else {
  346. channel32_writel(dc, CHAR, first->txd.phys);
  347. channel32_writel(dc, CCR, dc->ccr);
  348. }
  349. }
  350. }
  351. /*----------------------------------------------------------------------*/
  352. static void
  353. txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
  354. struct txx9dmac_desc *desc)
  355. {
  356. struct dmaengine_desc_callback cb;
  357. struct dma_async_tx_descriptor *txd = &desc->txd;
  358. dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
  359. txd->cookie, desc);
  360. dma_cookie_complete(txd);
  361. dmaengine_desc_get_callback(txd, &cb);
  362. txx9dmac_sync_desc_for_cpu(dc, desc);
  363. list_splice_init(&desc->tx_list, &dc->free_list);
  364. list_move(&desc->desc_node, &dc->free_list);
  365. dma_descriptor_unmap(txd);
  366. /*
  367. * The API requires that no submissions are done from a
  368. * callback, so we don't need to drop the lock here
  369. */
  370. dmaengine_desc_callback_invoke(&cb, NULL);
  371. dma_run_dependencies(txd);
  372. }
  373. static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
  374. {
  375. struct txx9dmac_dev *ddev = dc->ddev;
  376. struct txx9dmac_desc *desc;
  377. struct txx9dmac_desc *prev = NULL;
  378. BUG_ON(!list_empty(list));
  379. do {
  380. desc = txx9dmac_first_queued(dc);
  381. if (prev) {
  382. desc_write_CHAR(dc, prev, desc->txd.phys);
  383. dma_sync_single_for_device(chan2parent(&dc->chan),
  384. prev->txd.phys, ddev->descsize,
  385. DMA_TO_DEVICE);
  386. }
  387. prev = txx9dmac_last_child(desc);
  388. list_move_tail(&desc->desc_node, list);
  389. /* Make chain-completion interrupt happen */
  390. if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
  391. !txx9dmac_chan_INTENT(dc))
  392. break;
  393. } while (!list_empty(&dc->queue));
  394. }
  395. static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
  396. {
  397. struct txx9dmac_desc *desc, *_desc;
  398. LIST_HEAD(list);
  399. /*
  400. * Submit queued descriptors ASAP, i.e. before we go through
  401. * the completed ones.
  402. */
  403. list_splice_init(&dc->active_list, &list);
  404. if (!list_empty(&dc->queue)) {
  405. txx9dmac_dequeue(dc, &dc->active_list);
  406. txx9dmac_dostart(dc, txx9dmac_first_active(dc));
  407. }
  408. list_for_each_entry_safe(desc, _desc, &list, desc_node)
  409. txx9dmac_descriptor_complete(dc, desc);
  410. }
  411. static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
  412. struct txx9dmac_hwdesc *desc)
  413. {
  414. if (is_dmac64(dc)) {
  415. #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
  416. dev_crit(chan2dev(&dc->chan),
  417. " desc: ch%#llx s%#llx d%#llx c%#x\n",
  418. (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
  419. #else
  420. dev_crit(chan2dev(&dc->chan),
  421. " desc: ch%#llx s%#llx d%#llx c%#x"
  422. " si%#x di%#x cc%#x cs%#x\n",
  423. (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
  424. desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
  425. #endif
  426. } else {
  427. struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
  428. #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
  429. dev_crit(chan2dev(&dc->chan),
  430. " desc: ch%#x s%#x d%#x c%#x\n",
  431. d->CHAR, d->SAR, d->DAR, d->CNTR);
  432. #else
  433. dev_crit(chan2dev(&dc->chan),
  434. " desc: ch%#x s%#x d%#x c%#x"
  435. " si%#x di%#x cc%#x cs%#x\n",
  436. d->CHAR, d->SAR, d->DAR, d->CNTR,
  437. d->SAIR, d->DAIR, d->CCR, d->CSR);
  438. #endif
  439. }
  440. }
  441. static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
  442. {
  443. struct txx9dmac_desc *bad_desc;
  444. struct txx9dmac_desc *child;
  445. u32 errors;
  446. /*
  447. * The descriptor currently at the head of the active list is
  448. * borked. Since we don't have any way to report errors, we'll
  449. * just have to scream loudly and try to carry on.
  450. */
  451. dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
  452. txx9dmac_dump_regs(dc);
  453. bad_desc = txx9dmac_first_active(dc);
  454. list_del_init(&bad_desc->desc_node);
  455. /* Clear all error flags and try to restart the controller */
  456. errors = csr & (TXX9_DMA_CSR_ABCHC |
  457. TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
  458. TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
  459. channel_writel(dc, CSR, errors);
  460. if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
  461. txx9dmac_dequeue(dc, &dc->active_list);
  462. if (!list_empty(&dc->active_list))
  463. txx9dmac_dostart(dc, txx9dmac_first_active(dc));
  464. dev_crit(chan2dev(&dc->chan),
  465. "Bad descriptor submitted for DMA! (cookie: %d)\n",
  466. bad_desc->txd.cookie);
  467. txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
  468. list_for_each_entry(child, &bad_desc->tx_list, desc_node)
  469. txx9dmac_dump_desc(dc, &child->hwdesc);
  470. /* Pretend the descriptor completed successfully */
  471. txx9dmac_descriptor_complete(dc, bad_desc);
  472. }
  473. static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
  474. {
  475. dma_addr_t chain;
  476. struct txx9dmac_desc *desc, *_desc;
  477. struct txx9dmac_desc *child;
  478. u32 csr;
  479. if (is_dmac64(dc)) {
  480. chain = channel64_read_CHAR(dc);
  481. csr = channel64_readl(dc, CSR);
  482. channel64_writel(dc, CSR, csr);
  483. } else {
  484. chain = channel32_readl(dc, CHAR);
  485. csr = channel32_readl(dc, CSR);
  486. channel32_writel(dc, CSR, csr);
  487. }
  488. /* For dynamic chain, we should look at XFACT instead of NCHNC */
  489. if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
  490. /* Everything we've submitted is done */
  491. txx9dmac_complete_all(dc);
  492. return;
  493. }
  494. if (!(csr & TXX9_DMA_CSR_CHNEN))
  495. chain = 0; /* last descriptor of this chain */
  496. dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
  497. (u64)chain);
  498. list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
  499. if (desc_read_CHAR(dc, desc) == chain) {
  500. /* This one is currently in progress */
  501. if (csr & TXX9_DMA_CSR_ABCHC)
  502. goto scan_done;
  503. return;
  504. }
  505. list_for_each_entry(child, &desc->tx_list, desc_node)
  506. if (desc_read_CHAR(dc, child) == chain) {
  507. /* Currently in progress */
  508. if (csr & TXX9_DMA_CSR_ABCHC)
  509. goto scan_done;
  510. return;
  511. }
  512. /*
  513. * No descriptors so far seem to be in progress, i.e.
  514. * this one must be done.
  515. */
  516. txx9dmac_descriptor_complete(dc, desc);
  517. }
  518. scan_done:
  519. if (csr & TXX9_DMA_CSR_ABCHC) {
  520. txx9dmac_handle_error(dc, csr);
  521. return;
  522. }
  523. dev_err(chan2dev(&dc->chan),
  524. "BUG: All descriptors done, but channel not idle!\n");
  525. /* Try to continue after resetting the channel... */
  526. txx9dmac_reset_chan(dc);
  527. if (!list_empty(&dc->queue)) {
  528. txx9dmac_dequeue(dc, &dc->active_list);
  529. txx9dmac_dostart(dc, txx9dmac_first_active(dc));
  530. }
  531. }
  532. static void txx9dmac_chan_tasklet(struct tasklet_struct *t)
  533. {
  534. int irq;
  535. u32 csr;
  536. struct txx9dmac_chan *dc;
  537. dc = from_tasklet(dc, t, tasklet);
  538. csr = channel_readl(dc, CSR);
  539. dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
  540. spin_lock(&dc->lock);
  541. if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
  542. TXX9_DMA_CSR_NTRNFC))
  543. txx9dmac_scan_descriptors(dc);
  544. spin_unlock(&dc->lock);
  545. irq = dc->irq;
  546. enable_irq(irq);
  547. }
  548. static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
  549. {
  550. struct txx9dmac_chan *dc = dev_id;
  551. dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
  552. channel_readl(dc, CSR));
  553. tasklet_schedule(&dc->tasklet);
  554. /*
  555. * Just disable the interrupts. We'll turn them back on in the
  556. * softirq handler.
  557. */
  558. disable_irq_nosync(irq);
  559. return IRQ_HANDLED;
  560. }
  561. static void txx9dmac_tasklet(struct tasklet_struct *t)
  562. {
  563. int irq;
  564. u32 csr;
  565. struct txx9dmac_chan *dc;
  566. struct txx9dmac_dev *ddev = from_tasklet(ddev, t, tasklet);
  567. u32 mcr;
  568. int i;
  569. mcr = dma_readl(ddev, MCR);
  570. dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
  571. for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
  572. if ((mcr >> (24 + i)) & 0x11) {
  573. dc = ddev->chan[i];
  574. csr = channel_readl(dc, CSR);
  575. dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
  576. csr);
  577. spin_lock(&dc->lock);
  578. if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
  579. TXX9_DMA_CSR_NTRNFC))
  580. txx9dmac_scan_descriptors(dc);
  581. spin_unlock(&dc->lock);
  582. }
  583. }
  584. irq = ddev->irq;
  585. enable_irq(irq);
  586. }
  587. static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
  588. {
  589. struct txx9dmac_dev *ddev = dev_id;
  590. dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
  591. dma_readl(ddev, MCR));
  592. tasklet_schedule(&ddev->tasklet);
  593. /*
  594. * Just disable the interrupts. We'll turn them back on in the
  595. * softirq handler.
  596. */
  597. disable_irq_nosync(irq);
  598. return IRQ_HANDLED;
  599. }
  600. /*----------------------------------------------------------------------*/
  601. static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
  602. {
  603. struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
  604. struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
  605. dma_cookie_t cookie;
  606. spin_lock_bh(&dc->lock);
  607. cookie = dma_cookie_assign(tx);
  608. dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
  609. desc->txd.cookie, desc);
  610. list_add_tail(&desc->desc_node, &dc->queue);
  611. spin_unlock_bh(&dc->lock);
  612. return cookie;
  613. }
  614. static struct dma_async_tx_descriptor *
  615. txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  616. size_t len, unsigned long flags)
  617. {
  618. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  619. struct txx9dmac_dev *ddev = dc->ddev;
  620. struct txx9dmac_desc *desc;
  621. struct txx9dmac_desc *first;
  622. struct txx9dmac_desc *prev;
  623. size_t xfer_count;
  624. size_t offset;
  625. dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
  626. (u64)dest, (u64)src, len, flags);
  627. if (unlikely(!len)) {
  628. dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
  629. return NULL;
  630. }
  631. prev = first = NULL;
  632. for (offset = 0; offset < len; offset += xfer_count) {
  633. xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
  634. /*
  635. * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
  636. * ERT-TX49H4-016 (slightly conservative)
  637. */
  638. if (__is_dmac64(ddev)) {
  639. if (xfer_count > 0x100 &&
  640. (xfer_count & 0xff) >= 0xfa &&
  641. (xfer_count & 0xff) <= 0xff)
  642. xfer_count -= 0x20;
  643. } else {
  644. if (xfer_count > 0x80 &&
  645. (xfer_count & 0x7f) >= 0x7e &&
  646. (xfer_count & 0x7f) <= 0x7f)
  647. xfer_count -= 0x20;
  648. }
  649. desc = txx9dmac_desc_get(dc);
  650. if (!desc) {
  651. txx9dmac_desc_put(dc, first);
  652. return NULL;
  653. }
  654. if (__is_dmac64(ddev)) {
  655. desc->hwdesc.SAR = src + offset;
  656. desc->hwdesc.DAR = dest + offset;
  657. desc->hwdesc.CNTR = xfer_count;
  658. txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
  659. dc->ccr | TXX9_DMA_CCR_XFACT);
  660. } else {
  661. desc->hwdesc32.SAR = src + offset;
  662. desc->hwdesc32.DAR = dest + offset;
  663. desc->hwdesc32.CNTR = xfer_count;
  664. txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
  665. dc->ccr | TXX9_DMA_CCR_XFACT);
  666. }
  667. /*
  668. * The descriptors on tx_list are not reachable from
  669. * the dc->queue list or dc->active_list after a
  670. * submit. If we put all descriptors on active_list,
  671. * calling of callback on the completion will be more
  672. * complex.
  673. */
  674. if (!first) {
  675. first = desc;
  676. } else {
  677. desc_write_CHAR(dc, prev, desc->txd.phys);
  678. dma_sync_single_for_device(chan2parent(&dc->chan),
  679. prev->txd.phys, ddev->descsize,
  680. DMA_TO_DEVICE);
  681. list_add_tail(&desc->desc_node, &first->tx_list);
  682. }
  683. prev = desc;
  684. }
  685. /* Trigger interrupt after last block */
  686. if (flags & DMA_PREP_INTERRUPT)
  687. txx9dmac_desc_set_INTENT(ddev, prev);
  688. desc_write_CHAR(dc, prev, 0);
  689. dma_sync_single_for_device(chan2parent(&dc->chan),
  690. prev->txd.phys, ddev->descsize,
  691. DMA_TO_DEVICE);
  692. first->txd.flags = flags;
  693. first->len = len;
  694. return &first->txd;
  695. }
  696. static struct dma_async_tx_descriptor *
  697. txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  698. unsigned int sg_len, enum dma_transfer_direction direction,
  699. unsigned long flags, void *context)
  700. {
  701. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  702. struct txx9dmac_dev *ddev = dc->ddev;
  703. struct txx9dmac_slave *ds = chan->private;
  704. struct txx9dmac_desc *prev;
  705. struct txx9dmac_desc *first;
  706. unsigned int i;
  707. struct scatterlist *sg;
  708. dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
  709. BUG_ON(!ds || !ds->reg_width);
  710. if (ds->tx_reg)
  711. BUG_ON(direction != DMA_MEM_TO_DEV);
  712. else
  713. BUG_ON(direction != DMA_DEV_TO_MEM);
  714. if (unlikely(!sg_len))
  715. return NULL;
  716. prev = first = NULL;
  717. for_each_sg(sgl, sg, sg_len, i) {
  718. struct txx9dmac_desc *desc;
  719. dma_addr_t mem;
  720. u32 sai, dai;
  721. desc = txx9dmac_desc_get(dc);
  722. if (!desc) {
  723. txx9dmac_desc_put(dc, first);
  724. return NULL;
  725. }
  726. mem = sg_dma_address(sg);
  727. if (__is_dmac64(ddev)) {
  728. if (direction == DMA_MEM_TO_DEV) {
  729. desc->hwdesc.SAR = mem;
  730. desc->hwdesc.DAR = ds->tx_reg;
  731. } else {
  732. desc->hwdesc.SAR = ds->rx_reg;
  733. desc->hwdesc.DAR = mem;
  734. }
  735. desc->hwdesc.CNTR = sg_dma_len(sg);
  736. } else {
  737. if (direction == DMA_MEM_TO_DEV) {
  738. desc->hwdesc32.SAR = mem;
  739. desc->hwdesc32.DAR = ds->tx_reg;
  740. } else {
  741. desc->hwdesc32.SAR = ds->rx_reg;
  742. desc->hwdesc32.DAR = mem;
  743. }
  744. desc->hwdesc32.CNTR = sg_dma_len(sg);
  745. }
  746. if (direction == DMA_MEM_TO_DEV) {
  747. sai = ds->reg_width;
  748. dai = 0;
  749. } else {
  750. sai = 0;
  751. dai = ds->reg_width;
  752. }
  753. txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
  754. dc->ccr | TXX9_DMA_CCR_XFACT);
  755. if (!first) {
  756. first = desc;
  757. } else {
  758. desc_write_CHAR(dc, prev, desc->txd.phys);
  759. dma_sync_single_for_device(chan2parent(&dc->chan),
  760. prev->txd.phys,
  761. ddev->descsize,
  762. DMA_TO_DEVICE);
  763. list_add_tail(&desc->desc_node, &first->tx_list);
  764. }
  765. prev = desc;
  766. }
  767. /* Trigger interrupt after last block */
  768. if (flags & DMA_PREP_INTERRUPT)
  769. txx9dmac_desc_set_INTENT(ddev, prev);
  770. desc_write_CHAR(dc, prev, 0);
  771. dma_sync_single_for_device(chan2parent(&dc->chan),
  772. prev->txd.phys, ddev->descsize,
  773. DMA_TO_DEVICE);
  774. first->txd.flags = flags;
  775. first->len = 0;
  776. return &first->txd;
  777. }
  778. static int txx9dmac_terminate_all(struct dma_chan *chan)
  779. {
  780. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  781. struct txx9dmac_desc *desc, *_desc;
  782. LIST_HEAD(list);
  783. dev_vdbg(chan2dev(chan), "terminate_all\n");
  784. spin_lock_bh(&dc->lock);
  785. txx9dmac_reset_chan(dc);
  786. /* active_list entries will end up before queued entries */
  787. list_splice_init(&dc->queue, &list);
  788. list_splice_init(&dc->active_list, &list);
  789. spin_unlock_bh(&dc->lock);
  790. /* Flush all pending and queued descriptors */
  791. list_for_each_entry_safe(desc, _desc, &list, desc_node)
  792. txx9dmac_descriptor_complete(dc, desc);
  793. return 0;
  794. }
  795. static enum dma_status
  796. txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  797. struct dma_tx_state *txstate)
  798. {
  799. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  800. enum dma_status ret;
  801. ret = dma_cookie_status(chan, cookie, txstate);
  802. if (ret == DMA_COMPLETE)
  803. return DMA_COMPLETE;
  804. spin_lock_bh(&dc->lock);
  805. txx9dmac_scan_descriptors(dc);
  806. spin_unlock_bh(&dc->lock);
  807. return dma_cookie_status(chan, cookie, txstate);
  808. }
  809. static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
  810. struct txx9dmac_desc *prev)
  811. {
  812. struct txx9dmac_dev *ddev = dc->ddev;
  813. struct txx9dmac_desc *desc;
  814. LIST_HEAD(list);
  815. prev = txx9dmac_last_child(prev);
  816. txx9dmac_dequeue(dc, &list);
  817. desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
  818. desc_write_CHAR(dc, prev, desc->txd.phys);
  819. dma_sync_single_for_device(chan2parent(&dc->chan),
  820. prev->txd.phys, ddev->descsize,
  821. DMA_TO_DEVICE);
  822. if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
  823. channel_read_CHAR(dc) == prev->txd.phys)
  824. /* Restart chain DMA */
  825. channel_write_CHAR(dc, desc->txd.phys);
  826. list_splice_tail(&list, &dc->active_list);
  827. }
  828. static void txx9dmac_issue_pending(struct dma_chan *chan)
  829. {
  830. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  831. spin_lock_bh(&dc->lock);
  832. if (!list_empty(&dc->active_list))
  833. txx9dmac_scan_descriptors(dc);
  834. if (!list_empty(&dc->queue)) {
  835. if (list_empty(&dc->active_list)) {
  836. txx9dmac_dequeue(dc, &dc->active_list);
  837. txx9dmac_dostart(dc, txx9dmac_first_active(dc));
  838. } else if (txx9_dma_have_SMPCHN()) {
  839. struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
  840. if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
  841. txx9dmac_chan_INTENT(dc))
  842. txx9dmac_chain_dynamic(dc, prev);
  843. }
  844. }
  845. spin_unlock_bh(&dc->lock);
  846. }
  847. static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
  848. {
  849. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  850. struct txx9dmac_slave *ds = chan->private;
  851. struct txx9dmac_desc *desc;
  852. int i;
  853. dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
  854. /* ASSERT: channel is idle */
  855. if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
  856. dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
  857. return -EIO;
  858. }
  859. dma_cookie_init(chan);
  860. dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
  861. txx9dmac_chan_set_SMPCHN(dc);
  862. if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
  863. dc->ccr |= TXX9_DMA_CCR_INTENC;
  864. if (chan->device->device_prep_dma_memcpy) {
  865. if (ds)
  866. return -EINVAL;
  867. dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
  868. } else {
  869. if (!ds ||
  870. (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
  871. return -EINVAL;
  872. dc->ccr |= TXX9_DMA_CCR_EXTRQ |
  873. TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
  874. txx9dmac_chan_set_INTENT(dc);
  875. }
  876. spin_lock_bh(&dc->lock);
  877. i = dc->descs_allocated;
  878. while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
  879. spin_unlock_bh(&dc->lock);
  880. desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
  881. if (!desc) {
  882. dev_info(chan2dev(chan),
  883. "only allocated %d descriptors\n", i);
  884. spin_lock_bh(&dc->lock);
  885. break;
  886. }
  887. txx9dmac_desc_put(dc, desc);
  888. spin_lock_bh(&dc->lock);
  889. i = ++dc->descs_allocated;
  890. }
  891. spin_unlock_bh(&dc->lock);
  892. dev_dbg(chan2dev(chan),
  893. "alloc_chan_resources allocated %d descriptors\n", i);
  894. return i;
  895. }
  896. static void txx9dmac_free_chan_resources(struct dma_chan *chan)
  897. {
  898. struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
  899. struct txx9dmac_dev *ddev = dc->ddev;
  900. struct txx9dmac_desc *desc, *_desc;
  901. LIST_HEAD(list);
  902. dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
  903. dc->descs_allocated);
  904. /* ASSERT: channel is idle */
  905. BUG_ON(!list_empty(&dc->active_list));
  906. BUG_ON(!list_empty(&dc->queue));
  907. BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
  908. spin_lock_bh(&dc->lock);
  909. list_splice_init(&dc->free_list, &list);
  910. dc->descs_allocated = 0;
  911. spin_unlock_bh(&dc->lock);
  912. list_for_each_entry_safe(desc, _desc, &list, desc_node) {
  913. dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
  914. dma_unmap_single(chan2parent(chan), desc->txd.phys,
  915. ddev->descsize, DMA_TO_DEVICE);
  916. kfree(desc);
  917. }
  918. dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
  919. }
  920. /*----------------------------------------------------------------------*/
  921. static void txx9dmac_off(struct txx9dmac_dev *ddev)
  922. {
  923. dma_writel(ddev, MCR, 0);
  924. }
  925. static int __init txx9dmac_chan_probe(struct platform_device *pdev)
  926. {
  927. struct txx9dmac_chan_platform_data *cpdata =
  928. dev_get_platdata(&pdev->dev);
  929. struct platform_device *dmac_dev = cpdata->dmac_dev;
  930. struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
  931. struct txx9dmac_chan *dc;
  932. int err;
  933. int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
  934. int irq;
  935. dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
  936. if (!dc)
  937. return -ENOMEM;
  938. dc->dma.dev = &pdev->dev;
  939. dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
  940. dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
  941. dc->dma.device_terminate_all = txx9dmac_terminate_all;
  942. dc->dma.device_tx_status = txx9dmac_tx_status;
  943. dc->dma.device_issue_pending = txx9dmac_issue_pending;
  944. if (pdata && pdata->memcpy_chan == ch) {
  945. dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
  946. dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
  947. } else {
  948. dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
  949. dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
  950. dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
  951. }
  952. INIT_LIST_HEAD(&dc->dma.channels);
  953. dc->ddev = platform_get_drvdata(dmac_dev);
  954. if (dc->ddev->irq < 0) {
  955. irq = platform_get_irq(pdev, 0);
  956. if (irq < 0)
  957. return irq;
  958. tasklet_setup(&dc->tasklet, txx9dmac_chan_tasklet);
  959. dc->irq = irq;
  960. err = devm_request_irq(&pdev->dev, dc->irq,
  961. txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
  962. if (err)
  963. return err;
  964. } else
  965. dc->irq = -1;
  966. dc->ddev->chan[ch] = dc;
  967. dc->chan.device = &dc->dma;
  968. list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
  969. dma_cookie_init(&dc->chan);
  970. if (is_dmac64(dc))
  971. dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
  972. else
  973. dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
  974. spin_lock_init(&dc->lock);
  975. INIT_LIST_HEAD(&dc->active_list);
  976. INIT_LIST_HEAD(&dc->queue);
  977. INIT_LIST_HEAD(&dc->free_list);
  978. txx9dmac_reset_chan(dc);
  979. platform_set_drvdata(pdev, dc);
  980. err = dma_async_device_register(&dc->dma);
  981. if (err)
  982. return err;
  983. dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
  984. dc->dma.dev_id,
  985. dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
  986. dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
  987. return 0;
  988. }
  989. static int txx9dmac_chan_remove(struct platform_device *pdev)
  990. {
  991. struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
  992. dma_async_device_unregister(&dc->dma);
  993. if (dc->irq >= 0) {
  994. devm_free_irq(&pdev->dev, dc->irq, dc);
  995. tasklet_kill(&dc->tasklet);
  996. }
  997. dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
  998. return 0;
  999. }
  1000. static int __init txx9dmac_probe(struct platform_device *pdev)
  1001. {
  1002. struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1003. struct resource *io;
  1004. struct txx9dmac_dev *ddev;
  1005. u32 mcr;
  1006. int err;
  1007. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1008. if (!io)
  1009. return -EINVAL;
  1010. ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
  1011. if (!ddev)
  1012. return -ENOMEM;
  1013. if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
  1014. dev_name(&pdev->dev)))
  1015. return -EBUSY;
  1016. ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
  1017. if (!ddev->regs)
  1018. return -ENOMEM;
  1019. ddev->have_64bit_regs = pdata->have_64bit_regs;
  1020. if (__is_dmac64(ddev))
  1021. ddev->descsize = sizeof(struct txx9dmac_hwdesc);
  1022. else
  1023. ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
  1024. /* force dma off, just in case */
  1025. txx9dmac_off(ddev);
  1026. ddev->irq = platform_get_irq(pdev, 0);
  1027. if (ddev->irq >= 0) {
  1028. tasklet_setup(&ddev->tasklet, txx9dmac_tasklet);
  1029. err = devm_request_irq(&pdev->dev, ddev->irq,
  1030. txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
  1031. if (err)
  1032. return err;
  1033. }
  1034. mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
  1035. if (pdata && pdata->memcpy_chan >= 0)
  1036. mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
  1037. dma_writel(ddev, MCR, mcr);
  1038. platform_set_drvdata(pdev, ddev);
  1039. return 0;
  1040. }
  1041. static int txx9dmac_remove(struct platform_device *pdev)
  1042. {
  1043. struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
  1044. txx9dmac_off(ddev);
  1045. if (ddev->irq >= 0) {
  1046. devm_free_irq(&pdev->dev, ddev->irq, ddev);
  1047. tasklet_kill(&ddev->tasklet);
  1048. }
  1049. return 0;
  1050. }
  1051. static void txx9dmac_shutdown(struct platform_device *pdev)
  1052. {
  1053. struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
  1054. txx9dmac_off(ddev);
  1055. }
  1056. static int txx9dmac_suspend_noirq(struct device *dev)
  1057. {
  1058. struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
  1059. txx9dmac_off(ddev);
  1060. return 0;
  1061. }
  1062. static int txx9dmac_resume_noirq(struct device *dev)
  1063. {
  1064. struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
  1065. struct txx9dmac_platform_data *pdata = dev_get_platdata(dev);
  1066. u32 mcr;
  1067. mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
  1068. if (pdata && pdata->memcpy_chan >= 0)
  1069. mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
  1070. dma_writel(ddev, MCR, mcr);
  1071. return 0;
  1072. }
  1073. static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
  1074. .suspend_noirq = txx9dmac_suspend_noirq,
  1075. .resume_noirq = txx9dmac_resume_noirq,
  1076. };
  1077. static struct platform_driver txx9dmac_chan_driver = {
  1078. .remove = txx9dmac_chan_remove,
  1079. .driver = {
  1080. .name = "txx9dmac-chan",
  1081. },
  1082. };
  1083. static struct platform_driver txx9dmac_driver = {
  1084. .remove = txx9dmac_remove,
  1085. .shutdown = txx9dmac_shutdown,
  1086. .driver = {
  1087. .name = "txx9dmac",
  1088. .pm = &txx9dmac_dev_pm_ops,
  1089. },
  1090. };
  1091. static int __init txx9dmac_init(void)
  1092. {
  1093. int rc;
  1094. rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
  1095. if (!rc) {
  1096. rc = platform_driver_probe(&txx9dmac_chan_driver,
  1097. txx9dmac_chan_probe);
  1098. if (rc)
  1099. platform_driver_unregister(&txx9dmac_driver);
  1100. }
  1101. return rc;
  1102. }
  1103. module_init(txx9dmac_init);
  1104. static void __exit txx9dmac_exit(void)
  1105. {
  1106. platform_driver_unregister(&txx9dmac_chan_driver);
  1107. platform_driver_unregister(&txx9dmac_driver);
  1108. }
  1109. module_exit(txx9dmac_exit);
  1110. MODULE_LICENSE("GPL");
  1111. MODULE_DESCRIPTION("TXx9 DMA Controller driver");
  1112. MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
  1113. MODULE_ALIAS("platform:txx9dmac");
  1114. MODULE_ALIAS("platform:txx9dmac-chan");