tegra210-adma.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ADMA driver for Nvidia's Tegra210 ADMA controller.
  4. *
  5. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of_dma.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/slab.h>
  15. #include "virt-dma.h"
  16. #define ADMA_CH_CMD 0x00
  17. #define ADMA_CH_STATUS 0x0c
  18. #define ADMA_CH_STATUS_XFER_EN BIT(0)
  19. #define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
  20. #define ADMA_CH_INT_STATUS 0x10
  21. #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
  22. #define ADMA_CH_INT_CLEAR 0x1c
  23. #define ADMA_CH_CTRL 0x24
  24. #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
  25. #define ADMA_CH_CTRL_DIR_AHUB2MEM 2
  26. #define ADMA_CH_CTRL_DIR_MEM2AHUB 4
  27. #define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
  28. #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
  29. #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
  30. #define ADMA_CH_CONFIG 0x28
  31. #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
  32. #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
  33. #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
  34. #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
  35. #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
  36. #define ADMA_CH_CONFIG_MAX_BUFS 8
  37. #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
  38. #define ADMA_CH_FIFO_CTRL 0x2c
  39. #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
  40. #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf)
  41. #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8)
  42. #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f)
  43. #define ADMA_CH_LOWER_SRC_ADDR 0x34
  44. #define ADMA_CH_LOWER_TRG_ADDR 0x3c
  45. #define ADMA_CH_TC 0x44
  46. #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc
  47. #define ADMA_CH_XFER_STATUS 0x54
  48. #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
  49. #define ADMA_GLOBAL_CMD 0x00
  50. #define ADMA_GLOBAL_SOFT_RESET 0x04
  51. #define TEGRA_ADMA_BURST_COMPLETE_TIME 20
  52. #define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
  53. TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
  54. #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
  55. TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
  56. #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
  57. struct tegra_adma;
  58. /*
  59. * struct tegra_adma_chip_data - Tegra chip specific data
  60. * @global_reg_offset: Register offset of DMA global register.
  61. * @global_int_clear: Register offset of DMA global interrupt clear.
  62. * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
  63. * @ch_req_rx_shift: Register offset for AHUB receive channel select.
  64. * @ch_base_offset: Register offset of DMA channel registers.
  65. * @has_outstanding_reqs: If DMA channel can have outstanding requests.
  66. * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
  67. * @ch_req_mask: Mask for Tx or Rx channel select.
  68. * @ch_req_max: Maximum number of Tx or Rx channels available.
  69. * @ch_reg_size: Size of DMA channel register space.
  70. * @nr_channels: Number of DMA channels available.
  71. */
  72. struct tegra_adma_chip_data {
  73. unsigned int (*adma_get_burst_config)(unsigned int burst_size);
  74. unsigned int global_reg_offset;
  75. unsigned int global_int_clear;
  76. unsigned int ch_req_tx_shift;
  77. unsigned int ch_req_rx_shift;
  78. unsigned int ch_base_offset;
  79. unsigned int ch_fifo_ctrl;
  80. unsigned int ch_req_mask;
  81. unsigned int ch_req_max;
  82. unsigned int ch_reg_size;
  83. unsigned int nr_channels;
  84. bool has_outstanding_reqs;
  85. };
  86. /*
  87. * struct tegra_adma_chan_regs - Tegra ADMA channel registers
  88. */
  89. struct tegra_adma_chan_regs {
  90. unsigned int ctrl;
  91. unsigned int config;
  92. unsigned int src_addr;
  93. unsigned int trg_addr;
  94. unsigned int fifo_ctrl;
  95. unsigned int cmd;
  96. unsigned int tc;
  97. };
  98. /*
  99. * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
  100. */
  101. struct tegra_adma_desc {
  102. struct virt_dma_desc vd;
  103. struct tegra_adma_chan_regs ch_regs;
  104. size_t buf_len;
  105. size_t period_len;
  106. size_t num_periods;
  107. };
  108. /*
  109. * struct tegra_adma_chan - Tegra ADMA channel information
  110. */
  111. struct tegra_adma_chan {
  112. struct virt_dma_chan vc;
  113. struct tegra_adma_desc *desc;
  114. struct tegra_adma *tdma;
  115. int irq;
  116. void __iomem *chan_addr;
  117. /* Slave channel configuration info */
  118. struct dma_slave_config sconfig;
  119. enum dma_transfer_direction sreq_dir;
  120. unsigned int sreq_index;
  121. bool sreq_reserved;
  122. struct tegra_adma_chan_regs ch_regs;
  123. /* Transfer count and position info */
  124. unsigned int tx_buf_count;
  125. unsigned int tx_buf_pos;
  126. };
  127. /*
  128. * struct tegra_adma - Tegra ADMA controller information
  129. */
  130. struct tegra_adma {
  131. struct dma_device dma_dev;
  132. struct device *dev;
  133. void __iomem *base_addr;
  134. struct clk *ahub_clk;
  135. unsigned int nr_channels;
  136. unsigned long rx_requests_reserved;
  137. unsigned long tx_requests_reserved;
  138. /* Used to store global command register state when suspending */
  139. unsigned int global_cmd;
  140. const struct tegra_adma_chip_data *cdata;
  141. /* Last member of the structure */
  142. struct tegra_adma_chan channels[];
  143. };
  144. static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
  145. {
  146. writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
  147. }
  148. static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
  149. {
  150. return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
  151. }
  152. static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
  153. {
  154. writel(val, tdc->chan_addr + reg);
  155. }
  156. static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
  157. {
  158. return readl(tdc->chan_addr + reg);
  159. }
  160. static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
  161. {
  162. return container_of(dc, struct tegra_adma_chan, vc.chan);
  163. }
  164. static inline struct tegra_adma_desc *to_tegra_adma_desc(
  165. struct dma_async_tx_descriptor *td)
  166. {
  167. return container_of(td, struct tegra_adma_desc, vd.tx);
  168. }
  169. static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
  170. {
  171. return tdc->tdma->dev;
  172. }
  173. static void tegra_adma_desc_free(struct virt_dma_desc *vd)
  174. {
  175. kfree(container_of(vd, struct tegra_adma_desc, vd));
  176. }
  177. static int tegra_adma_slave_config(struct dma_chan *dc,
  178. struct dma_slave_config *sconfig)
  179. {
  180. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  181. memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
  182. return 0;
  183. }
  184. static int tegra_adma_init(struct tegra_adma *tdma)
  185. {
  186. u32 status;
  187. int ret;
  188. /* Clear any interrupts */
  189. tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
  190. /* Assert soft reset */
  191. tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
  192. /* Wait for reset to clear */
  193. ret = readx_poll_timeout(readl,
  194. tdma->base_addr +
  195. tdma->cdata->global_reg_offset +
  196. ADMA_GLOBAL_SOFT_RESET,
  197. status, status == 0, 20, 10000);
  198. if (ret)
  199. return ret;
  200. /* Enable global ADMA registers */
  201. tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
  202. return 0;
  203. }
  204. static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
  205. enum dma_transfer_direction direction)
  206. {
  207. struct tegra_adma *tdma = tdc->tdma;
  208. unsigned int sreq_index = tdc->sreq_index;
  209. if (tdc->sreq_reserved)
  210. return tdc->sreq_dir == direction ? 0 : -EINVAL;
  211. if (sreq_index > tdma->cdata->ch_req_max) {
  212. dev_err(tdma->dev, "invalid DMA request\n");
  213. return -EINVAL;
  214. }
  215. switch (direction) {
  216. case DMA_MEM_TO_DEV:
  217. if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
  218. dev_err(tdma->dev, "DMA request reserved\n");
  219. return -EINVAL;
  220. }
  221. break;
  222. case DMA_DEV_TO_MEM:
  223. if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
  224. dev_err(tdma->dev, "DMA request reserved\n");
  225. return -EINVAL;
  226. }
  227. break;
  228. default:
  229. dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
  230. dma_chan_name(&tdc->vc.chan));
  231. return -EINVAL;
  232. }
  233. tdc->sreq_dir = direction;
  234. tdc->sreq_reserved = true;
  235. return 0;
  236. }
  237. static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
  238. {
  239. struct tegra_adma *tdma = tdc->tdma;
  240. if (!tdc->sreq_reserved)
  241. return;
  242. switch (tdc->sreq_dir) {
  243. case DMA_MEM_TO_DEV:
  244. clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
  245. break;
  246. case DMA_DEV_TO_MEM:
  247. clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
  248. break;
  249. default:
  250. dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
  251. dma_chan_name(&tdc->vc.chan));
  252. return;
  253. }
  254. tdc->sreq_reserved = false;
  255. }
  256. static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
  257. {
  258. u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
  259. return status & ADMA_CH_INT_STATUS_XFER_DONE;
  260. }
  261. static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
  262. {
  263. u32 status = tegra_adma_irq_status(tdc);
  264. if (status)
  265. tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
  266. return status;
  267. }
  268. static void tegra_adma_stop(struct tegra_adma_chan *tdc)
  269. {
  270. unsigned int status;
  271. /* Disable ADMA */
  272. tdma_ch_write(tdc, ADMA_CH_CMD, 0);
  273. /* Clear interrupt status */
  274. tegra_adma_irq_clear(tdc);
  275. if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
  276. status, !(status & ADMA_CH_STATUS_XFER_EN),
  277. 20, 10000)) {
  278. dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
  279. return;
  280. }
  281. kfree(tdc->desc);
  282. tdc->desc = NULL;
  283. }
  284. static void tegra_adma_start(struct tegra_adma_chan *tdc)
  285. {
  286. struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
  287. struct tegra_adma_chan_regs *ch_regs;
  288. struct tegra_adma_desc *desc;
  289. if (!vd)
  290. return;
  291. list_del(&vd->node);
  292. desc = to_tegra_adma_desc(&vd->tx);
  293. if (!desc) {
  294. dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
  295. return;
  296. }
  297. ch_regs = &desc->ch_regs;
  298. tdc->tx_buf_pos = 0;
  299. tdc->tx_buf_count = 0;
  300. tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
  301. tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
  302. tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
  303. tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
  304. tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
  305. tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
  306. /* Start ADMA */
  307. tdma_ch_write(tdc, ADMA_CH_CMD, 1);
  308. tdc->desc = desc;
  309. }
  310. static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
  311. {
  312. struct tegra_adma_desc *desc = tdc->desc;
  313. unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
  314. unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
  315. unsigned int periods_remaining;
  316. /*
  317. * Handle wrap around of buffer count register
  318. */
  319. if (pos < tdc->tx_buf_pos)
  320. tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
  321. else
  322. tdc->tx_buf_count += pos - tdc->tx_buf_pos;
  323. periods_remaining = tdc->tx_buf_count % desc->num_periods;
  324. tdc->tx_buf_pos = pos;
  325. return desc->buf_len - (periods_remaining * desc->period_len);
  326. }
  327. static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
  328. {
  329. struct tegra_adma_chan *tdc = dev_id;
  330. unsigned long status;
  331. unsigned long flags;
  332. spin_lock_irqsave(&tdc->vc.lock, flags);
  333. status = tegra_adma_irq_clear(tdc);
  334. if (status == 0 || !tdc->desc) {
  335. spin_unlock_irqrestore(&tdc->vc.lock, flags);
  336. return IRQ_NONE;
  337. }
  338. vchan_cyclic_callback(&tdc->desc->vd);
  339. spin_unlock_irqrestore(&tdc->vc.lock, flags);
  340. return IRQ_HANDLED;
  341. }
  342. static void tegra_adma_issue_pending(struct dma_chan *dc)
  343. {
  344. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  345. unsigned long flags;
  346. spin_lock_irqsave(&tdc->vc.lock, flags);
  347. if (vchan_issue_pending(&tdc->vc)) {
  348. if (!tdc->desc)
  349. tegra_adma_start(tdc);
  350. }
  351. spin_unlock_irqrestore(&tdc->vc.lock, flags);
  352. }
  353. static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
  354. {
  355. u32 csts;
  356. csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
  357. csts &= ADMA_CH_STATUS_XFER_PAUSED;
  358. return csts ? true : false;
  359. }
  360. static int tegra_adma_pause(struct dma_chan *dc)
  361. {
  362. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  363. struct tegra_adma_desc *desc = tdc->desc;
  364. struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
  365. int dcnt = 10;
  366. ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
  367. ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
  368. tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
  369. while (dcnt-- && !tegra_adma_is_paused(tdc))
  370. udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
  371. if (dcnt < 0) {
  372. dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
  373. return -EBUSY;
  374. }
  375. return 0;
  376. }
  377. static int tegra_adma_resume(struct dma_chan *dc)
  378. {
  379. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  380. struct tegra_adma_desc *desc = tdc->desc;
  381. struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
  382. ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
  383. ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
  384. tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
  385. return 0;
  386. }
  387. static int tegra_adma_terminate_all(struct dma_chan *dc)
  388. {
  389. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  390. unsigned long flags;
  391. LIST_HEAD(head);
  392. spin_lock_irqsave(&tdc->vc.lock, flags);
  393. if (tdc->desc)
  394. tegra_adma_stop(tdc);
  395. tegra_adma_request_free(tdc);
  396. vchan_get_all_descriptors(&tdc->vc, &head);
  397. spin_unlock_irqrestore(&tdc->vc.lock, flags);
  398. vchan_dma_desc_free_list(&tdc->vc, &head);
  399. return 0;
  400. }
  401. static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
  402. dma_cookie_t cookie,
  403. struct dma_tx_state *txstate)
  404. {
  405. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  406. struct tegra_adma_desc *desc;
  407. struct virt_dma_desc *vd;
  408. enum dma_status ret;
  409. unsigned long flags;
  410. unsigned int residual;
  411. ret = dma_cookie_status(dc, cookie, txstate);
  412. if (ret == DMA_COMPLETE || !txstate)
  413. return ret;
  414. spin_lock_irqsave(&tdc->vc.lock, flags);
  415. vd = vchan_find_desc(&tdc->vc, cookie);
  416. if (vd) {
  417. desc = to_tegra_adma_desc(&vd->tx);
  418. residual = desc->ch_regs.tc;
  419. } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
  420. residual = tegra_adma_get_residue(tdc);
  421. } else {
  422. residual = 0;
  423. }
  424. spin_unlock_irqrestore(&tdc->vc.lock, flags);
  425. dma_set_residue(txstate, residual);
  426. return ret;
  427. }
  428. static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
  429. {
  430. if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
  431. burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
  432. return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
  433. }
  434. static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
  435. {
  436. if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
  437. burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
  438. return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
  439. }
  440. static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
  441. struct tegra_adma_desc *desc,
  442. dma_addr_t buf_addr,
  443. enum dma_transfer_direction direction)
  444. {
  445. struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
  446. const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
  447. unsigned int burst_size, adma_dir;
  448. if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
  449. return -EINVAL;
  450. switch (direction) {
  451. case DMA_MEM_TO_DEV:
  452. adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
  453. burst_size = tdc->sconfig.dst_maxburst;
  454. ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
  455. ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
  456. cdata->ch_req_mask,
  457. cdata->ch_req_tx_shift);
  458. ch_regs->src_addr = buf_addr;
  459. break;
  460. case DMA_DEV_TO_MEM:
  461. adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
  462. burst_size = tdc->sconfig.src_maxburst;
  463. ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
  464. ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
  465. cdata->ch_req_mask,
  466. cdata->ch_req_rx_shift);
  467. ch_regs->trg_addr = buf_addr;
  468. break;
  469. default:
  470. dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
  471. return -EINVAL;
  472. }
  473. ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
  474. ADMA_CH_CTRL_MODE_CONTINUOUS |
  475. ADMA_CH_CTRL_FLOWCTRL_EN;
  476. ch_regs->config |= cdata->adma_get_burst_config(burst_size);
  477. ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
  478. if (cdata->has_outstanding_reqs)
  479. ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
  480. ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
  481. ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
  482. return tegra_adma_request_alloc(tdc, direction);
  483. }
  484. static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
  485. struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
  486. size_t period_len, enum dma_transfer_direction direction,
  487. unsigned long flags)
  488. {
  489. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  490. struct tegra_adma_desc *desc = NULL;
  491. if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
  492. dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
  493. return NULL;
  494. }
  495. if (buf_len % period_len) {
  496. dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
  497. return NULL;
  498. }
  499. if (!IS_ALIGNED(buf_addr, 4)) {
  500. dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
  501. return NULL;
  502. }
  503. desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
  504. if (!desc)
  505. return NULL;
  506. desc->buf_len = buf_len;
  507. desc->period_len = period_len;
  508. desc->num_periods = buf_len / period_len;
  509. if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
  510. kfree(desc);
  511. return NULL;
  512. }
  513. return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
  514. }
  515. static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
  516. {
  517. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  518. int ret;
  519. ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
  520. if (ret) {
  521. dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
  522. dma_chan_name(dc));
  523. return ret;
  524. }
  525. ret = pm_runtime_get_sync(tdc2dev(tdc));
  526. if (ret < 0) {
  527. pm_runtime_put_noidle(tdc2dev(tdc));
  528. free_irq(tdc->irq, tdc);
  529. return ret;
  530. }
  531. dma_cookie_init(&tdc->vc.chan);
  532. return 0;
  533. }
  534. static void tegra_adma_free_chan_resources(struct dma_chan *dc)
  535. {
  536. struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
  537. tegra_adma_terminate_all(dc);
  538. vchan_free_chan_resources(&tdc->vc);
  539. tasklet_kill(&tdc->vc.task);
  540. free_irq(tdc->irq, tdc);
  541. pm_runtime_put(tdc2dev(tdc));
  542. tdc->sreq_index = 0;
  543. tdc->sreq_dir = DMA_TRANS_NONE;
  544. }
  545. static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
  546. struct of_dma *ofdma)
  547. {
  548. struct tegra_adma *tdma = ofdma->of_dma_data;
  549. struct tegra_adma_chan *tdc;
  550. struct dma_chan *chan;
  551. unsigned int sreq_index;
  552. if (dma_spec->args_count != 1)
  553. return NULL;
  554. sreq_index = dma_spec->args[0];
  555. if (sreq_index == 0) {
  556. dev_err(tdma->dev, "DMA request must not be 0\n");
  557. return NULL;
  558. }
  559. chan = dma_get_any_slave_channel(&tdma->dma_dev);
  560. if (!chan)
  561. return NULL;
  562. tdc = to_tegra_adma_chan(chan);
  563. tdc->sreq_index = sreq_index;
  564. return chan;
  565. }
  566. static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)
  567. {
  568. struct tegra_adma *tdma = dev_get_drvdata(dev);
  569. struct tegra_adma_chan_regs *ch_reg;
  570. struct tegra_adma_chan *tdc;
  571. int i;
  572. tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
  573. if (!tdma->global_cmd)
  574. goto clk_disable;
  575. for (i = 0; i < tdma->nr_channels; i++) {
  576. tdc = &tdma->channels[i];
  577. ch_reg = &tdc->ch_regs;
  578. ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
  579. /* skip if channel is not active */
  580. if (!ch_reg->cmd)
  581. continue;
  582. ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
  583. ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
  584. ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
  585. ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
  586. ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
  587. ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
  588. }
  589. clk_disable:
  590. clk_disable_unprepare(tdma->ahub_clk);
  591. return 0;
  592. }
  593. static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)
  594. {
  595. struct tegra_adma *tdma = dev_get_drvdata(dev);
  596. struct tegra_adma_chan_regs *ch_reg;
  597. struct tegra_adma_chan *tdc;
  598. int ret, i;
  599. ret = clk_prepare_enable(tdma->ahub_clk);
  600. if (ret) {
  601. dev_err(dev, "ahub clk_enable failed: %d\n", ret);
  602. return ret;
  603. }
  604. tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
  605. if (!tdma->global_cmd)
  606. return 0;
  607. for (i = 0; i < tdma->nr_channels; i++) {
  608. tdc = &tdma->channels[i];
  609. ch_reg = &tdc->ch_regs;
  610. /* skip if channel was not active earlier */
  611. if (!ch_reg->cmd)
  612. continue;
  613. tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
  614. tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
  615. tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
  616. tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
  617. tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
  618. tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
  619. tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
  620. }
  621. return 0;
  622. }
  623. static const struct tegra_adma_chip_data tegra210_chip_data = {
  624. .adma_get_burst_config = tegra210_adma_get_burst_config,
  625. .global_reg_offset = 0xc00,
  626. .global_int_clear = 0x20,
  627. .ch_req_tx_shift = 28,
  628. .ch_req_rx_shift = 24,
  629. .ch_base_offset = 0,
  630. .has_outstanding_reqs = false,
  631. .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
  632. .ch_req_mask = 0xf,
  633. .ch_req_max = 10,
  634. .ch_reg_size = 0x80,
  635. .nr_channels = 22,
  636. };
  637. static const struct tegra_adma_chip_data tegra186_chip_data = {
  638. .adma_get_burst_config = tegra186_adma_get_burst_config,
  639. .global_reg_offset = 0,
  640. .global_int_clear = 0x402c,
  641. .ch_req_tx_shift = 27,
  642. .ch_req_rx_shift = 22,
  643. .ch_base_offset = 0x10000,
  644. .has_outstanding_reqs = true,
  645. .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
  646. .ch_req_mask = 0x1f,
  647. .ch_req_max = 20,
  648. .ch_reg_size = 0x100,
  649. .nr_channels = 32,
  650. };
  651. static const struct of_device_id tegra_adma_of_match[] = {
  652. { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
  653. { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
  654. { },
  655. };
  656. MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
  657. static int tegra_adma_probe(struct platform_device *pdev)
  658. {
  659. const struct tegra_adma_chip_data *cdata;
  660. struct tegra_adma *tdma;
  661. struct resource *res;
  662. int ret, i;
  663. cdata = of_device_get_match_data(&pdev->dev);
  664. if (!cdata) {
  665. dev_err(&pdev->dev, "device match data not found\n");
  666. return -ENODEV;
  667. }
  668. tdma = devm_kzalloc(&pdev->dev,
  669. struct_size(tdma, channels, cdata->nr_channels),
  670. GFP_KERNEL);
  671. if (!tdma)
  672. return -ENOMEM;
  673. tdma->dev = &pdev->dev;
  674. tdma->cdata = cdata;
  675. tdma->nr_channels = cdata->nr_channels;
  676. platform_set_drvdata(pdev, tdma);
  677. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  678. tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
  679. if (IS_ERR(tdma->base_addr))
  680. return PTR_ERR(tdma->base_addr);
  681. tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
  682. if (IS_ERR(tdma->ahub_clk)) {
  683. dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
  684. return PTR_ERR(tdma->ahub_clk);
  685. }
  686. INIT_LIST_HEAD(&tdma->dma_dev.channels);
  687. for (i = 0; i < tdma->nr_channels; i++) {
  688. struct tegra_adma_chan *tdc = &tdma->channels[i];
  689. tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
  690. + (cdata->ch_reg_size * i);
  691. tdc->irq = of_irq_get(pdev->dev.of_node, i);
  692. if (tdc->irq <= 0) {
  693. ret = tdc->irq ?: -ENXIO;
  694. goto irq_dispose;
  695. }
  696. vchan_init(&tdc->vc, &tdma->dma_dev);
  697. tdc->vc.desc_free = tegra_adma_desc_free;
  698. tdc->tdma = tdma;
  699. }
  700. pm_runtime_enable(&pdev->dev);
  701. ret = pm_runtime_get_sync(&pdev->dev);
  702. if (ret < 0) {
  703. pm_runtime_put_noidle(&pdev->dev);
  704. goto rpm_disable;
  705. }
  706. ret = tegra_adma_init(tdma);
  707. if (ret)
  708. goto rpm_put;
  709. dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
  710. dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
  711. dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
  712. tdma->dma_dev.dev = &pdev->dev;
  713. tdma->dma_dev.device_alloc_chan_resources =
  714. tegra_adma_alloc_chan_resources;
  715. tdma->dma_dev.device_free_chan_resources =
  716. tegra_adma_free_chan_resources;
  717. tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
  718. tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
  719. tdma->dma_dev.device_config = tegra_adma_slave_config;
  720. tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
  721. tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
  722. tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  723. tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  724. tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  725. tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
  726. tdma->dma_dev.device_pause = tegra_adma_pause;
  727. tdma->dma_dev.device_resume = tegra_adma_resume;
  728. ret = dma_async_device_register(&tdma->dma_dev);
  729. if (ret < 0) {
  730. dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
  731. goto rpm_put;
  732. }
  733. ret = of_dma_controller_register(pdev->dev.of_node,
  734. tegra_dma_of_xlate, tdma);
  735. if (ret < 0) {
  736. dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
  737. goto dma_remove;
  738. }
  739. pm_runtime_put(&pdev->dev);
  740. dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
  741. tdma->nr_channels);
  742. return 0;
  743. dma_remove:
  744. dma_async_device_unregister(&tdma->dma_dev);
  745. rpm_put:
  746. pm_runtime_put_sync(&pdev->dev);
  747. rpm_disable:
  748. pm_runtime_disable(&pdev->dev);
  749. irq_dispose:
  750. while (--i >= 0)
  751. irq_dispose_mapping(tdma->channels[i].irq);
  752. return ret;
  753. }
  754. static int tegra_adma_remove(struct platform_device *pdev)
  755. {
  756. struct tegra_adma *tdma = platform_get_drvdata(pdev);
  757. int i;
  758. of_dma_controller_free(pdev->dev.of_node);
  759. dma_async_device_unregister(&tdma->dma_dev);
  760. for (i = 0; i < tdma->nr_channels; ++i)
  761. irq_dispose_mapping(tdma->channels[i].irq);
  762. pm_runtime_put_sync(&pdev->dev);
  763. pm_runtime_disable(&pdev->dev);
  764. return 0;
  765. }
  766. static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
  767. SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
  768. tegra_adma_runtime_resume, NULL)
  769. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  770. pm_runtime_force_resume)
  771. };
  772. static struct platform_driver tegra_admac_driver = {
  773. .driver = {
  774. .name = "tegra-adma",
  775. .pm = &tegra_adma_dev_pm_ops,
  776. .of_match_table = tegra_adma_of_match,
  777. },
  778. .probe = tegra_adma_probe,
  779. .remove = tegra_adma_remove,
  780. };
  781. module_platform_driver(tegra_admac_driver);
  782. MODULE_ALIAS("platform:tegra210-adma");
  783. MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
  784. MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
  785. MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
  786. MODULE_LICENSE("GPL v2");