sun6i-dma.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
  4. * Author: Sugar <shuge@allwinnertech.com>
  5. *
  6. * Copyright (C) 2014 Maxime Ripard
  7. * Maxime Ripard <maxime.ripard@free-electrons.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/of_dma.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/reset.h>
  19. #include <linux/slab.h>
  20. #include <linux/types.h>
  21. #include "virt-dma.h"
  22. /*
  23. * Common registers
  24. */
  25. #define DMA_IRQ_EN(x) ((x) * 0x04)
  26. #define DMA_IRQ_HALF BIT(0)
  27. #define DMA_IRQ_PKG BIT(1)
  28. #define DMA_IRQ_QUEUE BIT(2)
  29. #define DMA_IRQ_CHAN_NR 8
  30. #define DMA_IRQ_CHAN_WIDTH 4
  31. #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10)
  32. #define DMA_STAT 0x30
  33. /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */
  34. #define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4)
  35. /*
  36. * sun8i specific registers
  37. */
  38. #define SUN8I_DMA_GATE 0x20
  39. #define SUN8I_DMA_GATE_ENABLE 0x4
  40. #define SUNXI_H3_SECURE_REG 0x20
  41. #define SUNXI_H3_DMA_GATE 0x28
  42. #define SUNXI_H3_DMA_GATE_ENABLE 0x4
  43. /*
  44. * Channels specific registers
  45. */
  46. #define DMA_CHAN_ENABLE 0x00
  47. #define DMA_CHAN_ENABLE_START BIT(0)
  48. #define DMA_CHAN_ENABLE_STOP 0
  49. #define DMA_CHAN_PAUSE 0x04
  50. #define DMA_CHAN_PAUSE_PAUSE BIT(1)
  51. #define DMA_CHAN_PAUSE_RESUME 0
  52. #define DMA_CHAN_LLI_ADDR 0x08
  53. #define DMA_CHAN_CUR_CFG 0x0c
  54. #define DMA_CHAN_MAX_DRQ_A31 0x1f
  55. #define DMA_CHAN_MAX_DRQ_H6 0x3f
  56. #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
  57. #define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6)
  58. #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
  59. #define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8)
  60. #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
  61. #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
  62. #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
  63. #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
  64. #define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
  65. #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
  66. #define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
  67. #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
  68. #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
  69. #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
  70. #define DMA_CHAN_CUR_SRC 0x10
  71. #define DMA_CHAN_CUR_DST 0x14
  72. #define DMA_CHAN_CUR_CNT 0x18
  73. #define DMA_CHAN_CUR_PARA 0x1c
  74. /*
  75. * Various hardware related defines
  76. */
  77. #define LLI_LAST_ITEM 0xfffff800
  78. #define NORMAL_WAIT 8
  79. #define DRQ_SDRAM 1
  80. #define LINEAR_MODE 0
  81. #define IO_MODE 1
  82. /* forward declaration */
  83. struct sun6i_dma_dev;
  84. /*
  85. * Hardware channels / ports representation
  86. *
  87. * The hardware is used in several SoCs, with differing numbers
  88. * of channels and endpoints. This structure ties those numbers
  89. * to a certain compatible string.
  90. */
  91. struct sun6i_dma_config {
  92. u32 nr_max_channels;
  93. u32 nr_max_requests;
  94. u32 nr_max_vchans;
  95. /*
  96. * In the datasheets/user manuals of newer Allwinner SoCs, a special
  97. * bit (bit 2 at register 0x20) is present.
  98. * It's named "DMA MCLK interface circuit auto gating bit" in the
  99. * documents, and the footnote of this register says that this bit
  100. * should be set up when initializing the DMA controller.
  101. * Allwinner A23/A33 user manuals do not have this bit documented,
  102. * however these SoCs really have and need this bit, as seen in the
  103. * BSP kernel source code.
  104. */
  105. void (*clock_autogate_enable)(struct sun6i_dma_dev *);
  106. void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
  107. void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
  108. void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
  109. u32 src_burst_lengths;
  110. u32 dst_burst_lengths;
  111. u32 src_addr_widths;
  112. u32 dst_addr_widths;
  113. bool has_mbus_clk;
  114. };
  115. /*
  116. * Hardware representation of the LLI
  117. *
  118. * The hardware will be fed the physical address of this structure,
  119. * and read its content in order to start the transfer.
  120. */
  121. struct sun6i_dma_lli {
  122. u32 cfg;
  123. u32 src;
  124. u32 dst;
  125. u32 len;
  126. u32 para;
  127. u32 p_lli_next;
  128. /*
  129. * This field is not used by the DMA controller, but will be
  130. * used by the CPU to go through the list (mostly for dumping
  131. * or freeing it).
  132. */
  133. struct sun6i_dma_lli *v_lli_next;
  134. };
  135. struct sun6i_desc {
  136. struct virt_dma_desc vd;
  137. dma_addr_t p_lli;
  138. struct sun6i_dma_lli *v_lli;
  139. };
  140. struct sun6i_pchan {
  141. u32 idx;
  142. void __iomem *base;
  143. struct sun6i_vchan *vchan;
  144. struct sun6i_desc *desc;
  145. struct sun6i_desc *done;
  146. };
  147. struct sun6i_vchan {
  148. struct virt_dma_chan vc;
  149. struct list_head node;
  150. struct dma_slave_config cfg;
  151. struct sun6i_pchan *phy;
  152. u8 port;
  153. u8 irq_type;
  154. bool cyclic;
  155. };
  156. struct sun6i_dma_dev {
  157. struct dma_device slave;
  158. void __iomem *base;
  159. struct clk *clk;
  160. struct clk *clk_mbus;
  161. int irq;
  162. spinlock_t lock;
  163. struct reset_control *rstc;
  164. struct tasklet_struct task;
  165. atomic_t tasklet_shutdown;
  166. struct list_head pending;
  167. struct dma_pool *pool;
  168. struct sun6i_pchan *pchans;
  169. struct sun6i_vchan *vchans;
  170. const struct sun6i_dma_config *cfg;
  171. u32 num_pchans;
  172. u32 num_vchans;
  173. u32 max_request;
  174. };
  175. static struct device *chan2dev(struct dma_chan *chan)
  176. {
  177. return &chan->dev->device;
  178. }
  179. static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
  180. {
  181. return container_of(d, struct sun6i_dma_dev, slave);
  182. }
  183. static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
  184. {
  185. return container_of(chan, struct sun6i_vchan, vc.chan);
  186. }
  187. static inline struct sun6i_desc *
  188. to_sun6i_desc(struct dma_async_tx_descriptor *tx)
  189. {
  190. return container_of(tx, struct sun6i_desc, vd.tx);
  191. }
  192. static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
  193. {
  194. dev_dbg(sdev->slave.dev, "Common register:\n"
  195. "\tmask0(%04x): 0x%08x\n"
  196. "\tmask1(%04x): 0x%08x\n"
  197. "\tpend0(%04x): 0x%08x\n"
  198. "\tpend1(%04x): 0x%08x\n"
  199. "\tstats(%04x): 0x%08x\n",
  200. DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
  201. DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
  202. DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
  203. DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
  204. DMA_STAT, readl(sdev->base + DMA_STAT));
  205. }
  206. static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
  207. struct sun6i_pchan *pchan)
  208. {
  209. phys_addr_t reg = virt_to_phys(pchan->base);
  210. dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
  211. "\t___en(%04x): \t0x%08x\n"
  212. "\tpause(%04x): \t0x%08x\n"
  213. "\tstart(%04x): \t0x%08x\n"
  214. "\t__cfg(%04x): \t0x%08x\n"
  215. "\t__src(%04x): \t0x%08x\n"
  216. "\t__dst(%04x): \t0x%08x\n"
  217. "\tcount(%04x): \t0x%08x\n"
  218. "\t_para(%04x): \t0x%08x\n\n",
  219. pchan->idx, &reg,
  220. DMA_CHAN_ENABLE,
  221. readl(pchan->base + DMA_CHAN_ENABLE),
  222. DMA_CHAN_PAUSE,
  223. readl(pchan->base + DMA_CHAN_PAUSE),
  224. DMA_CHAN_LLI_ADDR,
  225. readl(pchan->base + DMA_CHAN_LLI_ADDR),
  226. DMA_CHAN_CUR_CFG,
  227. readl(pchan->base + DMA_CHAN_CUR_CFG),
  228. DMA_CHAN_CUR_SRC,
  229. readl(pchan->base + DMA_CHAN_CUR_SRC),
  230. DMA_CHAN_CUR_DST,
  231. readl(pchan->base + DMA_CHAN_CUR_DST),
  232. DMA_CHAN_CUR_CNT,
  233. readl(pchan->base + DMA_CHAN_CUR_CNT),
  234. DMA_CHAN_CUR_PARA,
  235. readl(pchan->base + DMA_CHAN_CUR_PARA));
  236. }
  237. static inline s8 convert_burst(u32 maxburst)
  238. {
  239. switch (maxburst) {
  240. case 1:
  241. return 0;
  242. case 4:
  243. return 1;
  244. case 8:
  245. return 2;
  246. case 16:
  247. return 3;
  248. default:
  249. return -EINVAL;
  250. }
  251. }
  252. static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
  253. {
  254. return ilog2(addr_width);
  255. }
  256. static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
  257. {
  258. writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
  259. }
  260. static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
  261. {
  262. writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
  263. }
  264. static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst)
  265. {
  266. *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
  267. DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
  268. }
  269. static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
  270. {
  271. *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
  272. DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
  273. }
  274. static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
  275. {
  276. *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
  277. DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
  278. }
  279. static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
  280. {
  281. *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
  282. DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
  283. }
  284. static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
  285. {
  286. *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
  287. DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
  288. }
  289. static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
  290. {
  291. *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
  292. DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
  293. }
  294. static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
  295. {
  296. struct sun6i_desc *txd = pchan->desc;
  297. struct sun6i_dma_lli *lli;
  298. size_t bytes;
  299. dma_addr_t pos;
  300. pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
  301. bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
  302. if (pos == LLI_LAST_ITEM)
  303. return bytes;
  304. for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
  305. if (lli->p_lli_next == pos) {
  306. for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
  307. bytes += lli->len;
  308. break;
  309. }
  310. }
  311. return bytes;
  312. }
  313. static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
  314. struct sun6i_dma_lli *next,
  315. dma_addr_t next_phy,
  316. struct sun6i_desc *txd)
  317. {
  318. if ((!prev && !txd) || !next)
  319. return NULL;
  320. if (!prev) {
  321. txd->p_lli = next_phy;
  322. txd->v_lli = next;
  323. } else {
  324. prev->p_lli_next = next_phy;
  325. prev->v_lli_next = next;
  326. }
  327. next->p_lli_next = LLI_LAST_ITEM;
  328. next->v_lli_next = NULL;
  329. return next;
  330. }
  331. static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
  332. struct sun6i_dma_lli *lli)
  333. {
  334. phys_addr_t p_lli = virt_to_phys(lli);
  335. dev_dbg(chan2dev(&vchan->vc.chan),
  336. "\n\tdesc: p - %pa v - 0x%p\n"
  337. "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
  338. "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
  339. &p_lli, lli,
  340. lli->cfg, lli->src, lli->dst,
  341. lli->len, lli->para, lli->p_lli_next);
  342. }
  343. static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
  344. {
  345. struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
  346. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
  347. struct sun6i_dma_lli *v_lli, *v_next;
  348. dma_addr_t p_lli, p_next;
  349. if (unlikely(!txd))
  350. return;
  351. p_lli = txd->p_lli;
  352. v_lli = txd->v_lli;
  353. while (v_lli) {
  354. v_next = v_lli->v_lli_next;
  355. p_next = v_lli->p_lli_next;
  356. dma_pool_free(sdev->pool, v_lli, p_lli);
  357. v_lli = v_next;
  358. p_lli = p_next;
  359. }
  360. kfree(txd);
  361. }
  362. static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
  363. {
  364. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
  365. struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
  366. struct sun6i_pchan *pchan = vchan->phy;
  367. u32 irq_val, irq_reg, irq_offset;
  368. if (!pchan)
  369. return -EAGAIN;
  370. if (!desc) {
  371. pchan->desc = NULL;
  372. pchan->done = NULL;
  373. return -EAGAIN;
  374. }
  375. list_del(&desc->node);
  376. pchan->desc = to_sun6i_desc(&desc->tx);
  377. pchan->done = NULL;
  378. sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
  379. irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
  380. irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
  381. vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
  382. irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
  383. irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
  384. (irq_offset * DMA_IRQ_CHAN_WIDTH));
  385. irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
  386. writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
  387. writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
  388. writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
  389. sun6i_dma_dump_com_regs(sdev);
  390. sun6i_dma_dump_chan_regs(sdev, pchan);
  391. return 0;
  392. }
  393. static void sun6i_dma_tasklet(struct tasklet_struct *t)
  394. {
  395. struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task);
  396. struct sun6i_vchan *vchan;
  397. struct sun6i_pchan *pchan;
  398. unsigned int pchan_alloc = 0;
  399. unsigned int pchan_idx;
  400. list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
  401. spin_lock_irq(&vchan->vc.lock);
  402. pchan = vchan->phy;
  403. if (pchan && pchan->done) {
  404. if (sun6i_dma_start_desc(vchan)) {
  405. /*
  406. * No current txd associated with this channel
  407. */
  408. dev_dbg(sdev->slave.dev, "pchan %u: free\n",
  409. pchan->idx);
  410. /* Mark this channel free */
  411. vchan->phy = NULL;
  412. pchan->vchan = NULL;
  413. }
  414. }
  415. spin_unlock_irq(&vchan->vc.lock);
  416. }
  417. spin_lock_irq(&sdev->lock);
  418. for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
  419. pchan = &sdev->pchans[pchan_idx];
  420. if (pchan->vchan || list_empty(&sdev->pending))
  421. continue;
  422. vchan = list_first_entry(&sdev->pending,
  423. struct sun6i_vchan, node);
  424. /* Remove from pending channels */
  425. list_del_init(&vchan->node);
  426. pchan_alloc |= BIT(pchan_idx);
  427. /* Mark this channel allocated */
  428. pchan->vchan = vchan;
  429. vchan->phy = pchan;
  430. dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
  431. pchan->idx, &vchan->vc);
  432. }
  433. spin_unlock_irq(&sdev->lock);
  434. for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
  435. if (!(pchan_alloc & BIT(pchan_idx)))
  436. continue;
  437. pchan = sdev->pchans + pchan_idx;
  438. vchan = pchan->vchan;
  439. if (vchan) {
  440. spin_lock_irq(&vchan->vc.lock);
  441. sun6i_dma_start_desc(vchan);
  442. spin_unlock_irq(&vchan->vc.lock);
  443. }
  444. }
  445. }
  446. static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
  447. {
  448. struct sun6i_dma_dev *sdev = dev_id;
  449. struct sun6i_vchan *vchan;
  450. struct sun6i_pchan *pchan;
  451. int i, j, ret = IRQ_NONE;
  452. u32 status;
  453. for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) {
  454. status = readl(sdev->base + DMA_IRQ_STAT(i));
  455. if (!status)
  456. continue;
  457. dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
  458. i ? "high" : "low", status);
  459. writel(status, sdev->base + DMA_IRQ_STAT(i));
  460. for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
  461. pchan = sdev->pchans + j;
  462. vchan = pchan->vchan;
  463. if (vchan && (status & vchan->irq_type)) {
  464. if (vchan->cyclic) {
  465. vchan_cyclic_callback(&pchan->desc->vd);
  466. } else {
  467. spin_lock(&vchan->vc.lock);
  468. vchan_cookie_complete(&pchan->desc->vd);
  469. pchan->done = pchan->desc;
  470. spin_unlock(&vchan->vc.lock);
  471. }
  472. }
  473. status = status >> DMA_IRQ_CHAN_WIDTH;
  474. }
  475. if (!atomic_read(&sdev->tasklet_shutdown))
  476. tasklet_schedule(&sdev->task);
  477. ret = IRQ_HANDLED;
  478. }
  479. return ret;
  480. }
  481. static int set_config(struct sun6i_dma_dev *sdev,
  482. struct dma_slave_config *sconfig,
  483. enum dma_transfer_direction direction,
  484. u32 *p_cfg)
  485. {
  486. enum dma_slave_buswidth src_addr_width, dst_addr_width;
  487. u32 src_maxburst, dst_maxburst;
  488. s8 src_width, dst_width, src_burst, dst_burst;
  489. src_addr_width = sconfig->src_addr_width;
  490. dst_addr_width = sconfig->dst_addr_width;
  491. src_maxburst = sconfig->src_maxburst;
  492. dst_maxburst = sconfig->dst_maxburst;
  493. switch (direction) {
  494. case DMA_MEM_TO_DEV:
  495. if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  496. src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  497. src_maxburst = src_maxburst ? src_maxburst : 8;
  498. break;
  499. case DMA_DEV_TO_MEM:
  500. if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  501. dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  502. dst_maxburst = dst_maxburst ? dst_maxburst : 8;
  503. break;
  504. default:
  505. return -EINVAL;
  506. }
  507. if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths))
  508. return -EINVAL;
  509. if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths))
  510. return -EINVAL;
  511. if (!(BIT(src_maxburst) & sdev->cfg->src_burst_lengths))
  512. return -EINVAL;
  513. if (!(BIT(dst_maxburst) & sdev->cfg->dst_burst_lengths))
  514. return -EINVAL;
  515. src_width = convert_buswidth(src_addr_width);
  516. dst_width = convert_buswidth(dst_addr_width);
  517. dst_burst = convert_burst(dst_maxburst);
  518. src_burst = convert_burst(src_maxburst);
  519. *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
  520. DMA_CHAN_CFG_DST_WIDTH(dst_width);
  521. sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst);
  522. return 0;
  523. }
  524. static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
  525. struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  526. size_t len, unsigned long flags)
  527. {
  528. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  529. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  530. struct sun6i_dma_lli *v_lli;
  531. struct sun6i_desc *txd;
  532. dma_addr_t p_lli;
  533. s8 burst, width;
  534. dev_dbg(chan2dev(chan),
  535. "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
  536. __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
  537. if (!len)
  538. return NULL;
  539. txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
  540. if (!txd)
  541. return NULL;
  542. v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
  543. if (!v_lli) {
  544. dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
  545. goto err_txd_free;
  546. }
  547. v_lli->src = src;
  548. v_lli->dst = dest;
  549. v_lli->len = len;
  550. v_lli->para = NORMAL_WAIT;
  551. burst = convert_burst(8);
  552. width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
  553. v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
  554. DMA_CHAN_CFG_DST_WIDTH(width);
  555. sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
  556. sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
  557. sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
  558. sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
  559. sun6i_dma_dump_lli(vchan, v_lli);
  560. return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
  561. err_txd_free:
  562. kfree(txd);
  563. return NULL;
  564. }
  565. static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
  566. struct dma_chan *chan, struct scatterlist *sgl,
  567. unsigned int sg_len, enum dma_transfer_direction dir,
  568. unsigned long flags, void *context)
  569. {
  570. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  571. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  572. struct dma_slave_config *sconfig = &vchan->cfg;
  573. struct sun6i_dma_lli *v_lli, *prev = NULL;
  574. struct sun6i_desc *txd;
  575. struct scatterlist *sg;
  576. dma_addr_t p_lli;
  577. u32 lli_cfg;
  578. int i, ret;
  579. if (!sgl)
  580. return NULL;
  581. ret = set_config(sdev, sconfig, dir, &lli_cfg);
  582. if (ret) {
  583. dev_err(chan2dev(chan), "Invalid DMA configuration\n");
  584. return NULL;
  585. }
  586. txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
  587. if (!txd)
  588. return NULL;
  589. for_each_sg(sgl, sg, sg_len, i) {
  590. v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
  591. if (!v_lli)
  592. goto err_lli_free;
  593. v_lli->len = sg_dma_len(sg);
  594. v_lli->para = NORMAL_WAIT;
  595. if (dir == DMA_MEM_TO_DEV) {
  596. v_lli->src = sg_dma_address(sg);
  597. v_lli->dst = sconfig->dst_addr;
  598. v_lli->cfg = lli_cfg;
  599. sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
  600. sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
  601. dev_dbg(chan2dev(chan),
  602. "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
  603. __func__, vchan->vc.chan.chan_id,
  604. &sconfig->dst_addr, &sg_dma_address(sg),
  605. sg_dma_len(sg), flags);
  606. } else {
  607. v_lli->src = sconfig->src_addr;
  608. v_lli->dst = sg_dma_address(sg);
  609. v_lli->cfg = lli_cfg;
  610. sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
  611. sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
  612. dev_dbg(chan2dev(chan),
  613. "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
  614. __func__, vchan->vc.chan.chan_id,
  615. &sg_dma_address(sg), &sconfig->src_addr,
  616. sg_dma_len(sg), flags);
  617. }
  618. prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
  619. }
  620. dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
  621. for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
  622. sun6i_dma_dump_lli(vchan, prev);
  623. return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
  624. err_lli_free:
  625. for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
  626. dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
  627. kfree(txd);
  628. return NULL;
  629. }
  630. static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
  631. struct dma_chan *chan,
  632. dma_addr_t buf_addr,
  633. size_t buf_len,
  634. size_t period_len,
  635. enum dma_transfer_direction dir,
  636. unsigned long flags)
  637. {
  638. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  639. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  640. struct dma_slave_config *sconfig = &vchan->cfg;
  641. struct sun6i_dma_lli *v_lli, *prev = NULL;
  642. struct sun6i_desc *txd;
  643. dma_addr_t p_lli;
  644. u32 lli_cfg;
  645. unsigned int i, periods = buf_len / period_len;
  646. int ret;
  647. ret = set_config(sdev, sconfig, dir, &lli_cfg);
  648. if (ret) {
  649. dev_err(chan2dev(chan), "Invalid DMA configuration\n");
  650. return NULL;
  651. }
  652. txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
  653. if (!txd)
  654. return NULL;
  655. for (i = 0; i < periods; i++) {
  656. v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
  657. if (!v_lli) {
  658. dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
  659. goto err_lli_free;
  660. }
  661. v_lli->len = period_len;
  662. v_lli->para = NORMAL_WAIT;
  663. if (dir == DMA_MEM_TO_DEV) {
  664. v_lli->src = buf_addr + period_len * i;
  665. v_lli->dst = sconfig->dst_addr;
  666. v_lli->cfg = lli_cfg;
  667. sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
  668. sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
  669. } else {
  670. v_lli->src = sconfig->src_addr;
  671. v_lli->dst = buf_addr + period_len * i;
  672. v_lli->cfg = lli_cfg;
  673. sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
  674. sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
  675. }
  676. prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
  677. }
  678. prev->p_lli_next = txd->p_lli; /* cyclic list */
  679. vchan->cyclic = true;
  680. return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
  681. err_lli_free:
  682. for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
  683. dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
  684. kfree(txd);
  685. return NULL;
  686. }
  687. static int sun6i_dma_config(struct dma_chan *chan,
  688. struct dma_slave_config *config)
  689. {
  690. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  691. memcpy(&vchan->cfg, config, sizeof(*config));
  692. return 0;
  693. }
  694. static int sun6i_dma_pause(struct dma_chan *chan)
  695. {
  696. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  697. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  698. struct sun6i_pchan *pchan = vchan->phy;
  699. dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
  700. if (pchan) {
  701. writel(DMA_CHAN_PAUSE_PAUSE,
  702. pchan->base + DMA_CHAN_PAUSE);
  703. } else {
  704. spin_lock(&sdev->lock);
  705. list_del_init(&vchan->node);
  706. spin_unlock(&sdev->lock);
  707. }
  708. return 0;
  709. }
  710. static int sun6i_dma_resume(struct dma_chan *chan)
  711. {
  712. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  713. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  714. struct sun6i_pchan *pchan = vchan->phy;
  715. unsigned long flags;
  716. dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
  717. spin_lock_irqsave(&vchan->vc.lock, flags);
  718. if (pchan) {
  719. writel(DMA_CHAN_PAUSE_RESUME,
  720. pchan->base + DMA_CHAN_PAUSE);
  721. } else if (!list_empty(&vchan->vc.desc_issued)) {
  722. spin_lock(&sdev->lock);
  723. list_add_tail(&vchan->node, &sdev->pending);
  724. spin_unlock(&sdev->lock);
  725. }
  726. spin_unlock_irqrestore(&vchan->vc.lock, flags);
  727. return 0;
  728. }
  729. static int sun6i_dma_terminate_all(struct dma_chan *chan)
  730. {
  731. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  732. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  733. struct sun6i_pchan *pchan = vchan->phy;
  734. unsigned long flags;
  735. LIST_HEAD(head);
  736. spin_lock(&sdev->lock);
  737. list_del_init(&vchan->node);
  738. spin_unlock(&sdev->lock);
  739. spin_lock_irqsave(&vchan->vc.lock, flags);
  740. if (vchan->cyclic) {
  741. vchan->cyclic = false;
  742. if (pchan && pchan->desc) {
  743. struct virt_dma_desc *vd = &pchan->desc->vd;
  744. struct virt_dma_chan *vc = &vchan->vc;
  745. list_add_tail(&vd->node, &vc->desc_completed);
  746. }
  747. }
  748. vchan_get_all_descriptors(&vchan->vc, &head);
  749. if (pchan) {
  750. writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
  751. writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
  752. vchan->phy = NULL;
  753. pchan->vchan = NULL;
  754. pchan->desc = NULL;
  755. pchan->done = NULL;
  756. }
  757. spin_unlock_irqrestore(&vchan->vc.lock, flags);
  758. vchan_dma_desc_free_list(&vchan->vc, &head);
  759. return 0;
  760. }
  761. static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
  762. dma_cookie_t cookie,
  763. struct dma_tx_state *state)
  764. {
  765. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  766. struct sun6i_pchan *pchan = vchan->phy;
  767. struct sun6i_dma_lli *lli;
  768. struct virt_dma_desc *vd;
  769. struct sun6i_desc *txd;
  770. enum dma_status ret;
  771. unsigned long flags;
  772. size_t bytes = 0;
  773. ret = dma_cookie_status(chan, cookie, state);
  774. if (ret == DMA_COMPLETE || !state)
  775. return ret;
  776. spin_lock_irqsave(&vchan->vc.lock, flags);
  777. vd = vchan_find_desc(&vchan->vc, cookie);
  778. txd = to_sun6i_desc(&vd->tx);
  779. if (vd) {
  780. for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
  781. bytes += lli->len;
  782. } else if (!pchan || !pchan->desc) {
  783. bytes = 0;
  784. } else {
  785. bytes = sun6i_get_chan_size(pchan);
  786. }
  787. spin_unlock_irqrestore(&vchan->vc.lock, flags);
  788. dma_set_residue(state, bytes);
  789. return ret;
  790. }
  791. static void sun6i_dma_issue_pending(struct dma_chan *chan)
  792. {
  793. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  794. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  795. unsigned long flags;
  796. spin_lock_irqsave(&vchan->vc.lock, flags);
  797. if (vchan_issue_pending(&vchan->vc)) {
  798. spin_lock(&sdev->lock);
  799. if (!vchan->phy && list_empty(&vchan->node)) {
  800. list_add_tail(&vchan->node, &sdev->pending);
  801. tasklet_schedule(&sdev->task);
  802. dev_dbg(chan2dev(chan), "vchan %p: issued\n",
  803. &vchan->vc);
  804. }
  805. spin_unlock(&sdev->lock);
  806. } else {
  807. dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
  808. &vchan->vc);
  809. }
  810. spin_unlock_irqrestore(&vchan->vc.lock, flags);
  811. }
  812. static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
  813. {
  814. struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
  815. struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
  816. unsigned long flags;
  817. spin_lock_irqsave(&sdev->lock, flags);
  818. list_del_init(&vchan->node);
  819. spin_unlock_irqrestore(&sdev->lock, flags);
  820. vchan_free_chan_resources(&vchan->vc);
  821. }
  822. static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
  823. struct of_dma *ofdma)
  824. {
  825. struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
  826. struct sun6i_vchan *vchan;
  827. struct dma_chan *chan;
  828. u8 port = dma_spec->args[0];
  829. if (port > sdev->max_request)
  830. return NULL;
  831. chan = dma_get_any_slave_channel(&sdev->slave);
  832. if (!chan)
  833. return NULL;
  834. vchan = to_sun6i_vchan(chan);
  835. vchan->port = port;
  836. return chan;
  837. }
  838. static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
  839. {
  840. /* Disable all interrupts from DMA */
  841. writel(0, sdev->base + DMA_IRQ_EN(0));
  842. writel(0, sdev->base + DMA_IRQ_EN(1));
  843. /* Prevent spurious interrupts from scheduling the tasklet */
  844. atomic_inc(&sdev->tasklet_shutdown);
  845. /* Make sure we won't have any further interrupts */
  846. devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
  847. /* Actually prevent the tasklet from being scheduled */
  848. tasklet_kill(&sdev->task);
  849. }
  850. static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
  851. {
  852. int i;
  853. for (i = 0; i < sdev->num_vchans; i++) {
  854. struct sun6i_vchan *vchan = &sdev->vchans[i];
  855. list_del(&vchan->vc.chan.device_node);
  856. tasklet_kill(&vchan->vc.task);
  857. }
  858. }
  859. /*
  860. * For A31:
  861. *
  862. * There's 16 physical channels that can work in parallel.
  863. *
  864. * However we have 30 different endpoints for our requests.
  865. *
  866. * Since the channels are able to handle only an unidirectional
  867. * transfer, we need to allocate more virtual channels so that
  868. * everyone can grab one channel.
  869. *
  870. * Some devices can't work in both direction (mostly because it
  871. * wouldn't make sense), so we have a bit fewer virtual channels than
  872. * 2 channels per endpoints.
  873. */
  874. static struct sun6i_dma_config sun6i_a31_dma_cfg = {
  875. .nr_max_channels = 16,
  876. .nr_max_requests = 30,
  877. .nr_max_vchans = 53,
  878. .set_burst_length = sun6i_set_burst_length_a31,
  879. .set_drq = sun6i_set_drq_a31,
  880. .set_mode = sun6i_set_mode_a31,
  881. .src_burst_lengths = BIT(1) | BIT(8),
  882. .dst_burst_lengths = BIT(1) | BIT(8),
  883. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  884. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  885. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  886. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  887. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  888. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  889. };
  890. /*
  891. * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
  892. * and a total of 37 usable source and destination endpoints.
  893. */
  894. static struct sun6i_dma_config sun8i_a23_dma_cfg = {
  895. .nr_max_channels = 8,
  896. .nr_max_requests = 24,
  897. .nr_max_vchans = 37,
  898. .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
  899. .set_burst_length = sun6i_set_burst_length_a31,
  900. .set_drq = sun6i_set_drq_a31,
  901. .set_mode = sun6i_set_mode_a31,
  902. .src_burst_lengths = BIT(1) | BIT(8),
  903. .dst_burst_lengths = BIT(1) | BIT(8),
  904. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  905. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  906. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  907. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  908. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  909. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  910. };
  911. static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
  912. .nr_max_channels = 8,
  913. .nr_max_requests = 28,
  914. .nr_max_vchans = 39,
  915. .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
  916. .set_burst_length = sun6i_set_burst_length_a31,
  917. .set_drq = sun6i_set_drq_a31,
  918. .set_mode = sun6i_set_mode_a31,
  919. .src_burst_lengths = BIT(1) | BIT(8),
  920. .dst_burst_lengths = BIT(1) | BIT(8),
  921. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  922. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  923. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  924. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  925. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  926. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  927. };
  928. /*
  929. * The H3 has 12 physical channels, a maximum DRQ port id of 27,
  930. * and a total of 34 usable source and destination endpoints.
  931. * It also supports additional burst lengths and bus widths,
  932. * and the burst length fields have different offsets.
  933. */
  934. static struct sun6i_dma_config sun8i_h3_dma_cfg = {
  935. .nr_max_channels = 12,
  936. .nr_max_requests = 27,
  937. .nr_max_vchans = 34,
  938. .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
  939. .set_burst_length = sun6i_set_burst_length_h3,
  940. .set_drq = sun6i_set_drq_a31,
  941. .set_mode = sun6i_set_mode_a31,
  942. .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  943. .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  944. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  945. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  946. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  947. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  948. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  949. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  950. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  951. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  952. };
  953. /*
  954. * The A64 binding uses the number of dma channels from the
  955. * device tree node.
  956. */
  957. static struct sun6i_dma_config sun50i_a64_dma_cfg = {
  958. .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
  959. .set_burst_length = sun6i_set_burst_length_h3,
  960. .set_drq = sun6i_set_drq_a31,
  961. .set_mode = sun6i_set_mode_a31,
  962. .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  963. .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  964. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  965. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  966. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  967. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  968. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  969. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  970. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  971. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  972. };
  973. /*
  974. * The H6 binding uses the number of dma channels from the
  975. * device tree node.
  976. */
  977. static struct sun6i_dma_config sun50i_h6_dma_cfg = {
  978. .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
  979. .set_burst_length = sun6i_set_burst_length_h3,
  980. .set_drq = sun6i_set_drq_h6,
  981. .set_mode = sun6i_set_mode_h6,
  982. .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  983. .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
  984. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  985. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  986. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  987. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  988. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  989. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  990. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  991. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
  992. .has_mbus_clk = true,
  993. };
  994. /*
  995. * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
  996. * and a total of 24 usable source and destination endpoints.
  997. */
  998. static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
  999. .nr_max_channels = 8,
  1000. .nr_max_requests = 23,
  1001. .nr_max_vchans = 24,
  1002. .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
  1003. .set_burst_length = sun6i_set_burst_length_a31,
  1004. .set_drq = sun6i_set_drq_a31,
  1005. .set_mode = sun6i_set_mode_a31,
  1006. .src_burst_lengths = BIT(1) | BIT(8),
  1007. .dst_burst_lengths = BIT(1) | BIT(8),
  1008. .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  1009. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  1010. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  1011. .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  1012. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  1013. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
  1014. };
  1015. static const struct of_device_id sun6i_dma_match[] = {
  1016. { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
  1017. { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
  1018. { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
  1019. { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
  1020. { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
  1021. { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
  1022. { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
  1023. { /* sentinel */ }
  1024. };
  1025. MODULE_DEVICE_TABLE(of, sun6i_dma_match);
  1026. static int sun6i_dma_probe(struct platform_device *pdev)
  1027. {
  1028. struct device_node *np = pdev->dev.of_node;
  1029. struct sun6i_dma_dev *sdc;
  1030. struct resource *res;
  1031. int ret, i;
  1032. sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
  1033. if (!sdc)
  1034. return -ENOMEM;
  1035. sdc->cfg = of_device_get_match_data(&pdev->dev);
  1036. if (!sdc->cfg)
  1037. return -ENODEV;
  1038. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1039. sdc->base = devm_ioremap_resource(&pdev->dev, res);
  1040. if (IS_ERR(sdc->base))
  1041. return PTR_ERR(sdc->base);
  1042. sdc->irq = platform_get_irq(pdev, 0);
  1043. if (sdc->irq < 0)
  1044. return sdc->irq;
  1045. sdc->clk = devm_clk_get(&pdev->dev, NULL);
  1046. if (IS_ERR(sdc->clk)) {
  1047. dev_err(&pdev->dev, "No clock specified\n");
  1048. return PTR_ERR(sdc->clk);
  1049. }
  1050. if (sdc->cfg->has_mbus_clk) {
  1051. sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
  1052. if (IS_ERR(sdc->clk_mbus)) {
  1053. dev_err(&pdev->dev, "No mbus clock specified\n");
  1054. return PTR_ERR(sdc->clk_mbus);
  1055. }
  1056. }
  1057. sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
  1058. if (IS_ERR(sdc->rstc)) {
  1059. dev_err(&pdev->dev, "No reset controller specified\n");
  1060. return PTR_ERR(sdc->rstc);
  1061. }
  1062. sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
  1063. sizeof(struct sun6i_dma_lli), 4, 0);
  1064. if (!sdc->pool) {
  1065. dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
  1066. return -ENOMEM;
  1067. }
  1068. platform_set_drvdata(pdev, sdc);
  1069. INIT_LIST_HEAD(&sdc->pending);
  1070. spin_lock_init(&sdc->lock);
  1071. dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
  1072. dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
  1073. dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
  1074. dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
  1075. INIT_LIST_HEAD(&sdc->slave.channels);
  1076. sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources;
  1077. sdc->slave.device_tx_status = sun6i_dma_tx_status;
  1078. sdc->slave.device_issue_pending = sun6i_dma_issue_pending;
  1079. sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg;
  1080. sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
  1081. sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic;
  1082. sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES;
  1083. sdc->slave.device_config = sun6i_dma_config;
  1084. sdc->slave.device_pause = sun6i_dma_pause;
  1085. sdc->slave.device_resume = sun6i_dma_resume;
  1086. sdc->slave.device_terminate_all = sun6i_dma_terminate_all;
  1087. sdc->slave.src_addr_widths = sdc->cfg->src_addr_widths;
  1088. sdc->slave.dst_addr_widths = sdc->cfg->dst_addr_widths;
  1089. sdc->slave.directions = BIT(DMA_DEV_TO_MEM) |
  1090. BIT(DMA_MEM_TO_DEV);
  1091. sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  1092. sdc->slave.dev = &pdev->dev;
  1093. sdc->num_pchans = sdc->cfg->nr_max_channels;
  1094. sdc->num_vchans = sdc->cfg->nr_max_vchans;
  1095. sdc->max_request = sdc->cfg->nr_max_requests;
  1096. ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans);
  1097. if (ret && !sdc->num_pchans) {
  1098. dev_err(&pdev->dev, "Can't get dma-channels.\n");
  1099. return ret;
  1100. }
  1101. ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
  1102. if (ret && !sdc->max_request) {
  1103. dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
  1104. DMA_CHAN_MAX_DRQ_A31);
  1105. sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
  1106. }
  1107. /*
  1108. * If the number of vchans is not specified, derive it from the
  1109. * highest port number, at most one channel per port and direction.
  1110. */
  1111. if (!sdc->num_vchans)
  1112. sdc->num_vchans = 2 * (sdc->max_request + 1);
  1113. sdc->pchans = devm_kcalloc(&pdev->dev, sdc->num_pchans,
  1114. sizeof(struct sun6i_pchan), GFP_KERNEL);
  1115. if (!sdc->pchans)
  1116. return -ENOMEM;
  1117. sdc->vchans = devm_kcalloc(&pdev->dev, sdc->num_vchans,
  1118. sizeof(struct sun6i_vchan), GFP_KERNEL);
  1119. if (!sdc->vchans)
  1120. return -ENOMEM;
  1121. tasklet_setup(&sdc->task, sun6i_dma_tasklet);
  1122. for (i = 0; i < sdc->num_pchans; i++) {
  1123. struct sun6i_pchan *pchan = &sdc->pchans[i];
  1124. pchan->idx = i;
  1125. pchan->base = sdc->base + 0x100 + i * 0x40;
  1126. }
  1127. for (i = 0; i < sdc->num_vchans; i++) {
  1128. struct sun6i_vchan *vchan = &sdc->vchans[i];
  1129. INIT_LIST_HEAD(&vchan->node);
  1130. vchan->vc.desc_free = sun6i_dma_free_desc;
  1131. vchan_init(&vchan->vc, &sdc->slave);
  1132. }
  1133. ret = reset_control_deassert(sdc->rstc);
  1134. if (ret) {
  1135. dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
  1136. goto err_chan_free;
  1137. }
  1138. ret = clk_prepare_enable(sdc->clk);
  1139. if (ret) {
  1140. dev_err(&pdev->dev, "Couldn't enable the clock\n");
  1141. goto err_reset_assert;
  1142. }
  1143. if (sdc->cfg->has_mbus_clk) {
  1144. ret = clk_prepare_enable(sdc->clk_mbus);
  1145. if (ret) {
  1146. dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
  1147. goto err_clk_disable;
  1148. }
  1149. }
  1150. ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
  1151. dev_name(&pdev->dev), sdc);
  1152. if (ret) {
  1153. dev_err(&pdev->dev, "Cannot request IRQ\n");
  1154. goto err_mbus_clk_disable;
  1155. }
  1156. ret = dma_async_device_register(&sdc->slave);
  1157. if (ret) {
  1158. dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
  1159. goto err_irq_disable;
  1160. }
  1161. ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
  1162. sdc);
  1163. if (ret) {
  1164. dev_err(&pdev->dev, "of_dma_controller_register failed\n");
  1165. goto err_dma_unregister;
  1166. }
  1167. if (sdc->cfg->clock_autogate_enable)
  1168. sdc->cfg->clock_autogate_enable(sdc);
  1169. return 0;
  1170. err_dma_unregister:
  1171. dma_async_device_unregister(&sdc->slave);
  1172. err_irq_disable:
  1173. sun6i_kill_tasklet(sdc);
  1174. err_mbus_clk_disable:
  1175. clk_disable_unprepare(sdc->clk_mbus);
  1176. err_clk_disable:
  1177. clk_disable_unprepare(sdc->clk);
  1178. err_reset_assert:
  1179. reset_control_assert(sdc->rstc);
  1180. err_chan_free:
  1181. sun6i_dma_free(sdc);
  1182. return ret;
  1183. }
  1184. static int sun6i_dma_remove(struct platform_device *pdev)
  1185. {
  1186. struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
  1187. of_dma_controller_free(pdev->dev.of_node);
  1188. dma_async_device_unregister(&sdc->slave);
  1189. sun6i_kill_tasklet(sdc);
  1190. clk_disable_unprepare(sdc->clk_mbus);
  1191. clk_disable_unprepare(sdc->clk);
  1192. reset_control_assert(sdc->rstc);
  1193. sun6i_dma_free(sdc);
  1194. return 0;
  1195. }
  1196. static struct platform_driver sun6i_dma_driver = {
  1197. .probe = sun6i_dma_probe,
  1198. .remove = sun6i_dma_remove,
  1199. .driver = {
  1200. .name = "sun6i-dma",
  1201. .of_match_table = sun6i_dma_match,
  1202. },
  1203. };
  1204. module_platform_driver(sun6i_dma_driver);
  1205. MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
  1206. MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
  1207. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  1208. MODULE_LICENSE("GPL");