ste_dma40.c 96 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) Ericsson AB 2007-2008
  4. * Copyright (C) ST-Ericsson SA 2008-2010
  5. * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
  6. * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/export.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/log2.h>
  17. #include <linux/pm.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/err.h>
  20. #include <linux/of.h>
  21. #include <linux/of_dma.h>
  22. #include <linux/amba/bus.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/platform_data/dma-ste-dma40.h>
  25. #include "dmaengine.h"
  26. #include "ste_dma40_ll.h"
  27. #define D40_NAME "dma40"
  28. #define D40_PHY_CHAN -1
  29. /* For masking out/in 2 bit channel positions */
  30. #define D40_CHAN_POS(chan) (2 * (chan / 2))
  31. #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  32. /* Maximum iterations taken before giving up suspending a channel */
  33. #define D40_SUSPEND_MAX_IT 500
  34. /* Milliseconds */
  35. #define DMA40_AUTOSUSPEND_DELAY 100
  36. /* Hardware requirement on LCLA alignment */
  37. #define LCLA_ALIGNMENT 0x40000
  38. /* Max number of links per event group */
  39. #define D40_LCLA_LINK_PER_EVENT_GRP 128
  40. #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  41. /* Max number of logical channels per physical channel */
  42. #define D40_MAX_LOG_CHAN_PER_PHY 32
  43. /* Attempts before giving up to trying to get pages that are aligned */
  44. #define MAX_LCLA_ALLOC_ATTEMPTS 256
  45. /* Bit markings for allocation map */
  46. #define D40_ALLOC_FREE BIT(31)
  47. #define D40_ALLOC_PHY BIT(30)
  48. #define D40_ALLOC_LOG_FREE 0
  49. #define D40_MEMCPY_MAX_CHANS 8
  50. /* Reserved event lines for memcpy only. */
  51. #define DB8500_DMA_MEMCPY_EV_0 51
  52. #define DB8500_DMA_MEMCPY_EV_1 56
  53. #define DB8500_DMA_MEMCPY_EV_2 57
  54. #define DB8500_DMA_MEMCPY_EV_3 58
  55. #define DB8500_DMA_MEMCPY_EV_4 59
  56. #define DB8500_DMA_MEMCPY_EV_5 60
  57. static int dma40_memcpy_channels[] = {
  58. DB8500_DMA_MEMCPY_EV_0,
  59. DB8500_DMA_MEMCPY_EV_1,
  60. DB8500_DMA_MEMCPY_EV_2,
  61. DB8500_DMA_MEMCPY_EV_3,
  62. DB8500_DMA_MEMCPY_EV_4,
  63. DB8500_DMA_MEMCPY_EV_5,
  64. };
  65. /* Default configuration for physcial memcpy */
  66. static const struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  67. .mode = STEDMA40_MODE_PHYSICAL,
  68. .dir = DMA_MEM_TO_MEM,
  69. .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  70. .src_info.psize = STEDMA40_PSIZE_PHY_1,
  71. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  72. .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  73. .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  74. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  75. };
  76. /* Default configuration for logical memcpy */
  77. static const struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  78. .mode = STEDMA40_MODE_LOGICAL,
  79. .dir = DMA_MEM_TO_MEM,
  80. .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  81. .src_info.psize = STEDMA40_PSIZE_LOG_1,
  82. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  83. .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  84. .dst_info.psize = STEDMA40_PSIZE_LOG_1,
  85. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  86. };
  87. /**
  88. * enum 40_command - The different commands and/or statuses.
  89. *
  90. * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
  91. * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
  92. * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
  93. * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
  94. */
  95. enum d40_command {
  96. D40_DMA_STOP = 0,
  97. D40_DMA_RUN = 1,
  98. D40_DMA_SUSPEND_REQ = 2,
  99. D40_DMA_SUSPENDED = 3
  100. };
  101. /*
  102. * enum d40_events - The different Event Enables for the event lines.
  103. *
  104. * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
  105. * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
  106. * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
  107. * @D40_ROUND_EVENTLINE: Status check for event line.
  108. */
  109. enum d40_events {
  110. D40_DEACTIVATE_EVENTLINE = 0,
  111. D40_ACTIVATE_EVENTLINE = 1,
  112. D40_SUSPEND_REQ_EVENTLINE = 2,
  113. D40_ROUND_EVENTLINE = 3
  114. };
  115. /*
  116. * These are the registers that has to be saved and later restored
  117. * when the DMA hw is powered off.
  118. * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
  119. */
  120. static __maybe_unused u32 d40_backup_regs[] = {
  121. D40_DREG_LCPA,
  122. D40_DREG_LCLA,
  123. D40_DREG_PRMSE,
  124. D40_DREG_PRMSO,
  125. D40_DREG_PRMOE,
  126. D40_DREG_PRMOO,
  127. };
  128. #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
  129. /*
  130. * since 9540 and 8540 has the same HW revision
  131. * use v4a for 9540 or ealier
  132. * use v4b for 8540 or later
  133. * HW revision:
  134. * DB8500ed has revision 0
  135. * DB8500v1 has revision 2
  136. * DB8500v2 has revision 3
  137. * AP9540v1 has revision 4
  138. * DB8540v1 has revision 4
  139. * TODO: Check if all these registers have to be saved/restored on dma40 v4a
  140. */
  141. static u32 d40_backup_regs_v4a[] = {
  142. D40_DREG_PSEG1,
  143. D40_DREG_PSEG2,
  144. D40_DREG_PSEG3,
  145. D40_DREG_PSEG4,
  146. D40_DREG_PCEG1,
  147. D40_DREG_PCEG2,
  148. D40_DREG_PCEG3,
  149. D40_DREG_PCEG4,
  150. D40_DREG_RSEG1,
  151. D40_DREG_RSEG2,
  152. D40_DREG_RSEG3,
  153. D40_DREG_RSEG4,
  154. D40_DREG_RCEG1,
  155. D40_DREG_RCEG2,
  156. D40_DREG_RCEG3,
  157. D40_DREG_RCEG4,
  158. };
  159. #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
  160. static u32 d40_backup_regs_v4b[] = {
  161. D40_DREG_CPSEG1,
  162. D40_DREG_CPSEG2,
  163. D40_DREG_CPSEG3,
  164. D40_DREG_CPSEG4,
  165. D40_DREG_CPSEG5,
  166. D40_DREG_CPCEG1,
  167. D40_DREG_CPCEG2,
  168. D40_DREG_CPCEG3,
  169. D40_DREG_CPCEG4,
  170. D40_DREG_CPCEG5,
  171. D40_DREG_CRSEG1,
  172. D40_DREG_CRSEG2,
  173. D40_DREG_CRSEG3,
  174. D40_DREG_CRSEG4,
  175. D40_DREG_CRSEG5,
  176. D40_DREG_CRCEG1,
  177. D40_DREG_CRCEG2,
  178. D40_DREG_CRCEG3,
  179. D40_DREG_CRCEG4,
  180. D40_DREG_CRCEG5,
  181. };
  182. #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
  183. static __maybe_unused u32 d40_backup_regs_chan[] = {
  184. D40_CHAN_REG_SSCFG,
  185. D40_CHAN_REG_SSELT,
  186. D40_CHAN_REG_SSPTR,
  187. D40_CHAN_REG_SSLNK,
  188. D40_CHAN_REG_SDCFG,
  189. D40_CHAN_REG_SDELT,
  190. D40_CHAN_REG_SDPTR,
  191. D40_CHAN_REG_SDLNK,
  192. };
  193. #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
  194. BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
  195. /**
  196. * struct d40_interrupt_lookup - lookup table for interrupt handler
  197. *
  198. * @src: Interrupt mask register.
  199. * @clr: Interrupt clear register.
  200. * @is_error: true if this is an error interrupt.
  201. * @offset: start delta in the lookup_log_chans in d40_base. If equals to
  202. * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
  203. */
  204. struct d40_interrupt_lookup {
  205. u32 src;
  206. u32 clr;
  207. bool is_error;
  208. int offset;
  209. };
  210. static struct d40_interrupt_lookup il_v4a[] = {
  211. {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
  212. {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
  213. {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
  214. {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
  215. {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
  216. {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
  217. {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
  218. {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
  219. {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
  220. {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
  221. };
  222. static struct d40_interrupt_lookup il_v4b[] = {
  223. {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
  224. {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
  225. {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
  226. {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
  227. {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
  228. {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
  229. {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
  230. {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
  231. {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
  232. {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
  233. {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
  234. {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
  235. };
  236. /**
  237. * struct d40_reg_val - simple lookup struct
  238. *
  239. * @reg: The register.
  240. * @val: The value that belongs to the register in reg.
  241. */
  242. struct d40_reg_val {
  243. unsigned int reg;
  244. unsigned int val;
  245. };
  246. static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
  247. /* Clock every part of the DMA block from start */
  248. { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
  249. /* Interrupts on all logical channels */
  250. { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
  251. { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
  252. { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
  253. { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
  254. { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
  255. { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
  256. { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
  257. { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
  258. { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
  259. { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
  260. { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
  261. { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
  262. };
  263. static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
  264. /* Clock every part of the DMA block from start */
  265. { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
  266. /* Interrupts on all logical channels */
  267. { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
  268. { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
  269. { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
  270. { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
  271. { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
  272. { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
  273. { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
  274. { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
  275. { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
  276. { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
  277. { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
  278. { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
  279. { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
  280. { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
  281. { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
  282. };
  283. /**
  284. * struct d40_lli_pool - Structure for keeping LLIs in memory
  285. *
  286. * @base: Pointer to memory area when the pre_alloc_lli's are not large
  287. * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
  288. * pre_alloc_lli is used.
  289. * @dma_addr: DMA address, if mapped
  290. * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
  291. * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
  292. * one buffer to one buffer.
  293. */
  294. struct d40_lli_pool {
  295. void *base;
  296. int size;
  297. dma_addr_t dma_addr;
  298. /* Space for dst and src, plus an extra for padding */
  299. u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
  300. };
  301. /**
  302. * struct d40_desc - A descriptor is one DMA job.
  303. *
  304. * @lli_phy: LLI settings for physical channel. Both src and dst=
  305. * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
  306. * lli_len equals one.
  307. * @lli_log: Same as above but for logical channels.
  308. * @lli_pool: The pool with two entries pre-allocated.
  309. * @lli_len: Number of llis of current descriptor.
  310. * @lli_current: Number of transferred llis.
  311. * @lcla_alloc: Number of LCLA entries allocated.
  312. * @txd: DMA engine struct. Used for among other things for communication
  313. * during a transfer.
  314. * @node: List entry.
  315. * @is_in_client_list: true if the client owns this descriptor.
  316. * @cyclic: true if this is a cyclic job
  317. *
  318. * This descriptor is used for both logical and physical transfers.
  319. */
  320. struct d40_desc {
  321. /* LLI physical */
  322. struct d40_phy_lli_bidir lli_phy;
  323. /* LLI logical */
  324. struct d40_log_lli_bidir lli_log;
  325. struct d40_lli_pool lli_pool;
  326. int lli_len;
  327. int lli_current;
  328. int lcla_alloc;
  329. struct dma_async_tx_descriptor txd;
  330. struct list_head node;
  331. bool is_in_client_list;
  332. bool cyclic;
  333. };
  334. /**
  335. * struct d40_lcla_pool - LCLA pool settings and data.
  336. *
  337. * @base: The virtual address of LCLA. 18 bit aligned.
  338. * @dma_addr: DMA address, if mapped
  339. * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
  340. * This pointer is only there for clean-up on error.
  341. * @pages: The number of pages needed for all physical channels.
  342. * Only used later for clean-up on error
  343. * @lock: Lock to protect the content in this struct.
  344. * @alloc_map: big map over which LCLA entry is own by which job.
  345. */
  346. struct d40_lcla_pool {
  347. void *base;
  348. dma_addr_t dma_addr;
  349. void *base_unaligned;
  350. int pages;
  351. spinlock_t lock;
  352. struct d40_desc **alloc_map;
  353. };
  354. /**
  355. * struct d40_phy_res - struct for handling eventlines mapped to physical
  356. * channels.
  357. *
  358. * @lock: A lock protection this entity.
  359. * @reserved: True if used by secure world or otherwise.
  360. * @num: The physical channel number of this entity.
  361. * @allocated_src: Bit mapped to show which src event line's are mapped to
  362. * this physical channel. Can also be free or physically allocated.
  363. * @allocated_dst: Same as for src but is dst.
  364. * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
  365. * event line number.
  366. * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
  367. */
  368. struct d40_phy_res {
  369. spinlock_t lock;
  370. bool reserved;
  371. int num;
  372. u32 allocated_src;
  373. u32 allocated_dst;
  374. bool use_soft_lli;
  375. };
  376. struct d40_base;
  377. /**
  378. * struct d40_chan - Struct that describes a channel.
  379. *
  380. * @lock: A spinlock to protect this struct.
  381. * @log_num: The logical number, if any of this channel.
  382. * @pending_tx: The number of pending transfers. Used between interrupt handler
  383. * and tasklet.
  384. * @busy: Set to true when transfer is ongoing on this channel.
  385. * @phy_chan: Pointer to physical channel which this instance runs on. If this
  386. * point is NULL, then the channel is not allocated.
  387. * @chan: DMA engine handle.
  388. * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
  389. * transfer and call client callback.
  390. * @client: Cliented owned descriptor list.
  391. * @pending_queue: Submitted jobs, to be issued by issue_pending()
  392. * @active: Active descriptor.
  393. * @done: Completed jobs
  394. * @queue: Queued jobs.
  395. * @prepare_queue: Prepared jobs.
  396. * @dma_cfg: The client configuration of this dma channel.
  397. * @slave_config: DMA slave configuration.
  398. * @configured: whether the dma_cfg configuration is valid
  399. * @base: Pointer to the device instance struct.
  400. * @src_def_cfg: Default cfg register setting for src.
  401. * @dst_def_cfg: Default cfg register setting for dst.
  402. * @log_def: Default logical channel settings.
  403. * @lcpa: Pointer to dst and src lcpa settings.
  404. * @runtime_addr: runtime configured address.
  405. * @runtime_direction: runtime configured direction.
  406. *
  407. * This struct can either "be" a logical or a physical channel.
  408. */
  409. struct d40_chan {
  410. spinlock_t lock;
  411. int log_num;
  412. int pending_tx;
  413. bool busy;
  414. struct d40_phy_res *phy_chan;
  415. struct dma_chan chan;
  416. struct tasklet_struct tasklet;
  417. struct list_head client;
  418. struct list_head pending_queue;
  419. struct list_head active;
  420. struct list_head done;
  421. struct list_head queue;
  422. struct list_head prepare_queue;
  423. struct stedma40_chan_cfg dma_cfg;
  424. struct dma_slave_config slave_config;
  425. bool configured;
  426. struct d40_base *base;
  427. /* Default register configurations */
  428. u32 src_def_cfg;
  429. u32 dst_def_cfg;
  430. struct d40_def_lcsp log_def;
  431. struct d40_log_lli_full *lcpa;
  432. /* Runtime reconfiguration */
  433. dma_addr_t runtime_addr;
  434. enum dma_transfer_direction runtime_direction;
  435. };
  436. /**
  437. * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
  438. * controller
  439. *
  440. * @backup: the pointer to the registers address array for backup
  441. * @backup_size: the size of the registers address array for backup
  442. * @realtime_en: the realtime enable register
  443. * @realtime_clear: the realtime clear register
  444. * @high_prio_en: the high priority enable register
  445. * @high_prio_clear: the high priority clear register
  446. * @interrupt_en: the interrupt enable register
  447. * @interrupt_clear: the interrupt clear register
  448. * @il: the pointer to struct d40_interrupt_lookup
  449. * @il_size: the size of d40_interrupt_lookup array
  450. * @init_reg: the pointer to the struct d40_reg_val
  451. * @init_reg_size: the size of d40_reg_val array
  452. */
  453. struct d40_gen_dmac {
  454. u32 *backup;
  455. u32 backup_size;
  456. u32 realtime_en;
  457. u32 realtime_clear;
  458. u32 high_prio_en;
  459. u32 high_prio_clear;
  460. u32 interrupt_en;
  461. u32 interrupt_clear;
  462. struct d40_interrupt_lookup *il;
  463. u32 il_size;
  464. struct d40_reg_val *init_reg;
  465. u32 init_reg_size;
  466. };
  467. /**
  468. * struct d40_base - The big global struct, one for each probe'd instance.
  469. *
  470. * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
  471. * @execmd_lock: Lock for execute command usage since several channels share
  472. * the same physical register.
  473. * @dev: The device structure.
  474. * @virtbase: The virtual base address of the DMA's register.
  475. * @rev: silicon revision detected.
  476. * @clk: Pointer to the DMA clock structure.
  477. * @phy_start: Physical memory start of the DMA registers.
  478. * @phy_size: Size of the DMA register map.
  479. * @irq: The IRQ number.
  480. * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
  481. * transfers).
  482. * @num_phy_chans: The number of physical channels. Read from HW. This
  483. * is the number of available channels for this driver, not counting "Secure
  484. * mode" allocated physical channels.
  485. * @num_log_chans: The number of logical channels. Calculated from
  486. * num_phy_chans.
  487. * @dma_both: dma_device channels that can do both memcpy and slave transfers.
  488. * @dma_slave: dma_device channels that can do only do slave transfers.
  489. * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
  490. * @phy_chans: Room for all possible physical channels in system.
  491. * @log_chans: Room for all possible logical channels in system.
  492. * @lookup_log_chans: Used to map interrupt number to logical channel. Points
  493. * to log_chans entries.
  494. * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
  495. * to phy_chans entries.
  496. * @plat_data: Pointer to provided platform_data which is the driver
  497. * configuration.
  498. * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
  499. * @phy_res: Vector containing all physical channels.
  500. * @lcla_pool: lcla pool settings and data.
  501. * @lcpa_base: The virtual mapped address of LCPA.
  502. * @phy_lcpa: The physical address of the LCPA.
  503. * @lcpa_size: The size of the LCPA area.
  504. * @desc_slab: cache for descriptors.
  505. * @reg_val_backup: Here the values of some hardware registers are stored
  506. * before the DMA is powered off. They are restored when the power is back on.
  507. * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
  508. * later
  509. * @reg_val_backup_chan: Backup data for standard channel parameter registers.
  510. * @regs_interrupt: Scratch space for registers during interrupt.
  511. * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
  512. * @gen_dmac: the struct for generic registers values to represent u8500/8540
  513. * DMA controller
  514. */
  515. struct d40_base {
  516. spinlock_t interrupt_lock;
  517. spinlock_t execmd_lock;
  518. struct device *dev;
  519. void __iomem *virtbase;
  520. u8 rev:4;
  521. struct clk *clk;
  522. phys_addr_t phy_start;
  523. resource_size_t phy_size;
  524. int irq;
  525. int num_memcpy_chans;
  526. int num_phy_chans;
  527. int num_log_chans;
  528. struct dma_device dma_both;
  529. struct dma_device dma_slave;
  530. struct dma_device dma_memcpy;
  531. struct d40_chan *phy_chans;
  532. struct d40_chan *log_chans;
  533. struct d40_chan **lookup_log_chans;
  534. struct d40_chan **lookup_phy_chans;
  535. struct stedma40_platform_data *plat_data;
  536. struct regulator *lcpa_regulator;
  537. /* Physical half channels */
  538. struct d40_phy_res *phy_res;
  539. struct d40_lcla_pool lcla_pool;
  540. void *lcpa_base;
  541. dma_addr_t phy_lcpa;
  542. resource_size_t lcpa_size;
  543. struct kmem_cache *desc_slab;
  544. u32 reg_val_backup[BACKUP_REGS_SZ];
  545. u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
  546. u32 *reg_val_backup_chan;
  547. u32 *regs_interrupt;
  548. u16 gcc_pwr_off_mask;
  549. struct d40_gen_dmac gen_dmac;
  550. };
  551. static struct device *chan2dev(struct d40_chan *d40c)
  552. {
  553. return &d40c->chan.dev->device;
  554. }
  555. static bool chan_is_physical(struct d40_chan *chan)
  556. {
  557. return chan->log_num == D40_PHY_CHAN;
  558. }
  559. static bool chan_is_logical(struct d40_chan *chan)
  560. {
  561. return !chan_is_physical(chan);
  562. }
  563. static void __iomem *chan_base(struct d40_chan *chan)
  564. {
  565. return chan->base->virtbase + D40_DREG_PCBASE +
  566. chan->phy_chan->num * D40_DREG_PCDELTA;
  567. }
  568. #define d40_err(dev, format, arg...) \
  569. dev_err(dev, "[%s] " format, __func__, ## arg)
  570. #define chan_err(d40c, format, arg...) \
  571. d40_err(chan2dev(d40c), format, ## arg)
  572. static int d40_set_runtime_config_write(struct dma_chan *chan,
  573. struct dma_slave_config *config,
  574. enum dma_transfer_direction direction);
  575. static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
  576. int lli_len)
  577. {
  578. bool is_log = chan_is_logical(d40c);
  579. u32 align;
  580. void *base;
  581. if (is_log)
  582. align = sizeof(struct d40_log_lli);
  583. else
  584. align = sizeof(struct d40_phy_lli);
  585. if (lli_len == 1) {
  586. base = d40d->lli_pool.pre_alloc_lli;
  587. d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
  588. d40d->lli_pool.base = NULL;
  589. } else {
  590. d40d->lli_pool.size = lli_len * 2 * align;
  591. base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
  592. d40d->lli_pool.base = base;
  593. if (d40d->lli_pool.base == NULL)
  594. return -ENOMEM;
  595. }
  596. if (is_log) {
  597. d40d->lli_log.src = PTR_ALIGN(base, align);
  598. d40d->lli_log.dst = d40d->lli_log.src + lli_len;
  599. d40d->lli_pool.dma_addr = 0;
  600. } else {
  601. d40d->lli_phy.src = PTR_ALIGN(base, align);
  602. d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
  603. d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
  604. d40d->lli_phy.src,
  605. d40d->lli_pool.size,
  606. DMA_TO_DEVICE);
  607. if (dma_mapping_error(d40c->base->dev,
  608. d40d->lli_pool.dma_addr)) {
  609. kfree(d40d->lli_pool.base);
  610. d40d->lli_pool.base = NULL;
  611. d40d->lli_pool.dma_addr = 0;
  612. return -ENOMEM;
  613. }
  614. }
  615. return 0;
  616. }
  617. static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
  618. {
  619. if (d40d->lli_pool.dma_addr)
  620. dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
  621. d40d->lli_pool.size, DMA_TO_DEVICE);
  622. kfree(d40d->lli_pool.base);
  623. d40d->lli_pool.base = NULL;
  624. d40d->lli_pool.size = 0;
  625. d40d->lli_log.src = NULL;
  626. d40d->lli_log.dst = NULL;
  627. d40d->lli_phy.src = NULL;
  628. d40d->lli_phy.dst = NULL;
  629. }
  630. static int d40_lcla_alloc_one(struct d40_chan *d40c,
  631. struct d40_desc *d40d)
  632. {
  633. unsigned long flags;
  634. int i;
  635. int ret = -EINVAL;
  636. spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
  637. /*
  638. * Allocate both src and dst at the same time, therefore the half
  639. * start on 1 since 0 can't be used since zero is used as end marker.
  640. */
  641. for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
  642. int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
  643. if (!d40c->base->lcla_pool.alloc_map[idx]) {
  644. d40c->base->lcla_pool.alloc_map[idx] = d40d;
  645. d40d->lcla_alloc++;
  646. ret = i;
  647. break;
  648. }
  649. }
  650. spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
  651. return ret;
  652. }
  653. static int d40_lcla_free_all(struct d40_chan *d40c,
  654. struct d40_desc *d40d)
  655. {
  656. unsigned long flags;
  657. int i;
  658. int ret = -EINVAL;
  659. if (chan_is_physical(d40c))
  660. return 0;
  661. spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
  662. for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
  663. int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
  664. if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
  665. d40c->base->lcla_pool.alloc_map[idx] = NULL;
  666. d40d->lcla_alloc--;
  667. if (d40d->lcla_alloc == 0) {
  668. ret = 0;
  669. break;
  670. }
  671. }
  672. }
  673. spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
  674. return ret;
  675. }
  676. static void d40_desc_remove(struct d40_desc *d40d)
  677. {
  678. list_del(&d40d->node);
  679. }
  680. static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
  681. {
  682. struct d40_desc *desc = NULL;
  683. if (!list_empty(&d40c->client)) {
  684. struct d40_desc *d;
  685. struct d40_desc *_d;
  686. list_for_each_entry_safe(d, _d, &d40c->client, node) {
  687. if (async_tx_test_ack(&d->txd)) {
  688. d40_desc_remove(d);
  689. desc = d;
  690. memset(desc, 0, sizeof(*desc));
  691. break;
  692. }
  693. }
  694. }
  695. if (!desc)
  696. desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
  697. if (desc)
  698. INIT_LIST_HEAD(&desc->node);
  699. return desc;
  700. }
  701. static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
  702. {
  703. d40_pool_lli_free(d40c, d40d);
  704. d40_lcla_free_all(d40c, d40d);
  705. kmem_cache_free(d40c->base->desc_slab, d40d);
  706. }
  707. static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
  708. {
  709. list_add_tail(&desc->node, &d40c->active);
  710. }
  711. static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
  712. {
  713. struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
  714. struct d40_phy_lli *lli_src = desc->lli_phy.src;
  715. void __iomem *base = chan_base(chan);
  716. writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
  717. writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
  718. writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
  719. writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
  720. writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
  721. writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
  722. writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
  723. writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
  724. }
  725. static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
  726. {
  727. list_add_tail(&desc->node, &d40c->done);
  728. }
  729. static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
  730. {
  731. struct d40_lcla_pool *pool = &chan->base->lcla_pool;
  732. struct d40_log_lli_bidir *lli = &desc->lli_log;
  733. int lli_current = desc->lli_current;
  734. int lli_len = desc->lli_len;
  735. bool cyclic = desc->cyclic;
  736. int curr_lcla = -EINVAL;
  737. int first_lcla = 0;
  738. bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
  739. bool linkback;
  740. /*
  741. * We may have partially running cyclic transfers, in case we did't get
  742. * enough LCLA entries.
  743. */
  744. linkback = cyclic && lli_current == 0;
  745. /*
  746. * For linkback, we need one LCLA even with only one link, because we
  747. * can't link back to the one in LCPA space
  748. */
  749. if (linkback || (lli_len - lli_current > 1)) {
  750. /*
  751. * If the channel is expected to use only soft_lli don't
  752. * allocate a lcla. This is to avoid a HW issue that exists
  753. * in some controller during a peripheral to memory transfer
  754. * that uses linked lists.
  755. */
  756. if (!(chan->phy_chan->use_soft_lli &&
  757. chan->dma_cfg.dir == DMA_DEV_TO_MEM))
  758. curr_lcla = d40_lcla_alloc_one(chan, desc);
  759. first_lcla = curr_lcla;
  760. }
  761. /*
  762. * For linkback, we normally load the LCPA in the loop since we need to
  763. * link it to the second LCLA and not the first. However, if we
  764. * couldn't even get a first LCLA, then we have to run in LCPA and
  765. * reload manually.
  766. */
  767. if (!linkback || curr_lcla == -EINVAL) {
  768. unsigned int flags = 0;
  769. if (curr_lcla == -EINVAL)
  770. flags |= LLI_TERM_INT;
  771. d40_log_lli_lcpa_write(chan->lcpa,
  772. &lli->dst[lli_current],
  773. &lli->src[lli_current],
  774. curr_lcla,
  775. flags);
  776. lli_current++;
  777. }
  778. if (curr_lcla < 0)
  779. goto set_current;
  780. for (; lli_current < lli_len; lli_current++) {
  781. unsigned int lcla_offset = chan->phy_chan->num * 1024 +
  782. 8 * curr_lcla * 2;
  783. struct d40_log_lli *lcla = pool->base + lcla_offset;
  784. unsigned int flags = 0;
  785. int next_lcla;
  786. if (lli_current + 1 < lli_len)
  787. next_lcla = d40_lcla_alloc_one(chan, desc);
  788. else
  789. next_lcla = linkback ? first_lcla : -EINVAL;
  790. if (cyclic || next_lcla == -EINVAL)
  791. flags |= LLI_TERM_INT;
  792. if (linkback && curr_lcla == first_lcla) {
  793. /* First link goes in both LCPA and LCLA */
  794. d40_log_lli_lcpa_write(chan->lcpa,
  795. &lli->dst[lli_current],
  796. &lli->src[lli_current],
  797. next_lcla, flags);
  798. }
  799. /*
  800. * One unused LCLA in the cyclic case if the very first
  801. * next_lcla fails...
  802. */
  803. d40_log_lli_lcla_write(lcla,
  804. &lli->dst[lli_current],
  805. &lli->src[lli_current],
  806. next_lcla, flags);
  807. /*
  808. * Cache maintenance is not needed if lcla is
  809. * mapped in esram
  810. */
  811. if (!use_esram_lcla) {
  812. dma_sync_single_range_for_device(chan->base->dev,
  813. pool->dma_addr, lcla_offset,
  814. 2 * sizeof(struct d40_log_lli),
  815. DMA_TO_DEVICE);
  816. }
  817. curr_lcla = next_lcla;
  818. if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
  819. lli_current++;
  820. break;
  821. }
  822. }
  823. set_current:
  824. desc->lli_current = lli_current;
  825. }
  826. static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
  827. {
  828. if (chan_is_physical(d40c)) {
  829. d40_phy_lli_load(d40c, d40d);
  830. d40d->lli_current = d40d->lli_len;
  831. } else
  832. d40_log_lli_to_lcxa(d40c, d40d);
  833. }
  834. static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
  835. {
  836. return list_first_entry_or_null(&d40c->active, struct d40_desc, node);
  837. }
  838. /* remove desc from current queue and add it to the pending_queue */
  839. static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
  840. {
  841. d40_desc_remove(desc);
  842. desc->is_in_client_list = false;
  843. list_add_tail(&desc->node, &d40c->pending_queue);
  844. }
  845. static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
  846. {
  847. return list_first_entry_or_null(&d40c->pending_queue, struct d40_desc,
  848. node);
  849. }
  850. static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
  851. {
  852. return list_first_entry_or_null(&d40c->queue, struct d40_desc, node);
  853. }
  854. static struct d40_desc *d40_first_done(struct d40_chan *d40c)
  855. {
  856. return list_first_entry_or_null(&d40c->done, struct d40_desc, node);
  857. }
  858. static int d40_psize_2_burst_size(bool is_log, int psize)
  859. {
  860. if (is_log) {
  861. if (psize == STEDMA40_PSIZE_LOG_1)
  862. return 1;
  863. } else {
  864. if (psize == STEDMA40_PSIZE_PHY_1)
  865. return 1;
  866. }
  867. return 2 << psize;
  868. }
  869. /*
  870. * The dma only supports transmitting packages up to
  871. * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
  872. *
  873. * Calculate the total number of dma elements required to send the entire sg list.
  874. */
  875. static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
  876. {
  877. int dmalen;
  878. u32 max_w = max(data_width1, data_width2);
  879. u32 min_w = min(data_width1, data_width2);
  880. u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
  881. if (seg_max > STEDMA40_MAX_SEG_SIZE)
  882. seg_max -= max_w;
  883. if (!IS_ALIGNED(size, max_w))
  884. return -EINVAL;
  885. if (size <= seg_max)
  886. dmalen = 1;
  887. else {
  888. dmalen = size / seg_max;
  889. if (dmalen * seg_max < size)
  890. dmalen++;
  891. }
  892. return dmalen;
  893. }
  894. static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
  895. u32 data_width1, u32 data_width2)
  896. {
  897. struct scatterlist *sg;
  898. int i;
  899. int len = 0;
  900. int ret;
  901. for_each_sg(sgl, sg, sg_len, i) {
  902. ret = d40_size_2_dmalen(sg_dma_len(sg),
  903. data_width1, data_width2);
  904. if (ret < 0)
  905. return ret;
  906. len += ret;
  907. }
  908. return len;
  909. }
  910. static int __d40_execute_command_phy(struct d40_chan *d40c,
  911. enum d40_command command)
  912. {
  913. u32 status;
  914. int i;
  915. void __iomem *active_reg;
  916. int ret = 0;
  917. unsigned long flags;
  918. u32 wmask;
  919. if (command == D40_DMA_STOP) {
  920. ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
  921. if (ret)
  922. return ret;
  923. }
  924. spin_lock_irqsave(&d40c->base->execmd_lock, flags);
  925. if (d40c->phy_chan->num % 2 == 0)
  926. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  927. else
  928. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  929. if (command == D40_DMA_SUSPEND_REQ) {
  930. status = (readl(active_reg) &
  931. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  932. D40_CHAN_POS(d40c->phy_chan->num);
  933. if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
  934. goto unlock;
  935. }
  936. wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
  937. writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
  938. active_reg);
  939. if (command == D40_DMA_SUSPEND_REQ) {
  940. for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
  941. status = (readl(active_reg) &
  942. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  943. D40_CHAN_POS(d40c->phy_chan->num);
  944. cpu_relax();
  945. /*
  946. * Reduce the number of bus accesses while
  947. * waiting for the DMA to suspend.
  948. */
  949. udelay(3);
  950. if (status == D40_DMA_STOP ||
  951. status == D40_DMA_SUSPENDED)
  952. break;
  953. }
  954. if (i == D40_SUSPEND_MAX_IT) {
  955. chan_err(d40c,
  956. "unable to suspend the chl %d (log: %d) status %x\n",
  957. d40c->phy_chan->num, d40c->log_num,
  958. status);
  959. dump_stack();
  960. ret = -EBUSY;
  961. }
  962. }
  963. unlock:
  964. spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
  965. return ret;
  966. }
  967. static void d40_term_all(struct d40_chan *d40c)
  968. {
  969. struct d40_desc *d40d;
  970. struct d40_desc *_d;
  971. /* Release completed descriptors */
  972. while ((d40d = d40_first_done(d40c))) {
  973. d40_desc_remove(d40d);
  974. d40_desc_free(d40c, d40d);
  975. }
  976. /* Release active descriptors */
  977. while ((d40d = d40_first_active_get(d40c))) {
  978. d40_desc_remove(d40d);
  979. d40_desc_free(d40c, d40d);
  980. }
  981. /* Release queued descriptors waiting for transfer */
  982. while ((d40d = d40_first_queued(d40c))) {
  983. d40_desc_remove(d40d);
  984. d40_desc_free(d40c, d40d);
  985. }
  986. /* Release pending descriptors */
  987. while ((d40d = d40_first_pending(d40c))) {
  988. d40_desc_remove(d40d);
  989. d40_desc_free(d40c, d40d);
  990. }
  991. /* Release client owned descriptors */
  992. if (!list_empty(&d40c->client))
  993. list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
  994. d40_desc_remove(d40d);
  995. d40_desc_free(d40c, d40d);
  996. }
  997. /* Release descriptors in prepare queue */
  998. if (!list_empty(&d40c->prepare_queue))
  999. list_for_each_entry_safe(d40d, _d,
  1000. &d40c->prepare_queue, node) {
  1001. d40_desc_remove(d40d);
  1002. d40_desc_free(d40c, d40d);
  1003. }
  1004. d40c->pending_tx = 0;
  1005. }
  1006. static void __d40_config_set_event(struct d40_chan *d40c,
  1007. enum d40_events event_type, u32 event,
  1008. int reg)
  1009. {
  1010. void __iomem *addr = chan_base(d40c) + reg;
  1011. int tries;
  1012. u32 status;
  1013. switch (event_type) {
  1014. case D40_DEACTIVATE_EVENTLINE:
  1015. writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
  1016. | ~D40_EVENTLINE_MASK(event), addr);
  1017. break;
  1018. case D40_SUSPEND_REQ_EVENTLINE:
  1019. status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
  1020. D40_EVENTLINE_POS(event);
  1021. if (status == D40_DEACTIVATE_EVENTLINE ||
  1022. status == D40_SUSPEND_REQ_EVENTLINE)
  1023. break;
  1024. writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
  1025. | ~D40_EVENTLINE_MASK(event), addr);
  1026. for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
  1027. status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
  1028. D40_EVENTLINE_POS(event);
  1029. cpu_relax();
  1030. /*
  1031. * Reduce the number of bus accesses while
  1032. * waiting for the DMA to suspend.
  1033. */
  1034. udelay(3);
  1035. if (status == D40_DEACTIVATE_EVENTLINE)
  1036. break;
  1037. }
  1038. if (tries == D40_SUSPEND_MAX_IT) {
  1039. chan_err(d40c,
  1040. "unable to stop the event_line chl %d (log: %d)"
  1041. "status %x\n", d40c->phy_chan->num,
  1042. d40c->log_num, status);
  1043. }
  1044. break;
  1045. case D40_ACTIVATE_EVENTLINE:
  1046. /*
  1047. * The hardware sometimes doesn't register the enable when src and dst
  1048. * event lines are active on the same logical channel. Retry to ensure
  1049. * it does. Usually only one retry is sufficient.
  1050. */
  1051. tries = 100;
  1052. while (--tries) {
  1053. writel((D40_ACTIVATE_EVENTLINE <<
  1054. D40_EVENTLINE_POS(event)) |
  1055. ~D40_EVENTLINE_MASK(event), addr);
  1056. if (readl(addr) & D40_EVENTLINE_MASK(event))
  1057. break;
  1058. }
  1059. if (tries != 99)
  1060. dev_dbg(chan2dev(d40c),
  1061. "[%s] workaround enable S%cLNK (%d tries)\n",
  1062. __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
  1063. 100 - tries);
  1064. WARN_ON(!tries);
  1065. break;
  1066. case D40_ROUND_EVENTLINE:
  1067. BUG();
  1068. break;
  1069. }
  1070. }
  1071. static void d40_config_set_event(struct d40_chan *d40c,
  1072. enum d40_events event_type)
  1073. {
  1074. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1075. /* Enable event line connected to device (or memcpy) */
  1076. if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
  1077. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  1078. __d40_config_set_event(d40c, event_type, event,
  1079. D40_CHAN_REG_SSLNK);
  1080. if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
  1081. __d40_config_set_event(d40c, event_type, event,
  1082. D40_CHAN_REG_SDLNK);
  1083. }
  1084. static u32 d40_chan_has_events(struct d40_chan *d40c)
  1085. {
  1086. void __iomem *chanbase = chan_base(d40c);
  1087. u32 val;
  1088. val = readl(chanbase + D40_CHAN_REG_SSLNK);
  1089. val |= readl(chanbase + D40_CHAN_REG_SDLNK);
  1090. return val;
  1091. }
  1092. static int
  1093. __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
  1094. {
  1095. unsigned long flags;
  1096. int ret = 0;
  1097. u32 active_status;
  1098. void __iomem *active_reg;
  1099. if (d40c->phy_chan->num % 2 == 0)
  1100. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  1101. else
  1102. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  1103. spin_lock_irqsave(&d40c->phy_chan->lock, flags);
  1104. switch (command) {
  1105. case D40_DMA_STOP:
  1106. case D40_DMA_SUSPEND_REQ:
  1107. active_status = (readl(active_reg) &
  1108. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  1109. D40_CHAN_POS(d40c->phy_chan->num);
  1110. if (active_status == D40_DMA_RUN)
  1111. d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
  1112. else
  1113. d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
  1114. if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
  1115. ret = __d40_execute_command_phy(d40c, command);
  1116. break;
  1117. case D40_DMA_RUN:
  1118. d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
  1119. ret = __d40_execute_command_phy(d40c, command);
  1120. break;
  1121. case D40_DMA_SUSPENDED:
  1122. BUG();
  1123. break;
  1124. }
  1125. spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
  1126. return ret;
  1127. }
  1128. static int d40_channel_execute_command(struct d40_chan *d40c,
  1129. enum d40_command command)
  1130. {
  1131. if (chan_is_logical(d40c))
  1132. return __d40_execute_command_log(d40c, command);
  1133. else
  1134. return __d40_execute_command_phy(d40c, command);
  1135. }
  1136. static u32 d40_get_prmo(struct d40_chan *d40c)
  1137. {
  1138. static const unsigned int phy_map[] = {
  1139. [STEDMA40_PCHAN_BASIC_MODE]
  1140. = D40_DREG_PRMO_PCHAN_BASIC,
  1141. [STEDMA40_PCHAN_MODULO_MODE]
  1142. = D40_DREG_PRMO_PCHAN_MODULO,
  1143. [STEDMA40_PCHAN_DOUBLE_DST_MODE]
  1144. = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
  1145. };
  1146. static const unsigned int log_map[] = {
  1147. [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
  1148. = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
  1149. [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
  1150. = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
  1151. [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
  1152. = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
  1153. };
  1154. if (chan_is_physical(d40c))
  1155. return phy_map[d40c->dma_cfg.mode_opt];
  1156. else
  1157. return log_map[d40c->dma_cfg.mode_opt];
  1158. }
  1159. static void d40_config_write(struct d40_chan *d40c)
  1160. {
  1161. u32 addr_base;
  1162. u32 var;
  1163. /* Odd addresses are even addresses + 4 */
  1164. addr_base = (d40c->phy_chan->num % 2) * 4;
  1165. /* Setup channel mode to logical or physical */
  1166. var = ((u32)(chan_is_logical(d40c)) + 1) <<
  1167. D40_CHAN_POS(d40c->phy_chan->num);
  1168. writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
  1169. /* Setup operational mode option register */
  1170. var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
  1171. writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
  1172. if (chan_is_logical(d40c)) {
  1173. int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
  1174. & D40_SREG_ELEM_LOG_LIDX_MASK;
  1175. void __iomem *chanbase = chan_base(d40c);
  1176. /* Set default config for CFG reg */
  1177. writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
  1178. writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
  1179. /* Set LIDX for lcla */
  1180. writel(lidx, chanbase + D40_CHAN_REG_SSELT);
  1181. writel(lidx, chanbase + D40_CHAN_REG_SDELT);
  1182. /* Clear LNK which will be used by d40_chan_has_events() */
  1183. writel(0, chanbase + D40_CHAN_REG_SSLNK);
  1184. writel(0, chanbase + D40_CHAN_REG_SDLNK);
  1185. }
  1186. }
  1187. static u32 d40_residue(struct d40_chan *d40c)
  1188. {
  1189. u32 num_elt;
  1190. if (chan_is_logical(d40c))
  1191. num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
  1192. >> D40_MEM_LCSP2_ECNT_POS;
  1193. else {
  1194. u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
  1195. num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
  1196. >> D40_SREG_ELEM_PHY_ECNT_POS;
  1197. }
  1198. return num_elt * d40c->dma_cfg.dst_info.data_width;
  1199. }
  1200. static bool d40_tx_is_linked(struct d40_chan *d40c)
  1201. {
  1202. bool is_link;
  1203. if (chan_is_logical(d40c))
  1204. is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
  1205. else
  1206. is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
  1207. & D40_SREG_LNK_PHYS_LNK_MASK;
  1208. return is_link;
  1209. }
  1210. static int d40_pause(struct dma_chan *chan)
  1211. {
  1212. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  1213. int res = 0;
  1214. unsigned long flags;
  1215. if (d40c->phy_chan == NULL) {
  1216. chan_err(d40c, "Channel is not allocated!\n");
  1217. return -EINVAL;
  1218. }
  1219. if (!d40c->busy)
  1220. return 0;
  1221. spin_lock_irqsave(&d40c->lock, flags);
  1222. pm_runtime_get_sync(d40c->base->dev);
  1223. res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
  1224. pm_runtime_mark_last_busy(d40c->base->dev);
  1225. pm_runtime_put_autosuspend(d40c->base->dev);
  1226. spin_unlock_irqrestore(&d40c->lock, flags);
  1227. return res;
  1228. }
  1229. static int d40_resume(struct dma_chan *chan)
  1230. {
  1231. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  1232. int res = 0;
  1233. unsigned long flags;
  1234. if (d40c->phy_chan == NULL) {
  1235. chan_err(d40c, "Channel is not allocated!\n");
  1236. return -EINVAL;
  1237. }
  1238. if (!d40c->busy)
  1239. return 0;
  1240. spin_lock_irqsave(&d40c->lock, flags);
  1241. pm_runtime_get_sync(d40c->base->dev);
  1242. /* If bytes left to transfer or linked tx resume job */
  1243. if (d40_residue(d40c) || d40_tx_is_linked(d40c))
  1244. res = d40_channel_execute_command(d40c, D40_DMA_RUN);
  1245. pm_runtime_mark_last_busy(d40c->base->dev);
  1246. pm_runtime_put_autosuspend(d40c->base->dev);
  1247. spin_unlock_irqrestore(&d40c->lock, flags);
  1248. return res;
  1249. }
  1250. static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
  1251. {
  1252. struct d40_chan *d40c = container_of(tx->chan,
  1253. struct d40_chan,
  1254. chan);
  1255. struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
  1256. unsigned long flags;
  1257. dma_cookie_t cookie;
  1258. spin_lock_irqsave(&d40c->lock, flags);
  1259. cookie = dma_cookie_assign(tx);
  1260. d40_desc_queue(d40c, d40d);
  1261. spin_unlock_irqrestore(&d40c->lock, flags);
  1262. return cookie;
  1263. }
  1264. static int d40_start(struct d40_chan *d40c)
  1265. {
  1266. return d40_channel_execute_command(d40c, D40_DMA_RUN);
  1267. }
  1268. static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
  1269. {
  1270. struct d40_desc *d40d;
  1271. int err;
  1272. /* Start queued jobs, if any */
  1273. d40d = d40_first_queued(d40c);
  1274. if (d40d != NULL) {
  1275. if (!d40c->busy) {
  1276. d40c->busy = true;
  1277. pm_runtime_get_sync(d40c->base->dev);
  1278. }
  1279. /* Remove from queue */
  1280. d40_desc_remove(d40d);
  1281. /* Add to active queue */
  1282. d40_desc_submit(d40c, d40d);
  1283. /* Initiate DMA job */
  1284. d40_desc_load(d40c, d40d);
  1285. /* Start dma job */
  1286. err = d40_start(d40c);
  1287. if (err)
  1288. return NULL;
  1289. }
  1290. return d40d;
  1291. }
  1292. /* called from interrupt context */
  1293. static void dma_tc_handle(struct d40_chan *d40c)
  1294. {
  1295. struct d40_desc *d40d;
  1296. /* Get first active entry from list */
  1297. d40d = d40_first_active_get(d40c);
  1298. if (d40d == NULL)
  1299. return;
  1300. if (d40d->cyclic) {
  1301. /*
  1302. * If this was a paritially loaded list, we need to reloaded
  1303. * it, and only when the list is completed. We need to check
  1304. * for done because the interrupt will hit for every link, and
  1305. * not just the last one.
  1306. */
  1307. if (d40d->lli_current < d40d->lli_len
  1308. && !d40_tx_is_linked(d40c)
  1309. && !d40_residue(d40c)) {
  1310. d40_lcla_free_all(d40c, d40d);
  1311. d40_desc_load(d40c, d40d);
  1312. (void) d40_start(d40c);
  1313. if (d40d->lli_current == d40d->lli_len)
  1314. d40d->lli_current = 0;
  1315. }
  1316. } else {
  1317. d40_lcla_free_all(d40c, d40d);
  1318. if (d40d->lli_current < d40d->lli_len) {
  1319. d40_desc_load(d40c, d40d);
  1320. /* Start dma job */
  1321. (void) d40_start(d40c);
  1322. return;
  1323. }
  1324. if (d40_queue_start(d40c) == NULL) {
  1325. d40c->busy = false;
  1326. pm_runtime_mark_last_busy(d40c->base->dev);
  1327. pm_runtime_put_autosuspend(d40c->base->dev);
  1328. }
  1329. d40_desc_remove(d40d);
  1330. d40_desc_done(d40c, d40d);
  1331. }
  1332. d40c->pending_tx++;
  1333. tasklet_schedule(&d40c->tasklet);
  1334. }
  1335. static void dma_tasklet(struct tasklet_struct *t)
  1336. {
  1337. struct d40_chan *d40c = from_tasklet(d40c, t, tasklet);
  1338. struct d40_desc *d40d;
  1339. unsigned long flags;
  1340. bool callback_active;
  1341. struct dmaengine_desc_callback cb;
  1342. spin_lock_irqsave(&d40c->lock, flags);
  1343. /* Get first entry from the done list */
  1344. d40d = d40_first_done(d40c);
  1345. if (d40d == NULL) {
  1346. /* Check if we have reached here for cyclic job */
  1347. d40d = d40_first_active_get(d40c);
  1348. if (d40d == NULL || !d40d->cyclic)
  1349. goto check_pending_tx;
  1350. }
  1351. if (!d40d->cyclic)
  1352. dma_cookie_complete(&d40d->txd);
  1353. /*
  1354. * If terminating a channel pending_tx is set to zero.
  1355. * This prevents any finished active jobs to return to the client.
  1356. */
  1357. if (d40c->pending_tx == 0) {
  1358. spin_unlock_irqrestore(&d40c->lock, flags);
  1359. return;
  1360. }
  1361. /* Callback to client */
  1362. callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
  1363. dmaengine_desc_get_callback(&d40d->txd, &cb);
  1364. if (!d40d->cyclic) {
  1365. if (async_tx_test_ack(&d40d->txd)) {
  1366. d40_desc_remove(d40d);
  1367. d40_desc_free(d40c, d40d);
  1368. } else if (!d40d->is_in_client_list) {
  1369. d40_desc_remove(d40d);
  1370. d40_lcla_free_all(d40c, d40d);
  1371. list_add_tail(&d40d->node, &d40c->client);
  1372. d40d->is_in_client_list = true;
  1373. }
  1374. }
  1375. d40c->pending_tx--;
  1376. if (d40c->pending_tx)
  1377. tasklet_schedule(&d40c->tasklet);
  1378. spin_unlock_irqrestore(&d40c->lock, flags);
  1379. if (callback_active)
  1380. dmaengine_desc_callback_invoke(&cb, NULL);
  1381. return;
  1382. check_pending_tx:
  1383. /* Rescue manouver if receiving double interrupts */
  1384. if (d40c->pending_tx > 0)
  1385. d40c->pending_tx--;
  1386. spin_unlock_irqrestore(&d40c->lock, flags);
  1387. }
  1388. static irqreturn_t d40_handle_interrupt(int irq, void *data)
  1389. {
  1390. int i;
  1391. u32 idx;
  1392. u32 row;
  1393. long chan = -1;
  1394. struct d40_chan *d40c;
  1395. unsigned long flags;
  1396. struct d40_base *base = data;
  1397. u32 *regs = base->regs_interrupt;
  1398. struct d40_interrupt_lookup *il = base->gen_dmac.il;
  1399. u32 il_size = base->gen_dmac.il_size;
  1400. spin_lock_irqsave(&base->interrupt_lock, flags);
  1401. /* Read interrupt status of both logical and physical channels */
  1402. for (i = 0; i < il_size; i++)
  1403. regs[i] = readl(base->virtbase + il[i].src);
  1404. for (;;) {
  1405. chan = find_next_bit((unsigned long *)regs,
  1406. BITS_PER_LONG * il_size, chan + 1);
  1407. /* No more set bits found? */
  1408. if (chan == BITS_PER_LONG * il_size)
  1409. break;
  1410. row = chan / BITS_PER_LONG;
  1411. idx = chan & (BITS_PER_LONG - 1);
  1412. if (il[row].offset == D40_PHY_CHAN)
  1413. d40c = base->lookup_phy_chans[idx];
  1414. else
  1415. d40c = base->lookup_log_chans[il[row].offset + idx];
  1416. if (!d40c) {
  1417. /*
  1418. * No error because this can happen if something else
  1419. * in the system is using the channel.
  1420. */
  1421. continue;
  1422. }
  1423. /* ACK interrupt */
  1424. writel(BIT(idx), base->virtbase + il[row].clr);
  1425. spin_lock(&d40c->lock);
  1426. if (!il[row].is_error)
  1427. dma_tc_handle(d40c);
  1428. else
  1429. d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
  1430. chan, il[row].offset, idx);
  1431. spin_unlock(&d40c->lock);
  1432. }
  1433. spin_unlock_irqrestore(&base->interrupt_lock, flags);
  1434. return IRQ_HANDLED;
  1435. }
  1436. static int d40_validate_conf(struct d40_chan *d40c,
  1437. struct stedma40_chan_cfg *conf)
  1438. {
  1439. int res = 0;
  1440. bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
  1441. if (!conf->dir) {
  1442. chan_err(d40c, "Invalid direction.\n");
  1443. res = -EINVAL;
  1444. }
  1445. if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
  1446. (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
  1447. (conf->dev_type < 0)) {
  1448. chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
  1449. res = -EINVAL;
  1450. }
  1451. if (conf->dir == DMA_DEV_TO_DEV) {
  1452. /*
  1453. * DMAC HW supports it. Will be added to this driver,
  1454. * in case any dma client requires it.
  1455. */
  1456. chan_err(d40c, "periph to periph not supported\n");
  1457. res = -EINVAL;
  1458. }
  1459. if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
  1460. conf->src_info.data_width !=
  1461. d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
  1462. conf->dst_info.data_width) {
  1463. /*
  1464. * The DMAC hardware only supports
  1465. * src (burst x width) == dst (burst x width)
  1466. */
  1467. chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
  1468. res = -EINVAL;
  1469. }
  1470. return res;
  1471. }
  1472. static bool d40_alloc_mask_set(struct d40_phy_res *phy,
  1473. bool is_src, int log_event_line, bool is_log,
  1474. bool *first_user)
  1475. {
  1476. unsigned long flags;
  1477. spin_lock_irqsave(&phy->lock, flags);
  1478. *first_user = ((phy->allocated_src | phy->allocated_dst)
  1479. == D40_ALLOC_FREE);
  1480. if (!is_log) {
  1481. /* Physical interrupts are masked per physical full channel */
  1482. if (phy->allocated_src == D40_ALLOC_FREE &&
  1483. phy->allocated_dst == D40_ALLOC_FREE) {
  1484. phy->allocated_dst = D40_ALLOC_PHY;
  1485. phy->allocated_src = D40_ALLOC_PHY;
  1486. goto found_unlock;
  1487. } else
  1488. goto not_found_unlock;
  1489. }
  1490. /* Logical channel */
  1491. if (is_src) {
  1492. if (phy->allocated_src == D40_ALLOC_PHY)
  1493. goto not_found_unlock;
  1494. if (phy->allocated_src == D40_ALLOC_FREE)
  1495. phy->allocated_src = D40_ALLOC_LOG_FREE;
  1496. if (!(phy->allocated_src & BIT(log_event_line))) {
  1497. phy->allocated_src |= BIT(log_event_line);
  1498. goto found_unlock;
  1499. } else
  1500. goto not_found_unlock;
  1501. } else {
  1502. if (phy->allocated_dst == D40_ALLOC_PHY)
  1503. goto not_found_unlock;
  1504. if (phy->allocated_dst == D40_ALLOC_FREE)
  1505. phy->allocated_dst = D40_ALLOC_LOG_FREE;
  1506. if (!(phy->allocated_dst & BIT(log_event_line))) {
  1507. phy->allocated_dst |= BIT(log_event_line);
  1508. goto found_unlock;
  1509. }
  1510. }
  1511. not_found_unlock:
  1512. spin_unlock_irqrestore(&phy->lock, flags);
  1513. return false;
  1514. found_unlock:
  1515. spin_unlock_irqrestore(&phy->lock, flags);
  1516. return true;
  1517. }
  1518. static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
  1519. int log_event_line)
  1520. {
  1521. unsigned long flags;
  1522. bool is_free = false;
  1523. spin_lock_irqsave(&phy->lock, flags);
  1524. if (!log_event_line) {
  1525. phy->allocated_dst = D40_ALLOC_FREE;
  1526. phy->allocated_src = D40_ALLOC_FREE;
  1527. is_free = true;
  1528. goto unlock;
  1529. }
  1530. /* Logical channel */
  1531. if (is_src) {
  1532. phy->allocated_src &= ~BIT(log_event_line);
  1533. if (phy->allocated_src == D40_ALLOC_LOG_FREE)
  1534. phy->allocated_src = D40_ALLOC_FREE;
  1535. } else {
  1536. phy->allocated_dst &= ~BIT(log_event_line);
  1537. if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
  1538. phy->allocated_dst = D40_ALLOC_FREE;
  1539. }
  1540. is_free = ((phy->allocated_src | phy->allocated_dst) ==
  1541. D40_ALLOC_FREE);
  1542. unlock:
  1543. spin_unlock_irqrestore(&phy->lock, flags);
  1544. return is_free;
  1545. }
  1546. static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
  1547. {
  1548. int dev_type = d40c->dma_cfg.dev_type;
  1549. int event_group;
  1550. int event_line;
  1551. struct d40_phy_res *phys;
  1552. int i;
  1553. int j;
  1554. int log_num;
  1555. int num_phy_chans;
  1556. bool is_src;
  1557. bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
  1558. phys = d40c->base->phy_res;
  1559. num_phy_chans = d40c->base->num_phy_chans;
  1560. if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
  1561. log_num = 2 * dev_type;
  1562. is_src = true;
  1563. } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1564. d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1565. /* dst event lines are used for logical memcpy */
  1566. log_num = 2 * dev_type + 1;
  1567. is_src = false;
  1568. } else
  1569. return -EINVAL;
  1570. event_group = D40_TYPE_TO_GROUP(dev_type);
  1571. event_line = D40_TYPE_TO_EVENT(dev_type);
  1572. if (!is_log) {
  1573. if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1574. /* Find physical half channel */
  1575. if (d40c->dma_cfg.use_fixed_channel) {
  1576. i = d40c->dma_cfg.phy_channel;
  1577. if (d40_alloc_mask_set(&phys[i], is_src,
  1578. 0, is_log,
  1579. first_phy_user))
  1580. goto found_phy;
  1581. } else {
  1582. for (i = 0; i < num_phy_chans; i++) {
  1583. if (d40_alloc_mask_set(&phys[i], is_src,
  1584. 0, is_log,
  1585. first_phy_user))
  1586. goto found_phy;
  1587. }
  1588. }
  1589. } else
  1590. for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
  1591. int phy_num = j + event_group * 2;
  1592. for (i = phy_num; i < phy_num + 2; i++) {
  1593. if (d40_alloc_mask_set(&phys[i],
  1594. is_src,
  1595. 0,
  1596. is_log,
  1597. first_phy_user))
  1598. goto found_phy;
  1599. }
  1600. }
  1601. return -EINVAL;
  1602. found_phy:
  1603. d40c->phy_chan = &phys[i];
  1604. d40c->log_num = D40_PHY_CHAN;
  1605. goto out;
  1606. }
  1607. if (dev_type == -1)
  1608. return -EINVAL;
  1609. /* Find logical channel */
  1610. for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
  1611. int phy_num = j + event_group * 2;
  1612. if (d40c->dma_cfg.use_fixed_channel) {
  1613. i = d40c->dma_cfg.phy_channel;
  1614. if ((i != phy_num) && (i != phy_num + 1)) {
  1615. dev_err(chan2dev(d40c),
  1616. "invalid fixed phy channel %d\n", i);
  1617. return -EINVAL;
  1618. }
  1619. if (d40_alloc_mask_set(&phys[i], is_src, event_line,
  1620. is_log, first_phy_user))
  1621. goto found_log;
  1622. dev_err(chan2dev(d40c),
  1623. "could not allocate fixed phy channel %d\n", i);
  1624. return -EINVAL;
  1625. }
  1626. /*
  1627. * Spread logical channels across all available physical rather
  1628. * than pack every logical channel at the first available phy
  1629. * channels.
  1630. */
  1631. if (is_src) {
  1632. for (i = phy_num; i < phy_num + 2; i++) {
  1633. if (d40_alloc_mask_set(&phys[i], is_src,
  1634. event_line, is_log,
  1635. first_phy_user))
  1636. goto found_log;
  1637. }
  1638. } else {
  1639. for (i = phy_num + 1; i >= phy_num; i--) {
  1640. if (d40_alloc_mask_set(&phys[i], is_src,
  1641. event_line, is_log,
  1642. first_phy_user))
  1643. goto found_log;
  1644. }
  1645. }
  1646. }
  1647. return -EINVAL;
  1648. found_log:
  1649. d40c->phy_chan = &phys[i];
  1650. d40c->log_num = log_num;
  1651. out:
  1652. if (is_log)
  1653. d40c->base->lookup_log_chans[d40c->log_num] = d40c;
  1654. else
  1655. d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
  1656. return 0;
  1657. }
  1658. static int d40_config_memcpy(struct d40_chan *d40c)
  1659. {
  1660. dma_cap_mask_t cap = d40c->chan.device->cap_mask;
  1661. if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
  1662. d40c->dma_cfg = dma40_memcpy_conf_log;
  1663. d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
  1664. d40_log_cfg(&d40c->dma_cfg,
  1665. &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
  1666. } else if (dma_has_cap(DMA_MEMCPY, cap) &&
  1667. dma_has_cap(DMA_SLAVE, cap)) {
  1668. d40c->dma_cfg = dma40_memcpy_conf_phy;
  1669. /* Generate interrrupt at end of transfer or relink. */
  1670. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
  1671. /* Generate interrupt on error. */
  1672. d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
  1673. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
  1674. } else {
  1675. chan_err(d40c, "No memcpy\n");
  1676. return -EINVAL;
  1677. }
  1678. return 0;
  1679. }
  1680. static int d40_free_dma(struct d40_chan *d40c)
  1681. {
  1682. int res = 0;
  1683. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1684. struct d40_phy_res *phy = d40c->phy_chan;
  1685. bool is_src;
  1686. /* Terminate all queued and active transfers */
  1687. d40_term_all(d40c);
  1688. if (phy == NULL) {
  1689. chan_err(d40c, "phy == null\n");
  1690. return -EINVAL;
  1691. }
  1692. if (phy->allocated_src == D40_ALLOC_FREE &&
  1693. phy->allocated_dst == D40_ALLOC_FREE) {
  1694. chan_err(d40c, "channel already free\n");
  1695. return -EINVAL;
  1696. }
  1697. if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1698. d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
  1699. is_src = false;
  1700. else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
  1701. is_src = true;
  1702. else {
  1703. chan_err(d40c, "Unknown direction\n");
  1704. return -EINVAL;
  1705. }
  1706. pm_runtime_get_sync(d40c->base->dev);
  1707. res = d40_channel_execute_command(d40c, D40_DMA_STOP);
  1708. if (res) {
  1709. chan_err(d40c, "stop failed\n");
  1710. goto mark_last_busy;
  1711. }
  1712. d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
  1713. if (chan_is_logical(d40c))
  1714. d40c->base->lookup_log_chans[d40c->log_num] = NULL;
  1715. else
  1716. d40c->base->lookup_phy_chans[phy->num] = NULL;
  1717. if (d40c->busy) {
  1718. pm_runtime_mark_last_busy(d40c->base->dev);
  1719. pm_runtime_put_autosuspend(d40c->base->dev);
  1720. }
  1721. d40c->busy = false;
  1722. d40c->phy_chan = NULL;
  1723. d40c->configured = false;
  1724. mark_last_busy:
  1725. pm_runtime_mark_last_busy(d40c->base->dev);
  1726. pm_runtime_put_autosuspend(d40c->base->dev);
  1727. return res;
  1728. }
  1729. static bool d40_is_paused(struct d40_chan *d40c)
  1730. {
  1731. void __iomem *chanbase = chan_base(d40c);
  1732. bool is_paused = false;
  1733. unsigned long flags;
  1734. void __iomem *active_reg;
  1735. u32 status;
  1736. u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
  1737. spin_lock_irqsave(&d40c->lock, flags);
  1738. if (chan_is_physical(d40c)) {
  1739. if (d40c->phy_chan->num % 2 == 0)
  1740. active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
  1741. else
  1742. active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
  1743. status = (readl(active_reg) &
  1744. D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
  1745. D40_CHAN_POS(d40c->phy_chan->num);
  1746. if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
  1747. is_paused = true;
  1748. goto unlock;
  1749. }
  1750. if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
  1751. d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
  1752. status = readl(chanbase + D40_CHAN_REG_SDLNK);
  1753. } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
  1754. status = readl(chanbase + D40_CHAN_REG_SSLNK);
  1755. } else {
  1756. chan_err(d40c, "Unknown direction\n");
  1757. goto unlock;
  1758. }
  1759. status = (status & D40_EVENTLINE_MASK(event)) >>
  1760. D40_EVENTLINE_POS(event);
  1761. if (status != D40_DMA_RUN)
  1762. is_paused = true;
  1763. unlock:
  1764. spin_unlock_irqrestore(&d40c->lock, flags);
  1765. return is_paused;
  1766. }
  1767. static u32 stedma40_residue(struct dma_chan *chan)
  1768. {
  1769. struct d40_chan *d40c =
  1770. container_of(chan, struct d40_chan, chan);
  1771. u32 bytes_left;
  1772. unsigned long flags;
  1773. spin_lock_irqsave(&d40c->lock, flags);
  1774. bytes_left = d40_residue(d40c);
  1775. spin_unlock_irqrestore(&d40c->lock, flags);
  1776. return bytes_left;
  1777. }
  1778. static int
  1779. d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
  1780. struct scatterlist *sg_src, struct scatterlist *sg_dst,
  1781. unsigned int sg_len, dma_addr_t src_dev_addr,
  1782. dma_addr_t dst_dev_addr)
  1783. {
  1784. struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
  1785. struct stedma40_half_channel_info *src_info = &cfg->src_info;
  1786. struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
  1787. int ret;
  1788. ret = d40_log_sg_to_lli(sg_src, sg_len,
  1789. src_dev_addr,
  1790. desc->lli_log.src,
  1791. chan->log_def.lcsp1,
  1792. src_info->data_width,
  1793. dst_info->data_width);
  1794. ret = d40_log_sg_to_lli(sg_dst, sg_len,
  1795. dst_dev_addr,
  1796. desc->lli_log.dst,
  1797. chan->log_def.lcsp3,
  1798. dst_info->data_width,
  1799. src_info->data_width);
  1800. return ret < 0 ? ret : 0;
  1801. }
  1802. static int
  1803. d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
  1804. struct scatterlist *sg_src, struct scatterlist *sg_dst,
  1805. unsigned int sg_len, dma_addr_t src_dev_addr,
  1806. dma_addr_t dst_dev_addr)
  1807. {
  1808. struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
  1809. struct stedma40_half_channel_info *src_info = &cfg->src_info;
  1810. struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
  1811. unsigned long flags = 0;
  1812. int ret;
  1813. if (desc->cyclic)
  1814. flags |= LLI_CYCLIC | LLI_TERM_INT;
  1815. ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
  1816. desc->lli_phy.src,
  1817. virt_to_phys(desc->lli_phy.src),
  1818. chan->src_def_cfg,
  1819. src_info, dst_info, flags);
  1820. ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
  1821. desc->lli_phy.dst,
  1822. virt_to_phys(desc->lli_phy.dst),
  1823. chan->dst_def_cfg,
  1824. dst_info, src_info, flags);
  1825. dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
  1826. desc->lli_pool.size, DMA_TO_DEVICE);
  1827. return ret < 0 ? ret : 0;
  1828. }
  1829. static struct d40_desc *
  1830. d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
  1831. unsigned int sg_len, unsigned long dma_flags)
  1832. {
  1833. struct stedma40_chan_cfg *cfg;
  1834. struct d40_desc *desc;
  1835. int ret;
  1836. desc = d40_desc_get(chan);
  1837. if (!desc)
  1838. return NULL;
  1839. cfg = &chan->dma_cfg;
  1840. desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
  1841. cfg->dst_info.data_width);
  1842. if (desc->lli_len < 0) {
  1843. chan_err(chan, "Unaligned size\n");
  1844. goto free_desc;
  1845. }
  1846. ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
  1847. if (ret < 0) {
  1848. chan_err(chan, "Could not allocate lli\n");
  1849. goto free_desc;
  1850. }
  1851. desc->lli_current = 0;
  1852. desc->txd.flags = dma_flags;
  1853. desc->txd.tx_submit = d40_tx_submit;
  1854. dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
  1855. return desc;
  1856. free_desc:
  1857. d40_desc_free(chan, desc);
  1858. return NULL;
  1859. }
  1860. static struct dma_async_tx_descriptor *
  1861. d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
  1862. struct scatterlist *sg_dst, unsigned int sg_len,
  1863. enum dma_transfer_direction direction, unsigned long dma_flags)
  1864. {
  1865. struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
  1866. dma_addr_t src_dev_addr;
  1867. dma_addr_t dst_dev_addr;
  1868. struct d40_desc *desc;
  1869. unsigned long flags;
  1870. int ret;
  1871. if (!chan->phy_chan) {
  1872. chan_err(chan, "Cannot prepare unallocated channel\n");
  1873. return NULL;
  1874. }
  1875. d40_set_runtime_config_write(dchan, &chan->slave_config, direction);
  1876. spin_lock_irqsave(&chan->lock, flags);
  1877. desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
  1878. if (desc == NULL)
  1879. goto unlock;
  1880. if (sg_next(&sg_src[sg_len - 1]) == sg_src)
  1881. desc->cyclic = true;
  1882. src_dev_addr = 0;
  1883. dst_dev_addr = 0;
  1884. if (direction == DMA_DEV_TO_MEM)
  1885. src_dev_addr = chan->runtime_addr;
  1886. else if (direction == DMA_MEM_TO_DEV)
  1887. dst_dev_addr = chan->runtime_addr;
  1888. if (chan_is_logical(chan))
  1889. ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
  1890. sg_len, src_dev_addr, dst_dev_addr);
  1891. else
  1892. ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
  1893. sg_len, src_dev_addr, dst_dev_addr);
  1894. if (ret) {
  1895. chan_err(chan, "Failed to prepare %s sg job: %d\n",
  1896. chan_is_logical(chan) ? "log" : "phy", ret);
  1897. goto free_desc;
  1898. }
  1899. /*
  1900. * add descriptor to the prepare queue in order to be able
  1901. * to free them later in terminate_all
  1902. */
  1903. list_add_tail(&desc->node, &chan->prepare_queue);
  1904. spin_unlock_irqrestore(&chan->lock, flags);
  1905. return &desc->txd;
  1906. free_desc:
  1907. d40_desc_free(chan, desc);
  1908. unlock:
  1909. spin_unlock_irqrestore(&chan->lock, flags);
  1910. return NULL;
  1911. }
  1912. bool stedma40_filter(struct dma_chan *chan, void *data)
  1913. {
  1914. struct stedma40_chan_cfg *info = data;
  1915. struct d40_chan *d40c =
  1916. container_of(chan, struct d40_chan, chan);
  1917. int err;
  1918. if (data) {
  1919. err = d40_validate_conf(d40c, info);
  1920. if (!err)
  1921. d40c->dma_cfg = *info;
  1922. } else
  1923. err = d40_config_memcpy(d40c);
  1924. if (!err)
  1925. d40c->configured = true;
  1926. return err == 0;
  1927. }
  1928. EXPORT_SYMBOL(stedma40_filter);
  1929. static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
  1930. {
  1931. bool realtime = d40c->dma_cfg.realtime;
  1932. bool highprio = d40c->dma_cfg.high_priority;
  1933. u32 rtreg;
  1934. u32 event = D40_TYPE_TO_EVENT(dev_type);
  1935. u32 group = D40_TYPE_TO_GROUP(dev_type);
  1936. u32 bit = BIT(event);
  1937. u32 prioreg;
  1938. struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
  1939. rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
  1940. /*
  1941. * Due to a hardware bug, in some cases a logical channel triggered by
  1942. * a high priority destination event line can generate extra packet
  1943. * transactions.
  1944. *
  1945. * The workaround is to not set the high priority level for the
  1946. * destination event lines that trigger logical channels.
  1947. */
  1948. if (!src && chan_is_logical(d40c))
  1949. highprio = false;
  1950. prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
  1951. /* Destination event lines are stored in the upper halfword */
  1952. if (!src)
  1953. bit <<= 16;
  1954. writel(bit, d40c->base->virtbase + prioreg + group * 4);
  1955. writel(bit, d40c->base->virtbase + rtreg + group * 4);
  1956. }
  1957. static void d40_set_prio_realtime(struct d40_chan *d40c)
  1958. {
  1959. if (d40c->base->rev < 3)
  1960. return;
  1961. if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
  1962. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  1963. __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
  1964. if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
  1965. (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
  1966. __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
  1967. }
  1968. #define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
  1969. #define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
  1970. #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
  1971. #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
  1972. #define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
  1973. static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
  1974. struct of_dma *ofdma)
  1975. {
  1976. struct stedma40_chan_cfg cfg;
  1977. dma_cap_mask_t cap;
  1978. u32 flags;
  1979. memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
  1980. dma_cap_zero(cap);
  1981. dma_cap_set(DMA_SLAVE, cap);
  1982. cfg.dev_type = dma_spec->args[0];
  1983. flags = dma_spec->args[2];
  1984. switch (D40_DT_FLAGS_MODE(flags)) {
  1985. case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
  1986. case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
  1987. }
  1988. switch (D40_DT_FLAGS_DIR(flags)) {
  1989. case 0:
  1990. cfg.dir = DMA_MEM_TO_DEV;
  1991. cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
  1992. break;
  1993. case 1:
  1994. cfg.dir = DMA_DEV_TO_MEM;
  1995. cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
  1996. break;
  1997. }
  1998. if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
  1999. cfg.phy_channel = dma_spec->args[1];
  2000. cfg.use_fixed_channel = true;
  2001. }
  2002. if (D40_DT_FLAGS_HIGH_PRIO(flags))
  2003. cfg.high_priority = true;
  2004. return dma_request_channel(cap, stedma40_filter, &cfg);
  2005. }
  2006. /* DMA ENGINE functions */
  2007. static int d40_alloc_chan_resources(struct dma_chan *chan)
  2008. {
  2009. int err;
  2010. unsigned long flags;
  2011. struct d40_chan *d40c =
  2012. container_of(chan, struct d40_chan, chan);
  2013. bool is_free_phy;
  2014. spin_lock_irqsave(&d40c->lock, flags);
  2015. dma_cookie_init(chan);
  2016. /* If no dma configuration is set use default configuration (memcpy) */
  2017. if (!d40c->configured) {
  2018. err = d40_config_memcpy(d40c);
  2019. if (err) {
  2020. chan_err(d40c, "Failed to configure memcpy channel\n");
  2021. goto mark_last_busy;
  2022. }
  2023. }
  2024. err = d40_allocate_channel(d40c, &is_free_phy);
  2025. if (err) {
  2026. chan_err(d40c, "Failed to allocate channel\n");
  2027. d40c->configured = false;
  2028. goto mark_last_busy;
  2029. }
  2030. pm_runtime_get_sync(d40c->base->dev);
  2031. d40_set_prio_realtime(d40c);
  2032. if (chan_is_logical(d40c)) {
  2033. if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
  2034. d40c->lcpa = d40c->base->lcpa_base +
  2035. d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
  2036. else
  2037. d40c->lcpa = d40c->base->lcpa_base +
  2038. d40c->dma_cfg.dev_type *
  2039. D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
  2040. /* Unmask the Global Interrupt Mask. */
  2041. d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
  2042. d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
  2043. }
  2044. dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
  2045. chan_is_logical(d40c) ? "logical" : "physical",
  2046. d40c->phy_chan->num,
  2047. d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
  2048. /*
  2049. * Only write channel configuration to the DMA if the physical
  2050. * resource is free. In case of multiple logical channels
  2051. * on the same physical resource, only the first write is necessary.
  2052. */
  2053. if (is_free_phy)
  2054. d40_config_write(d40c);
  2055. mark_last_busy:
  2056. pm_runtime_mark_last_busy(d40c->base->dev);
  2057. pm_runtime_put_autosuspend(d40c->base->dev);
  2058. spin_unlock_irqrestore(&d40c->lock, flags);
  2059. return err;
  2060. }
  2061. static void d40_free_chan_resources(struct dma_chan *chan)
  2062. {
  2063. struct d40_chan *d40c =
  2064. container_of(chan, struct d40_chan, chan);
  2065. int err;
  2066. unsigned long flags;
  2067. if (d40c->phy_chan == NULL) {
  2068. chan_err(d40c, "Cannot free unallocated channel\n");
  2069. return;
  2070. }
  2071. spin_lock_irqsave(&d40c->lock, flags);
  2072. err = d40_free_dma(d40c);
  2073. if (err)
  2074. chan_err(d40c, "Failed to free channel\n");
  2075. spin_unlock_irqrestore(&d40c->lock, flags);
  2076. }
  2077. static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
  2078. dma_addr_t dst,
  2079. dma_addr_t src,
  2080. size_t size,
  2081. unsigned long dma_flags)
  2082. {
  2083. struct scatterlist dst_sg;
  2084. struct scatterlist src_sg;
  2085. sg_init_table(&dst_sg, 1);
  2086. sg_init_table(&src_sg, 1);
  2087. sg_dma_address(&dst_sg) = dst;
  2088. sg_dma_address(&src_sg) = src;
  2089. sg_dma_len(&dst_sg) = size;
  2090. sg_dma_len(&src_sg) = size;
  2091. return d40_prep_sg(chan, &src_sg, &dst_sg, 1,
  2092. DMA_MEM_TO_MEM, dma_flags);
  2093. }
  2094. static struct dma_async_tx_descriptor *
  2095. d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  2096. unsigned int sg_len, enum dma_transfer_direction direction,
  2097. unsigned long dma_flags, void *context)
  2098. {
  2099. if (!is_slave_direction(direction))
  2100. return NULL;
  2101. return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
  2102. }
  2103. static struct dma_async_tx_descriptor *
  2104. dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
  2105. size_t buf_len, size_t period_len,
  2106. enum dma_transfer_direction direction, unsigned long flags)
  2107. {
  2108. unsigned int periods = buf_len / period_len;
  2109. struct dma_async_tx_descriptor *txd;
  2110. struct scatterlist *sg;
  2111. int i;
  2112. sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
  2113. if (!sg)
  2114. return NULL;
  2115. for (i = 0; i < periods; i++) {
  2116. sg_dma_address(&sg[i]) = dma_addr;
  2117. sg_dma_len(&sg[i]) = period_len;
  2118. dma_addr += period_len;
  2119. }
  2120. sg_chain(sg, periods + 1, sg);
  2121. txd = d40_prep_sg(chan, sg, sg, periods, direction,
  2122. DMA_PREP_INTERRUPT);
  2123. kfree(sg);
  2124. return txd;
  2125. }
  2126. static enum dma_status d40_tx_status(struct dma_chan *chan,
  2127. dma_cookie_t cookie,
  2128. struct dma_tx_state *txstate)
  2129. {
  2130. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2131. enum dma_status ret;
  2132. if (d40c->phy_chan == NULL) {
  2133. chan_err(d40c, "Cannot read status of unallocated channel\n");
  2134. return -EINVAL;
  2135. }
  2136. ret = dma_cookie_status(chan, cookie, txstate);
  2137. if (ret != DMA_COMPLETE && txstate)
  2138. dma_set_residue(txstate, stedma40_residue(chan));
  2139. if (d40_is_paused(d40c))
  2140. ret = DMA_PAUSED;
  2141. return ret;
  2142. }
  2143. static void d40_issue_pending(struct dma_chan *chan)
  2144. {
  2145. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2146. unsigned long flags;
  2147. if (d40c->phy_chan == NULL) {
  2148. chan_err(d40c, "Channel is not allocated!\n");
  2149. return;
  2150. }
  2151. spin_lock_irqsave(&d40c->lock, flags);
  2152. list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
  2153. /* Busy means that queued jobs are already being processed */
  2154. if (!d40c->busy)
  2155. (void) d40_queue_start(d40c);
  2156. spin_unlock_irqrestore(&d40c->lock, flags);
  2157. }
  2158. static int d40_terminate_all(struct dma_chan *chan)
  2159. {
  2160. unsigned long flags;
  2161. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2162. int ret;
  2163. if (d40c->phy_chan == NULL) {
  2164. chan_err(d40c, "Channel is not allocated!\n");
  2165. return -EINVAL;
  2166. }
  2167. spin_lock_irqsave(&d40c->lock, flags);
  2168. pm_runtime_get_sync(d40c->base->dev);
  2169. ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
  2170. if (ret)
  2171. chan_err(d40c, "Failed to stop channel\n");
  2172. d40_term_all(d40c);
  2173. pm_runtime_mark_last_busy(d40c->base->dev);
  2174. pm_runtime_put_autosuspend(d40c->base->dev);
  2175. if (d40c->busy) {
  2176. pm_runtime_mark_last_busy(d40c->base->dev);
  2177. pm_runtime_put_autosuspend(d40c->base->dev);
  2178. }
  2179. d40c->busy = false;
  2180. spin_unlock_irqrestore(&d40c->lock, flags);
  2181. return 0;
  2182. }
  2183. static int
  2184. dma40_config_to_halfchannel(struct d40_chan *d40c,
  2185. struct stedma40_half_channel_info *info,
  2186. u32 maxburst)
  2187. {
  2188. int psize;
  2189. if (chan_is_logical(d40c)) {
  2190. if (maxburst >= 16)
  2191. psize = STEDMA40_PSIZE_LOG_16;
  2192. else if (maxburst >= 8)
  2193. psize = STEDMA40_PSIZE_LOG_8;
  2194. else if (maxburst >= 4)
  2195. psize = STEDMA40_PSIZE_LOG_4;
  2196. else
  2197. psize = STEDMA40_PSIZE_LOG_1;
  2198. } else {
  2199. if (maxburst >= 16)
  2200. psize = STEDMA40_PSIZE_PHY_16;
  2201. else if (maxburst >= 8)
  2202. psize = STEDMA40_PSIZE_PHY_8;
  2203. else if (maxburst >= 4)
  2204. psize = STEDMA40_PSIZE_PHY_4;
  2205. else
  2206. psize = STEDMA40_PSIZE_PHY_1;
  2207. }
  2208. info->psize = psize;
  2209. info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
  2210. return 0;
  2211. }
  2212. static int d40_set_runtime_config(struct dma_chan *chan,
  2213. struct dma_slave_config *config)
  2214. {
  2215. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2216. memcpy(&d40c->slave_config, config, sizeof(*config));
  2217. return 0;
  2218. }
  2219. /* Runtime reconfiguration extension */
  2220. static int d40_set_runtime_config_write(struct dma_chan *chan,
  2221. struct dma_slave_config *config,
  2222. enum dma_transfer_direction direction)
  2223. {
  2224. struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
  2225. struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
  2226. enum dma_slave_buswidth src_addr_width, dst_addr_width;
  2227. dma_addr_t config_addr;
  2228. u32 src_maxburst, dst_maxburst;
  2229. int ret;
  2230. if (d40c->phy_chan == NULL) {
  2231. chan_err(d40c, "Channel is not allocated!\n");
  2232. return -EINVAL;
  2233. }
  2234. src_addr_width = config->src_addr_width;
  2235. src_maxburst = config->src_maxburst;
  2236. dst_addr_width = config->dst_addr_width;
  2237. dst_maxburst = config->dst_maxburst;
  2238. if (direction == DMA_DEV_TO_MEM) {
  2239. config_addr = config->src_addr;
  2240. if (cfg->dir != DMA_DEV_TO_MEM)
  2241. dev_dbg(d40c->base->dev,
  2242. "channel was not configured for peripheral "
  2243. "to memory transfer (%d) overriding\n",
  2244. cfg->dir);
  2245. cfg->dir = DMA_DEV_TO_MEM;
  2246. /* Configure the memory side */
  2247. if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  2248. dst_addr_width = src_addr_width;
  2249. if (dst_maxburst == 0)
  2250. dst_maxburst = src_maxburst;
  2251. } else if (direction == DMA_MEM_TO_DEV) {
  2252. config_addr = config->dst_addr;
  2253. if (cfg->dir != DMA_MEM_TO_DEV)
  2254. dev_dbg(d40c->base->dev,
  2255. "channel was not configured for memory "
  2256. "to peripheral transfer (%d) overriding\n",
  2257. cfg->dir);
  2258. cfg->dir = DMA_MEM_TO_DEV;
  2259. /* Configure the memory side */
  2260. if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  2261. src_addr_width = dst_addr_width;
  2262. if (src_maxburst == 0)
  2263. src_maxburst = dst_maxburst;
  2264. } else {
  2265. dev_err(d40c->base->dev,
  2266. "unrecognized channel direction %d\n",
  2267. direction);
  2268. return -EINVAL;
  2269. }
  2270. if (config_addr <= 0) {
  2271. dev_err(d40c->base->dev, "no address supplied\n");
  2272. return -EINVAL;
  2273. }
  2274. if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
  2275. dev_err(d40c->base->dev,
  2276. "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
  2277. src_maxburst,
  2278. src_addr_width,
  2279. dst_maxburst,
  2280. dst_addr_width);
  2281. return -EINVAL;
  2282. }
  2283. if (src_maxburst > 16) {
  2284. src_maxburst = 16;
  2285. dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
  2286. } else if (dst_maxburst > 16) {
  2287. dst_maxburst = 16;
  2288. src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
  2289. }
  2290. /* Only valid widths are; 1, 2, 4 and 8. */
  2291. if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
  2292. src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
  2293. dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
  2294. dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
  2295. !is_power_of_2(src_addr_width) ||
  2296. !is_power_of_2(dst_addr_width))
  2297. return -EINVAL;
  2298. cfg->src_info.data_width = src_addr_width;
  2299. cfg->dst_info.data_width = dst_addr_width;
  2300. ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
  2301. src_maxburst);
  2302. if (ret)
  2303. return ret;
  2304. ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
  2305. dst_maxburst);
  2306. if (ret)
  2307. return ret;
  2308. /* Fill in register values */
  2309. if (chan_is_logical(d40c))
  2310. d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
  2311. else
  2312. d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
  2313. /* These settings will take precedence later */
  2314. d40c->runtime_addr = config_addr;
  2315. d40c->runtime_direction = direction;
  2316. dev_dbg(d40c->base->dev,
  2317. "configured channel %s for %s, data width %d/%d, "
  2318. "maxburst %d/%d elements, LE, no flow control\n",
  2319. dma_chan_name(chan),
  2320. (direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
  2321. src_addr_width, dst_addr_width,
  2322. src_maxburst, dst_maxburst);
  2323. return 0;
  2324. }
  2325. /* Initialization functions */
  2326. static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
  2327. struct d40_chan *chans, int offset,
  2328. int num_chans)
  2329. {
  2330. int i = 0;
  2331. struct d40_chan *d40c;
  2332. INIT_LIST_HEAD(&dma->channels);
  2333. for (i = offset; i < offset + num_chans; i++) {
  2334. d40c = &chans[i];
  2335. d40c->base = base;
  2336. d40c->chan.device = dma;
  2337. spin_lock_init(&d40c->lock);
  2338. d40c->log_num = D40_PHY_CHAN;
  2339. INIT_LIST_HEAD(&d40c->done);
  2340. INIT_LIST_HEAD(&d40c->active);
  2341. INIT_LIST_HEAD(&d40c->queue);
  2342. INIT_LIST_HEAD(&d40c->pending_queue);
  2343. INIT_LIST_HEAD(&d40c->client);
  2344. INIT_LIST_HEAD(&d40c->prepare_queue);
  2345. tasklet_setup(&d40c->tasklet, dma_tasklet);
  2346. list_add_tail(&d40c->chan.device_node,
  2347. &dma->channels);
  2348. }
  2349. }
  2350. static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
  2351. {
  2352. if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) {
  2353. dev->device_prep_slave_sg = d40_prep_slave_sg;
  2354. dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  2355. }
  2356. if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
  2357. dev->device_prep_dma_memcpy = d40_prep_memcpy;
  2358. dev->directions = BIT(DMA_MEM_TO_MEM);
  2359. /*
  2360. * This controller can only access address at even
  2361. * 32bit boundaries, i.e. 2^2
  2362. */
  2363. dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
  2364. }
  2365. if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
  2366. dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
  2367. dev->device_alloc_chan_resources = d40_alloc_chan_resources;
  2368. dev->device_free_chan_resources = d40_free_chan_resources;
  2369. dev->device_issue_pending = d40_issue_pending;
  2370. dev->device_tx_status = d40_tx_status;
  2371. dev->device_config = d40_set_runtime_config;
  2372. dev->device_pause = d40_pause;
  2373. dev->device_resume = d40_resume;
  2374. dev->device_terminate_all = d40_terminate_all;
  2375. dev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  2376. dev->dev = base->dev;
  2377. }
  2378. static int __init d40_dmaengine_init(struct d40_base *base,
  2379. int num_reserved_chans)
  2380. {
  2381. int err ;
  2382. d40_chan_init(base, &base->dma_slave, base->log_chans,
  2383. 0, base->num_log_chans);
  2384. dma_cap_zero(base->dma_slave.cap_mask);
  2385. dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
  2386. dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
  2387. d40_ops_init(base, &base->dma_slave);
  2388. err = dmaenginem_async_device_register(&base->dma_slave);
  2389. if (err) {
  2390. d40_err(base->dev, "Failed to register slave channels\n");
  2391. goto exit;
  2392. }
  2393. d40_chan_init(base, &base->dma_memcpy, base->log_chans,
  2394. base->num_log_chans, base->num_memcpy_chans);
  2395. dma_cap_zero(base->dma_memcpy.cap_mask);
  2396. dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
  2397. d40_ops_init(base, &base->dma_memcpy);
  2398. err = dmaenginem_async_device_register(&base->dma_memcpy);
  2399. if (err) {
  2400. d40_err(base->dev,
  2401. "Failed to register memcpy only channels\n");
  2402. goto exit;
  2403. }
  2404. d40_chan_init(base, &base->dma_both, base->phy_chans,
  2405. 0, num_reserved_chans);
  2406. dma_cap_zero(base->dma_both.cap_mask);
  2407. dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
  2408. dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
  2409. dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
  2410. d40_ops_init(base, &base->dma_both);
  2411. err = dmaenginem_async_device_register(&base->dma_both);
  2412. if (err) {
  2413. d40_err(base->dev,
  2414. "Failed to register logical and physical capable channels\n");
  2415. goto exit;
  2416. }
  2417. return 0;
  2418. exit:
  2419. return err;
  2420. }
  2421. /* Suspend resume functionality */
  2422. #ifdef CONFIG_PM_SLEEP
  2423. static int dma40_suspend(struct device *dev)
  2424. {
  2425. struct d40_base *base = dev_get_drvdata(dev);
  2426. int ret;
  2427. ret = pm_runtime_force_suspend(dev);
  2428. if (ret)
  2429. return ret;
  2430. if (base->lcpa_regulator)
  2431. ret = regulator_disable(base->lcpa_regulator);
  2432. return ret;
  2433. }
  2434. static int dma40_resume(struct device *dev)
  2435. {
  2436. struct d40_base *base = dev_get_drvdata(dev);
  2437. int ret = 0;
  2438. if (base->lcpa_regulator) {
  2439. ret = regulator_enable(base->lcpa_regulator);
  2440. if (ret)
  2441. return ret;
  2442. }
  2443. return pm_runtime_force_resume(dev);
  2444. }
  2445. #endif
  2446. #ifdef CONFIG_PM
  2447. static void dma40_backup(void __iomem *baseaddr, u32 *backup,
  2448. u32 *regaddr, int num, bool save)
  2449. {
  2450. int i;
  2451. for (i = 0; i < num; i++) {
  2452. void __iomem *addr = baseaddr + regaddr[i];
  2453. if (save)
  2454. backup[i] = readl_relaxed(addr);
  2455. else
  2456. writel_relaxed(backup[i], addr);
  2457. }
  2458. }
  2459. static void d40_save_restore_registers(struct d40_base *base, bool save)
  2460. {
  2461. int i;
  2462. /* Save/Restore channel specific registers */
  2463. for (i = 0; i < base->num_phy_chans; i++) {
  2464. void __iomem *addr;
  2465. int idx;
  2466. if (base->phy_res[i].reserved)
  2467. continue;
  2468. addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
  2469. idx = i * ARRAY_SIZE(d40_backup_regs_chan);
  2470. dma40_backup(addr, &base->reg_val_backup_chan[idx],
  2471. d40_backup_regs_chan,
  2472. ARRAY_SIZE(d40_backup_regs_chan),
  2473. save);
  2474. }
  2475. /* Save/Restore global registers */
  2476. dma40_backup(base->virtbase, base->reg_val_backup,
  2477. d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
  2478. save);
  2479. /* Save/Restore registers only existing on dma40 v3 and later */
  2480. if (base->gen_dmac.backup)
  2481. dma40_backup(base->virtbase, base->reg_val_backup_v4,
  2482. base->gen_dmac.backup,
  2483. base->gen_dmac.backup_size,
  2484. save);
  2485. }
  2486. static int dma40_runtime_suspend(struct device *dev)
  2487. {
  2488. struct d40_base *base = dev_get_drvdata(dev);
  2489. d40_save_restore_registers(base, true);
  2490. /* Don't disable/enable clocks for v1 due to HW bugs */
  2491. if (base->rev != 1)
  2492. writel_relaxed(base->gcc_pwr_off_mask,
  2493. base->virtbase + D40_DREG_GCC);
  2494. return 0;
  2495. }
  2496. static int dma40_runtime_resume(struct device *dev)
  2497. {
  2498. struct d40_base *base = dev_get_drvdata(dev);
  2499. d40_save_restore_registers(base, false);
  2500. writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
  2501. base->virtbase + D40_DREG_GCC);
  2502. return 0;
  2503. }
  2504. #endif
  2505. static const struct dev_pm_ops dma40_pm_ops = {
  2506. SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume)
  2507. SET_RUNTIME_PM_OPS(dma40_runtime_suspend,
  2508. dma40_runtime_resume,
  2509. NULL)
  2510. };
  2511. /* Initialization functions. */
  2512. static int __init d40_phy_res_init(struct d40_base *base)
  2513. {
  2514. int i;
  2515. int num_phy_chans_avail = 0;
  2516. u32 val[2];
  2517. int odd_even_bit = -2;
  2518. int gcc = D40_DREG_GCC_ENA;
  2519. val[0] = readl(base->virtbase + D40_DREG_PRSME);
  2520. val[1] = readl(base->virtbase + D40_DREG_PRSMO);
  2521. for (i = 0; i < base->num_phy_chans; i++) {
  2522. base->phy_res[i].num = i;
  2523. odd_even_bit += 2 * ((i % 2) == 0);
  2524. if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
  2525. /* Mark security only channels as occupied */
  2526. base->phy_res[i].allocated_src = D40_ALLOC_PHY;
  2527. base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
  2528. base->phy_res[i].reserved = true;
  2529. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
  2530. D40_DREG_GCC_SRC);
  2531. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
  2532. D40_DREG_GCC_DST);
  2533. } else {
  2534. base->phy_res[i].allocated_src = D40_ALLOC_FREE;
  2535. base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
  2536. base->phy_res[i].reserved = false;
  2537. num_phy_chans_avail++;
  2538. }
  2539. spin_lock_init(&base->phy_res[i].lock);
  2540. }
  2541. /* Mark disabled channels as occupied */
  2542. for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
  2543. int chan = base->plat_data->disabled_channels[i];
  2544. base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
  2545. base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
  2546. base->phy_res[chan].reserved = true;
  2547. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
  2548. D40_DREG_GCC_SRC);
  2549. gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
  2550. D40_DREG_GCC_DST);
  2551. num_phy_chans_avail--;
  2552. }
  2553. /* Mark soft_lli channels */
  2554. for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
  2555. int chan = base->plat_data->soft_lli_chans[i];
  2556. base->phy_res[chan].use_soft_lli = true;
  2557. }
  2558. dev_info(base->dev, "%d of %d physical DMA channels available\n",
  2559. num_phy_chans_avail, base->num_phy_chans);
  2560. /* Verify settings extended vs standard */
  2561. val[0] = readl(base->virtbase + D40_DREG_PRTYP);
  2562. for (i = 0; i < base->num_phy_chans; i++) {
  2563. if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
  2564. (val[0] & 0x3) != 1)
  2565. dev_info(base->dev,
  2566. "[%s] INFO: channel %d is misconfigured (%d)\n",
  2567. __func__, i, val[0] & 0x3);
  2568. val[0] = val[0] >> 2;
  2569. }
  2570. /*
  2571. * To keep things simple, Enable all clocks initially.
  2572. * The clocks will get managed later post channel allocation.
  2573. * The clocks for the event lines on which reserved channels exists
  2574. * are not managed here.
  2575. */
  2576. writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
  2577. base->gcc_pwr_off_mask = gcc;
  2578. return num_phy_chans_avail;
  2579. }
  2580. static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
  2581. {
  2582. struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
  2583. struct clk *clk;
  2584. void __iomem *virtbase;
  2585. struct resource *res;
  2586. struct d40_base *base;
  2587. int num_log_chans;
  2588. int num_phy_chans;
  2589. int num_memcpy_chans;
  2590. int clk_ret = -EINVAL;
  2591. int i;
  2592. u32 pid;
  2593. u32 cid;
  2594. u8 rev;
  2595. clk = clk_get(&pdev->dev, NULL);
  2596. if (IS_ERR(clk)) {
  2597. d40_err(&pdev->dev, "No matching clock found\n");
  2598. goto check_prepare_enabled;
  2599. }
  2600. clk_ret = clk_prepare_enable(clk);
  2601. if (clk_ret) {
  2602. d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
  2603. goto disable_unprepare;
  2604. }
  2605. /* Get IO for DMAC base address */
  2606. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
  2607. if (!res)
  2608. goto disable_unprepare;
  2609. if (request_mem_region(res->start, resource_size(res),
  2610. D40_NAME " I/O base") == NULL)
  2611. goto release_region;
  2612. virtbase = ioremap(res->start, resource_size(res));
  2613. if (!virtbase)
  2614. goto release_region;
  2615. /* This is just a regular AMBA PrimeCell ID actually */
  2616. for (pid = 0, i = 0; i < 4; i++)
  2617. pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
  2618. & 255) << (i * 8);
  2619. for (cid = 0, i = 0; i < 4; i++)
  2620. cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
  2621. & 255) << (i * 8);
  2622. if (cid != AMBA_CID) {
  2623. d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
  2624. goto unmap_io;
  2625. }
  2626. if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
  2627. d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
  2628. AMBA_MANF_BITS(pid),
  2629. AMBA_VENDOR_ST);
  2630. goto unmap_io;
  2631. }
  2632. /*
  2633. * HW revision:
  2634. * DB8500ed has revision 0
  2635. * ? has revision 1
  2636. * DB8500v1 has revision 2
  2637. * DB8500v2 has revision 3
  2638. * AP9540v1 has revision 4
  2639. * DB8540v1 has revision 4
  2640. */
  2641. rev = AMBA_REV_BITS(pid);
  2642. if (rev < 2) {
  2643. d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
  2644. goto unmap_io;
  2645. }
  2646. /* The number of physical channels on this HW */
  2647. if (plat_data->num_of_phy_chans)
  2648. num_phy_chans = plat_data->num_of_phy_chans;
  2649. else
  2650. num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
  2651. /* The number of channels used for memcpy */
  2652. if (plat_data->num_of_memcpy_chans)
  2653. num_memcpy_chans = plat_data->num_of_memcpy_chans;
  2654. else
  2655. num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
  2656. num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
  2657. dev_info(&pdev->dev,
  2658. "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
  2659. rev, &res->start, num_phy_chans, num_log_chans);
  2660. base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
  2661. (num_phy_chans + num_log_chans + num_memcpy_chans) *
  2662. sizeof(struct d40_chan), GFP_KERNEL);
  2663. if (base == NULL)
  2664. goto unmap_io;
  2665. base->rev = rev;
  2666. base->clk = clk;
  2667. base->num_memcpy_chans = num_memcpy_chans;
  2668. base->num_phy_chans = num_phy_chans;
  2669. base->num_log_chans = num_log_chans;
  2670. base->phy_start = res->start;
  2671. base->phy_size = resource_size(res);
  2672. base->virtbase = virtbase;
  2673. base->plat_data = plat_data;
  2674. base->dev = &pdev->dev;
  2675. base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
  2676. base->log_chans = &base->phy_chans[num_phy_chans];
  2677. if (base->plat_data->num_of_phy_chans == 14) {
  2678. base->gen_dmac.backup = d40_backup_regs_v4b;
  2679. base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
  2680. base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
  2681. base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
  2682. base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
  2683. base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
  2684. base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
  2685. base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
  2686. base->gen_dmac.il = il_v4b;
  2687. base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
  2688. base->gen_dmac.init_reg = dma_init_reg_v4b;
  2689. base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
  2690. } else {
  2691. if (base->rev >= 3) {
  2692. base->gen_dmac.backup = d40_backup_regs_v4a;
  2693. base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
  2694. }
  2695. base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
  2696. base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
  2697. base->gen_dmac.realtime_en = D40_DREG_RSEG1;
  2698. base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
  2699. base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
  2700. base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
  2701. base->gen_dmac.il = il_v4a;
  2702. base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
  2703. base->gen_dmac.init_reg = dma_init_reg_v4a;
  2704. base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
  2705. }
  2706. base->phy_res = kcalloc(num_phy_chans,
  2707. sizeof(*base->phy_res),
  2708. GFP_KERNEL);
  2709. if (!base->phy_res)
  2710. goto free_base;
  2711. base->lookup_phy_chans = kcalloc(num_phy_chans,
  2712. sizeof(*base->lookup_phy_chans),
  2713. GFP_KERNEL);
  2714. if (!base->lookup_phy_chans)
  2715. goto free_phy_res;
  2716. base->lookup_log_chans = kcalloc(num_log_chans,
  2717. sizeof(*base->lookup_log_chans),
  2718. GFP_KERNEL);
  2719. if (!base->lookup_log_chans)
  2720. goto free_phy_chans;
  2721. base->reg_val_backup_chan = kmalloc_array(base->num_phy_chans,
  2722. sizeof(d40_backup_regs_chan),
  2723. GFP_KERNEL);
  2724. if (!base->reg_val_backup_chan)
  2725. goto free_log_chans;
  2726. base->lcla_pool.alloc_map = kcalloc(num_phy_chans
  2727. * D40_LCLA_LINK_PER_EVENT_GRP,
  2728. sizeof(*base->lcla_pool.alloc_map),
  2729. GFP_KERNEL);
  2730. if (!base->lcla_pool.alloc_map)
  2731. goto free_backup_chan;
  2732. base->regs_interrupt = kmalloc_array(base->gen_dmac.il_size,
  2733. sizeof(*base->regs_interrupt),
  2734. GFP_KERNEL);
  2735. if (!base->regs_interrupt)
  2736. goto free_map;
  2737. base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
  2738. 0, SLAB_HWCACHE_ALIGN,
  2739. NULL);
  2740. if (base->desc_slab == NULL)
  2741. goto free_regs;
  2742. return base;
  2743. free_regs:
  2744. kfree(base->regs_interrupt);
  2745. free_map:
  2746. kfree(base->lcla_pool.alloc_map);
  2747. free_backup_chan:
  2748. kfree(base->reg_val_backup_chan);
  2749. free_log_chans:
  2750. kfree(base->lookup_log_chans);
  2751. free_phy_chans:
  2752. kfree(base->lookup_phy_chans);
  2753. free_phy_res:
  2754. kfree(base->phy_res);
  2755. free_base:
  2756. kfree(base);
  2757. unmap_io:
  2758. iounmap(virtbase);
  2759. release_region:
  2760. release_mem_region(res->start, resource_size(res));
  2761. check_prepare_enabled:
  2762. if (!clk_ret)
  2763. disable_unprepare:
  2764. clk_disable_unprepare(clk);
  2765. if (!IS_ERR(clk))
  2766. clk_put(clk);
  2767. return NULL;
  2768. }
  2769. static void __init d40_hw_init(struct d40_base *base)
  2770. {
  2771. int i;
  2772. u32 prmseo[2] = {0, 0};
  2773. u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
  2774. u32 pcmis = 0;
  2775. u32 pcicr = 0;
  2776. struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
  2777. u32 reg_size = base->gen_dmac.init_reg_size;
  2778. for (i = 0; i < reg_size; i++)
  2779. writel(dma_init_reg[i].val,
  2780. base->virtbase + dma_init_reg[i].reg);
  2781. /* Configure all our dma channels to default settings */
  2782. for (i = 0; i < base->num_phy_chans; i++) {
  2783. activeo[i % 2] = activeo[i % 2] << 2;
  2784. if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
  2785. == D40_ALLOC_PHY) {
  2786. activeo[i % 2] |= 3;
  2787. continue;
  2788. }
  2789. /* Enable interrupt # */
  2790. pcmis = (pcmis << 1) | 1;
  2791. /* Clear interrupt # */
  2792. pcicr = (pcicr << 1) | 1;
  2793. /* Set channel to physical mode */
  2794. prmseo[i % 2] = prmseo[i % 2] << 2;
  2795. prmseo[i % 2] |= 1;
  2796. }
  2797. writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
  2798. writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
  2799. writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
  2800. writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
  2801. /* Write which interrupt to enable */
  2802. writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
  2803. /* Write which interrupt to clear */
  2804. writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
  2805. /* These are __initdata and cannot be accessed after init */
  2806. base->gen_dmac.init_reg = NULL;
  2807. base->gen_dmac.init_reg_size = 0;
  2808. }
  2809. static int __init d40_lcla_allocate(struct d40_base *base)
  2810. {
  2811. struct d40_lcla_pool *pool = &base->lcla_pool;
  2812. unsigned long *page_list;
  2813. int i, j;
  2814. int ret;
  2815. /*
  2816. * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
  2817. * To full fill this hardware requirement without wasting 256 kb
  2818. * we allocate pages until we get an aligned one.
  2819. */
  2820. page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS,
  2821. sizeof(*page_list),
  2822. GFP_KERNEL);
  2823. if (!page_list)
  2824. return -ENOMEM;
  2825. /* Calculating how many pages that are required */
  2826. base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
  2827. for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
  2828. page_list[i] = __get_free_pages(GFP_KERNEL,
  2829. base->lcla_pool.pages);
  2830. if (!page_list[i]) {
  2831. d40_err(base->dev, "Failed to allocate %d pages.\n",
  2832. base->lcla_pool.pages);
  2833. ret = -ENOMEM;
  2834. for (j = 0; j < i; j++)
  2835. free_pages(page_list[j], base->lcla_pool.pages);
  2836. goto free_page_list;
  2837. }
  2838. if ((virt_to_phys((void *)page_list[i]) &
  2839. (LCLA_ALIGNMENT - 1)) == 0)
  2840. break;
  2841. }
  2842. for (j = 0; j < i; j++)
  2843. free_pages(page_list[j], base->lcla_pool.pages);
  2844. if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
  2845. base->lcla_pool.base = (void *)page_list[i];
  2846. } else {
  2847. /*
  2848. * After many attempts and no succees with finding the correct
  2849. * alignment, try with allocating a big buffer.
  2850. */
  2851. dev_warn(base->dev,
  2852. "[%s] Failed to get %d pages @ 18 bit align.\n",
  2853. __func__, base->lcla_pool.pages);
  2854. base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
  2855. base->num_phy_chans +
  2856. LCLA_ALIGNMENT,
  2857. GFP_KERNEL);
  2858. if (!base->lcla_pool.base_unaligned) {
  2859. ret = -ENOMEM;
  2860. goto free_page_list;
  2861. }
  2862. base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
  2863. LCLA_ALIGNMENT);
  2864. }
  2865. pool->dma_addr = dma_map_single(base->dev, pool->base,
  2866. SZ_1K * base->num_phy_chans,
  2867. DMA_TO_DEVICE);
  2868. if (dma_mapping_error(base->dev, pool->dma_addr)) {
  2869. pool->dma_addr = 0;
  2870. ret = -ENOMEM;
  2871. goto free_page_list;
  2872. }
  2873. writel(virt_to_phys(base->lcla_pool.base),
  2874. base->virtbase + D40_DREG_LCLA);
  2875. ret = 0;
  2876. free_page_list:
  2877. kfree(page_list);
  2878. return ret;
  2879. }
  2880. static int __init d40_of_probe(struct platform_device *pdev,
  2881. struct device_node *np)
  2882. {
  2883. struct stedma40_platform_data *pdata;
  2884. int num_phy = 0, num_memcpy = 0, num_disabled = 0;
  2885. const __be32 *list;
  2886. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  2887. if (!pdata)
  2888. return -ENOMEM;
  2889. /* If absent this value will be obtained from h/w. */
  2890. of_property_read_u32(np, "dma-channels", &num_phy);
  2891. if (num_phy > 0)
  2892. pdata->num_of_phy_chans = num_phy;
  2893. list = of_get_property(np, "memcpy-channels", &num_memcpy);
  2894. num_memcpy /= sizeof(*list);
  2895. if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
  2896. d40_err(&pdev->dev,
  2897. "Invalid number of memcpy channels specified (%d)\n",
  2898. num_memcpy);
  2899. return -EINVAL;
  2900. }
  2901. pdata->num_of_memcpy_chans = num_memcpy;
  2902. of_property_read_u32_array(np, "memcpy-channels",
  2903. dma40_memcpy_channels,
  2904. num_memcpy);
  2905. list = of_get_property(np, "disabled-channels", &num_disabled);
  2906. num_disabled /= sizeof(*list);
  2907. if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
  2908. d40_err(&pdev->dev,
  2909. "Invalid number of disabled channels specified (%d)\n",
  2910. num_disabled);
  2911. return -EINVAL;
  2912. }
  2913. of_property_read_u32_array(np, "disabled-channels",
  2914. pdata->disabled_channels,
  2915. num_disabled);
  2916. pdata->disabled_channels[num_disabled] = -1;
  2917. pdev->dev.platform_data = pdata;
  2918. return 0;
  2919. }
  2920. static int __init d40_probe(struct platform_device *pdev)
  2921. {
  2922. struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
  2923. struct device_node *np = pdev->dev.of_node;
  2924. int ret = -ENOENT;
  2925. struct d40_base *base;
  2926. struct resource *res;
  2927. int num_reserved_chans;
  2928. u32 val;
  2929. if (!plat_data) {
  2930. if (np) {
  2931. if (d40_of_probe(pdev, np)) {
  2932. ret = -ENOMEM;
  2933. goto report_failure;
  2934. }
  2935. } else {
  2936. d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
  2937. goto report_failure;
  2938. }
  2939. }
  2940. base = d40_hw_detect_init(pdev);
  2941. if (!base)
  2942. goto report_failure;
  2943. num_reserved_chans = d40_phy_res_init(base);
  2944. platform_set_drvdata(pdev, base);
  2945. spin_lock_init(&base->interrupt_lock);
  2946. spin_lock_init(&base->execmd_lock);
  2947. /* Get IO for logical channel parameter address */
  2948. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
  2949. if (!res) {
  2950. ret = -ENOENT;
  2951. d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
  2952. goto destroy_cache;
  2953. }
  2954. base->lcpa_size = resource_size(res);
  2955. base->phy_lcpa = res->start;
  2956. if (request_mem_region(res->start, resource_size(res),
  2957. D40_NAME " I/O lcpa") == NULL) {
  2958. ret = -EBUSY;
  2959. d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
  2960. goto destroy_cache;
  2961. }
  2962. /* We make use of ESRAM memory for this. */
  2963. val = readl(base->virtbase + D40_DREG_LCPA);
  2964. if (res->start != val && val != 0) {
  2965. dev_warn(&pdev->dev,
  2966. "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
  2967. __func__, val, &res->start);
  2968. } else
  2969. writel(res->start, base->virtbase + D40_DREG_LCPA);
  2970. base->lcpa_base = ioremap(res->start, resource_size(res));
  2971. if (!base->lcpa_base) {
  2972. ret = -ENOMEM;
  2973. d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
  2974. goto destroy_cache;
  2975. }
  2976. /* If lcla has to be located in ESRAM we don't need to allocate */
  2977. if (base->plat_data->use_esram_lcla) {
  2978. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  2979. "lcla_esram");
  2980. if (!res) {
  2981. ret = -ENOENT;
  2982. d40_err(&pdev->dev,
  2983. "No \"lcla_esram\" memory resource\n");
  2984. goto destroy_cache;
  2985. }
  2986. base->lcla_pool.base = ioremap(res->start,
  2987. resource_size(res));
  2988. if (!base->lcla_pool.base) {
  2989. ret = -ENOMEM;
  2990. d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
  2991. goto destroy_cache;
  2992. }
  2993. writel(res->start, base->virtbase + D40_DREG_LCLA);
  2994. } else {
  2995. ret = d40_lcla_allocate(base);
  2996. if (ret) {
  2997. d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
  2998. goto destroy_cache;
  2999. }
  3000. }
  3001. spin_lock_init(&base->lcla_pool.lock);
  3002. base->irq = platform_get_irq(pdev, 0);
  3003. ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
  3004. if (ret) {
  3005. d40_err(&pdev->dev, "No IRQ defined\n");
  3006. goto destroy_cache;
  3007. }
  3008. if (base->plat_data->use_esram_lcla) {
  3009. base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
  3010. if (IS_ERR(base->lcpa_regulator)) {
  3011. d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
  3012. ret = PTR_ERR(base->lcpa_regulator);
  3013. base->lcpa_regulator = NULL;
  3014. goto destroy_cache;
  3015. }
  3016. ret = regulator_enable(base->lcpa_regulator);
  3017. if (ret) {
  3018. d40_err(&pdev->dev,
  3019. "Failed to enable lcpa_regulator\n");
  3020. regulator_put(base->lcpa_regulator);
  3021. base->lcpa_regulator = NULL;
  3022. goto destroy_cache;
  3023. }
  3024. }
  3025. writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
  3026. pm_runtime_irq_safe(base->dev);
  3027. pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
  3028. pm_runtime_use_autosuspend(base->dev);
  3029. pm_runtime_mark_last_busy(base->dev);
  3030. pm_runtime_set_active(base->dev);
  3031. pm_runtime_enable(base->dev);
  3032. ret = d40_dmaengine_init(base, num_reserved_chans);
  3033. if (ret)
  3034. goto destroy_cache;
  3035. ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
  3036. if (ret) {
  3037. d40_err(&pdev->dev, "Failed to set dma max seg size\n");
  3038. goto destroy_cache;
  3039. }
  3040. d40_hw_init(base);
  3041. if (np) {
  3042. ret = of_dma_controller_register(np, d40_xlate, NULL);
  3043. if (ret)
  3044. dev_err(&pdev->dev,
  3045. "could not register of_dma_controller\n");
  3046. }
  3047. dev_info(base->dev, "initialized\n");
  3048. return 0;
  3049. destroy_cache:
  3050. kmem_cache_destroy(base->desc_slab);
  3051. if (base->virtbase)
  3052. iounmap(base->virtbase);
  3053. if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
  3054. iounmap(base->lcla_pool.base);
  3055. base->lcla_pool.base = NULL;
  3056. }
  3057. if (base->lcla_pool.dma_addr)
  3058. dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
  3059. SZ_1K * base->num_phy_chans,
  3060. DMA_TO_DEVICE);
  3061. if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
  3062. free_pages((unsigned long)base->lcla_pool.base,
  3063. base->lcla_pool.pages);
  3064. kfree(base->lcla_pool.base_unaligned);
  3065. if (base->lcpa_base)
  3066. iounmap(base->lcpa_base);
  3067. if (base->phy_lcpa)
  3068. release_mem_region(base->phy_lcpa,
  3069. base->lcpa_size);
  3070. if (base->phy_start)
  3071. release_mem_region(base->phy_start,
  3072. base->phy_size);
  3073. if (base->clk) {
  3074. clk_disable_unprepare(base->clk);
  3075. clk_put(base->clk);
  3076. }
  3077. if (base->lcpa_regulator) {
  3078. regulator_disable(base->lcpa_regulator);
  3079. regulator_put(base->lcpa_regulator);
  3080. }
  3081. kfree(base->lcla_pool.alloc_map);
  3082. kfree(base->lookup_log_chans);
  3083. kfree(base->lookup_phy_chans);
  3084. kfree(base->phy_res);
  3085. kfree(base);
  3086. report_failure:
  3087. d40_err(&pdev->dev, "probe failed\n");
  3088. return ret;
  3089. }
  3090. static const struct of_device_id d40_match[] = {
  3091. { .compatible = "stericsson,dma40", },
  3092. {}
  3093. };
  3094. static struct platform_driver d40_driver = {
  3095. .driver = {
  3096. .name = D40_NAME,
  3097. .pm = &dma40_pm_ops,
  3098. .of_match_table = d40_match,
  3099. },
  3100. };
  3101. static int __init stedma40_init(void)
  3102. {
  3103. return platform_driver_probe(&d40_driver, d40_probe);
  3104. }
  3105. subsys_initcall(stedma40_init);