st_fdma.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * DMA driver header for STMicroelectronics STi FDMA controller
  4. *
  5. * Copyright (C) 2014 STMicroelectronics
  6. *
  7. * Author: Ludovic Barre <Ludovic.barre@st.com>
  8. */
  9. #ifndef __DMA_ST_FDMA_H
  10. #define __DMA_ST_FDMA_H
  11. #include <linux/dmaengine.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/io.h>
  14. #include <linux/remoteproc/st_slim_rproc.h>
  15. #include "virt-dma.h"
  16. #define ST_FDMA_NR_DREQS 32
  17. #define FW_NAME_SIZE 30
  18. #define DRIVER_NAME "st-fdma"
  19. /**
  20. * struct st_fdma_generic_node - Free running/paced generic node
  21. *
  22. * @length: Length in bytes of a line in a 2D mem to mem
  23. * @sstride: Stride, in bytes, between source lines in a 2D data move
  24. * @dstride: Stride, in bytes, between destination lines in a 2D data move
  25. */
  26. struct st_fdma_generic_node {
  27. u32 length;
  28. u32 sstride;
  29. u32 dstride;
  30. };
  31. /**
  32. * struct st_fdma_hw_node - Node structure used by fdma hw
  33. *
  34. * @next: Pointer to next node
  35. * @control: Transfer Control Parameters
  36. * @nbytes: Number of Bytes to read
  37. * @saddr: Source address
  38. * @daddr: Destination address
  39. *
  40. * @generic: generic node for free running/paced transfert type
  41. * 2 others transfert type are possible, but not yet implemented
  42. *
  43. * The NODE structures must be aligned to a 32 byte boundary
  44. */
  45. struct st_fdma_hw_node {
  46. u32 next;
  47. u32 control;
  48. u32 nbytes;
  49. u32 saddr;
  50. u32 daddr;
  51. union {
  52. struct st_fdma_generic_node generic;
  53. };
  54. } __aligned(32);
  55. /*
  56. * node control parameters
  57. */
  58. #define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
  59. #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
  60. #define FDMA_NODE_CTRL_REQ_MAP_DREQ(n) ((n)&FDMA_NODE_CTRL_REQ_MAP_MASK)
  61. #define FDMA_NODE_CTRL_REQ_MAP_EXT FDMA_NODE_CTRL_REQ_MAP_MASK
  62. #define FDMA_NODE_CTRL_SRC_MASK GENMASK(6, 5)
  63. #define FDMA_NODE_CTRL_SRC_STATIC BIT(5)
  64. #define FDMA_NODE_CTRL_SRC_INCR BIT(6)
  65. #define FDMA_NODE_CTRL_DST_MASK GENMASK(8, 7)
  66. #define FDMA_NODE_CTRL_DST_STATIC BIT(7)
  67. #define FDMA_NODE_CTRL_DST_INCR BIT(8)
  68. #define FDMA_NODE_CTRL_SECURE BIT(15)
  69. #define FDMA_NODE_CTRL_PAUSE_EON BIT(30)
  70. #define FDMA_NODE_CTRL_INT_EON BIT(31)
  71. /**
  72. * struct st_fdma_sw_node - descriptor structure for link list
  73. *
  74. * @pdesc: Physical address of desc
  75. * @node: link used for putting this into a channel queue
  76. */
  77. struct st_fdma_sw_node {
  78. dma_addr_t pdesc;
  79. struct st_fdma_hw_node *desc;
  80. };
  81. #define NAME_SZ 10
  82. struct st_fdma_driverdata {
  83. u32 id;
  84. char name[NAME_SZ];
  85. };
  86. struct st_fdma_desc {
  87. struct virt_dma_desc vdesc;
  88. struct st_fdma_chan *fchan;
  89. bool iscyclic;
  90. unsigned int n_nodes;
  91. struct st_fdma_sw_node node[];
  92. };
  93. enum st_fdma_type {
  94. ST_FDMA_TYPE_FREE_RUN,
  95. ST_FDMA_TYPE_PACED,
  96. };
  97. struct st_fdma_cfg {
  98. struct device_node *of_node;
  99. enum st_fdma_type type;
  100. dma_addr_t dev_addr;
  101. enum dma_transfer_direction dir;
  102. int req_line; /* request line */
  103. long req_ctrl; /* Request control */
  104. };
  105. struct st_fdma_chan {
  106. struct st_fdma_dev *fdev;
  107. struct dma_pool *node_pool;
  108. struct dma_slave_config scfg;
  109. struct st_fdma_cfg cfg;
  110. int dreq_line;
  111. struct virt_dma_chan vchan;
  112. struct st_fdma_desc *fdesc;
  113. enum dma_status status;
  114. };
  115. struct st_fdma_dev {
  116. struct device *dev;
  117. const struct st_fdma_driverdata *drvdata;
  118. struct dma_device dma_device;
  119. struct st_slim_rproc *slim_rproc;
  120. int irq;
  121. struct st_fdma_chan *chans;
  122. spinlock_t dreq_lock;
  123. unsigned long dreq_mask;
  124. u32 nr_channels;
  125. char fw_name[FW_NAME_SIZE];
  126. };
  127. /* Peripheral Registers*/
  128. #define FDMA_CMD_STA_OFST 0xFC0
  129. #define FDMA_CMD_SET_OFST 0xFC4
  130. #define FDMA_CMD_CLR_OFST 0xFC8
  131. #define FDMA_CMD_MASK_OFST 0xFCC
  132. #define FDMA_CMD_START(ch) (0x1 << (ch << 1))
  133. #define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
  134. #define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
  135. #define FDMA_INT_STA_OFST 0xFD0
  136. #define FDMA_INT_STA_CH 0x1
  137. #define FDMA_INT_STA_ERR 0x2
  138. #define FDMA_INT_SET_OFST 0xFD4
  139. #define FDMA_INT_CLR_OFST 0xFD8
  140. #define FDMA_INT_MASK_OFST 0xFDC
  141. #define fdma_read(fdev, name) \
  142. readl((fdev)->slim_rproc->peri + name)
  143. #define fdma_write(fdev, val, name) \
  144. writel((val), (fdev)->slim_rproc->peri + name)
  145. /* fchan interface (dmem) */
  146. #define FDMA_CH_CMD_OFST 0x200
  147. #define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)
  148. #define FDMA_CH_CMD_STA_IDLE (0x0)
  149. #define FDMA_CH_CMD_STA_START (0x1)
  150. #define FDMA_CH_CMD_STA_RUNNING (0x2)
  151. #define FDMA_CH_CMD_STA_PAUSED (0x3)
  152. #define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2)
  153. #define FDMA_CH_CMD_ERR_INT (0x0 << 2)
  154. #define FDMA_CH_CMD_ERR_NAND (0x1 << 2)
  155. #define FDMA_CH_CMD_ERR_MCHI (0x2 << 2)
  156. #define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5)
  157. #define fchan_read(fchan, name) \
  158. readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
  159. + (fchan)->vchan.chan.chan_id * 0x4 \
  160. + name)
  161. #define fchan_write(fchan, val, name) \
  162. writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
  163. + (fchan)->vchan.chan.chan_id * 0x4 \
  164. + name)
  165. /* req interface */
  166. #define FDMA_REQ_CTRL_OFST 0x240
  167. #define dreq_write(fchan, val, name) \
  168. writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
  169. + fchan->dreq_line * 0x04 \
  170. + name)
  171. /* node interface */
  172. #define FDMA_NODE_SZ 128
  173. #define FDMA_PTRN_OFST 0x800
  174. #define FDMA_CNTN_OFST 0x808
  175. #define FDMA_SADDRN_OFST 0x80c
  176. #define FDMA_DADDRN_OFST 0x810
  177. #define fnode_read(fchan, name) \
  178. readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
  179. + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
  180. + name)
  181. #define fnode_write(fchan, val, name) \
  182. writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
  183. + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
  184. + name)
  185. /*
  186. * request control bits
  187. */
  188. #define FDMA_REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24)
  189. #define FDMA_REQ_CTRL_NUM_OPS(n) (FDMA_REQ_CTRL_NUM_OPS_MASK & \
  190. ((n) << 24))
  191. #define FDMA_REQ_CTRL_INITIATOR_MASK BIT(22)
  192. #define FDMA_REQ_CTRL_INIT0 (0x0 << 22)
  193. #define FDMA_REQ_CTRL_INIT1 (0x1 << 22)
  194. #define FDMA_REQ_CTRL_INC_ADDR_ON BIT(21)
  195. #define FDMA_REQ_CTRL_DATA_SWAP_ON BIT(17)
  196. #define FDMA_REQ_CTRL_WNR BIT(14)
  197. #define FDMA_REQ_CTRL_OPCODE_MASK GENMASK(7, 4)
  198. #define FDMA_REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4)
  199. #define FDMA_REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4)
  200. #define FDMA_REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4)
  201. #define FDMA_REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4)
  202. #define FDMA_REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4)
  203. #define FDMA_REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4)
  204. #define FDMA_REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4)
  205. #define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)
  206. #define FDMA_REQ_CTRL_HOLDOFF(n) ((n) & FDMA_REQ_CTRL_HOLDOFF_MASK)
  207. /* bits used by client to configure request control */
  208. #define FDMA_REQ_CTRL_CFG_MASK (FDMA_REQ_CTRL_HOLDOFF_MASK | \
  209. FDMA_REQ_CTRL_DATA_SWAP_ON | \
  210. FDMA_REQ_CTRL_INC_ADDR_ON | \
  211. FDMA_REQ_CTRL_INITIATOR_MASK)
  212. #endif /* __DMA_ST_FDMA_H */