shdma-base.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
  4. *
  5. * extracted from shdma.c
  6. *
  7. * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  8. * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  9. * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
  10. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/shdma-base.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/slab.h>
  20. #include <linux/spinlock.h>
  21. #include "../dmaengine.h"
  22. /* DMA descriptor control */
  23. enum shdma_desc_status {
  24. DESC_IDLE,
  25. DESC_PREPARED,
  26. DESC_SUBMITTED,
  27. DESC_COMPLETED, /* completed, have to call callback */
  28. DESC_WAITING, /* callback called, waiting for ack / re-submit */
  29. };
  30. #define NR_DESCS_PER_CHANNEL 32
  31. #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
  32. #define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev)
  33. /*
  34. * For slave DMA we assume, that there is a finite number of DMA slaves in the
  35. * system, and that each such slave can only use a finite number of channels.
  36. * We use slave channel IDs to make sure, that no such slave channel ID is
  37. * allocated more than once.
  38. */
  39. static unsigned int slave_num = 256;
  40. module_param(slave_num, uint, 0444);
  41. /* A bitmask with slave_num bits */
  42. static unsigned long *shdma_slave_used;
  43. /* Called under spin_lock_irq(&schan->chan_lock") */
  44. static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan)
  45. {
  46. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  47. const struct shdma_ops *ops = sdev->ops;
  48. struct shdma_desc *sdesc;
  49. /* DMA work check */
  50. if (ops->channel_busy(schan))
  51. return;
  52. /* Find the first not transferred descriptor */
  53. list_for_each_entry(sdesc, &schan->ld_queue, node)
  54. if (sdesc->mark == DESC_SUBMITTED) {
  55. ops->start_xfer(schan, sdesc);
  56. break;
  57. }
  58. }
  59. static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx)
  60. {
  61. struct shdma_desc *chunk, *c, *desc =
  62. container_of(tx, struct shdma_desc, async_tx);
  63. struct shdma_chan *schan = to_shdma_chan(tx->chan);
  64. dma_async_tx_callback callback = tx->callback;
  65. dma_cookie_t cookie;
  66. bool power_up;
  67. spin_lock_irq(&schan->chan_lock);
  68. power_up = list_empty(&schan->ld_queue);
  69. cookie = dma_cookie_assign(tx);
  70. /* Mark all chunks of this descriptor as submitted, move to the queue */
  71. list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
  72. /*
  73. * All chunks are on the global ld_free, so, we have to find
  74. * the end of the chain ourselves
  75. */
  76. if (chunk != desc && (chunk->mark == DESC_IDLE ||
  77. chunk->async_tx.cookie > 0 ||
  78. chunk->async_tx.cookie == -EBUSY ||
  79. &chunk->node == &schan->ld_free))
  80. break;
  81. chunk->mark = DESC_SUBMITTED;
  82. if (chunk->chunks == 1) {
  83. chunk->async_tx.callback = callback;
  84. chunk->async_tx.callback_param = tx->callback_param;
  85. } else {
  86. /* Callback goes to the last chunk */
  87. chunk->async_tx.callback = NULL;
  88. }
  89. chunk->cookie = cookie;
  90. list_move_tail(&chunk->node, &schan->ld_queue);
  91. dev_dbg(schan->dev, "submit #%d@%p on %d\n",
  92. tx->cookie, &chunk->async_tx, schan->id);
  93. }
  94. if (power_up) {
  95. int ret;
  96. schan->pm_state = SHDMA_PM_BUSY;
  97. ret = pm_runtime_get(schan->dev);
  98. spin_unlock_irq(&schan->chan_lock);
  99. if (ret < 0)
  100. dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret);
  101. pm_runtime_barrier(schan->dev);
  102. spin_lock_irq(&schan->chan_lock);
  103. /* Have we been reset, while waiting? */
  104. if (schan->pm_state != SHDMA_PM_ESTABLISHED) {
  105. struct shdma_dev *sdev =
  106. to_shdma_dev(schan->dma_chan.device);
  107. const struct shdma_ops *ops = sdev->ops;
  108. dev_dbg(schan->dev, "Bring up channel %d\n",
  109. schan->id);
  110. /*
  111. * TODO: .xfer_setup() might fail on some platforms.
  112. * Make it int then, on error remove chunks from the
  113. * queue again
  114. */
  115. ops->setup_xfer(schan, schan->slave_id);
  116. if (schan->pm_state == SHDMA_PM_PENDING)
  117. shdma_chan_xfer_ld_queue(schan);
  118. schan->pm_state = SHDMA_PM_ESTABLISHED;
  119. }
  120. } else {
  121. /*
  122. * Tell .device_issue_pending() not to run the queue, interrupts
  123. * will do it anyway
  124. */
  125. schan->pm_state = SHDMA_PM_PENDING;
  126. }
  127. spin_unlock_irq(&schan->chan_lock);
  128. return cookie;
  129. }
  130. /* Called with desc_lock held */
  131. static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan)
  132. {
  133. struct shdma_desc *sdesc;
  134. list_for_each_entry(sdesc, &schan->ld_free, node)
  135. if (sdesc->mark != DESC_PREPARED) {
  136. BUG_ON(sdesc->mark != DESC_IDLE);
  137. list_del(&sdesc->node);
  138. return sdesc;
  139. }
  140. return NULL;
  141. }
  142. static int shdma_setup_slave(struct shdma_chan *schan, dma_addr_t slave_addr)
  143. {
  144. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  145. const struct shdma_ops *ops = sdev->ops;
  146. int ret, match;
  147. if (schan->dev->of_node) {
  148. match = schan->hw_req;
  149. ret = ops->set_slave(schan, match, slave_addr, true);
  150. if (ret < 0)
  151. return ret;
  152. } else {
  153. match = schan->real_slave_id;
  154. }
  155. if (schan->real_slave_id < 0 || schan->real_slave_id >= slave_num)
  156. return -EINVAL;
  157. if (test_and_set_bit(schan->real_slave_id, shdma_slave_used))
  158. return -EBUSY;
  159. ret = ops->set_slave(schan, match, slave_addr, false);
  160. if (ret < 0) {
  161. clear_bit(schan->real_slave_id, shdma_slave_used);
  162. return ret;
  163. }
  164. schan->slave_id = schan->real_slave_id;
  165. return 0;
  166. }
  167. static int shdma_alloc_chan_resources(struct dma_chan *chan)
  168. {
  169. struct shdma_chan *schan = to_shdma_chan(chan);
  170. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  171. const struct shdma_ops *ops = sdev->ops;
  172. struct shdma_desc *desc;
  173. struct shdma_slave *slave = chan->private;
  174. int ret, i;
  175. /*
  176. * This relies on the guarantee from dmaengine that alloc_chan_resources
  177. * never runs concurrently with itself or free_chan_resources.
  178. */
  179. if (slave) {
  180. /* Legacy mode: .private is set in filter */
  181. schan->real_slave_id = slave->slave_id;
  182. ret = shdma_setup_slave(schan, 0);
  183. if (ret < 0)
  184. goto esetslave;
  185. } else {
  186. /* Normal mode: real_slave_id was set by filter */
  187. schan->slave_id = -EINVAL;
  188. }
  189. schan->desc = kcalloc(NR_DESCS_PER_CHANNEL,
  190. sdev->desc_size, GFP_KERNEL);
  191. if (!schan->desc) {
  192. ret = -ENOMEM;
  193. goto edescalloc;
  194. }
  195. schan->desc_num = NR_DESCS_PER_CHANNEL;
  196. for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) {
  197. desc = ops->embedded_desc(schan->desc, i);
  198. dma_async_tx_descriptor_init(&desc->async_tx,
  199. &schan->dma_chan);
  200. desc->async_tx.tx_submit = shdma_tx_submit;
  201. desc->mark = DESC_IDLE;
  202. list_add(&desc->node, &schan->ld_free);
  203. }
  204. return NR_DESCS_PER_CHANNEL;
  205. edescalloc:
  206. if (slave)
  207. esetslave:
  208. clear_bit(slave->slave_id, shdma_slave_used);
  209. chan->private = NULL;
  210. return ret;
  211. }
  212. /*
  213. * This is the standard shdma filter function to be used as a replacement to the
  214. * "old" method, using the .private pointer.
  215. * You always have to pass a valid slave id as the argument, old drivers that
  216. * pass ERR_PTR(-EINVAL) as a filter parameter and set it up in dma_slave_config
  217. * need to be updated so we can remove the slave_id field from dma_slave_config.
  218. * parameter. If this filter is used, the slave driver, after calling
  219. * dma_request_channel(), will also have to call dmaengine_slave_config() with
  220. * .direction, and either .src_addr or .dst_addr set.
  221. *
  222. * NOTE: this filter doesn't support multiple DMAC drivers with the DMA_SLAVE
  223. * capability! If this becomes a requirement, hardware glue drivers, using this
  224. * services would have to provide their own filters, which first would check
  225. * the device driver, similar to how other DMAC drivers, e.g., sa11x0-dma.c, do
  226. * this, and only then, in case of a match, call this common filter.
  227. * NOTE 2: This filter function is also used in the DT case by shdma_of_xlate().
  228. * In that case the MID-RID value is used for slave channel filtering and is
  229. * passed to this function in the "arg" parameter.
  230. */
  231. bool shdma_chan_filter(struct dma_chan *chan, void *arg)
  232. {
  233. struct shdma_chan *schan;
  234. struct shdma_dev *sdev;
  235. int slave_id = (long)arg;
  236. int ret;
  237. /* Only support channels handled by this driver. */
  238. if (chan->device->device_alloc_chan_resources !=
  239. shdma_alloc_chan_resources)
  240. return false;
  241. schan = to_shdma_chan(chan);
  242. sdev = to_shdma_dev(chan->device);
  243. /*
  244. * For DT, the schan->slave_id field is generated by the
  245. * set_slave function from the slave ID that is passed in
  246. * from xlate. For the non-DT case, the slave ID is
  247. * directly passed into the filter function by the driver
  248. */
  249. if (schan->dev->of_node) {
  250. ret = sdev->ops->set_slave(schan, slave_id, 0, true);
  251. if (ret < 0)
  252. return false;
  253. schan->real_slave_id = schan->slave_id;
  254. return true;
  255. }
  256. if (slave_id < 0) {
  257. /* No slave requested - arbitrary channel */
  258. dev_warn(sdev->dma_dev.dev, "invalid slave ID passed to dma_request_slave\n");
  259. return true;
  260. }
  261. if (slave_id >= slave_num)
  262. return false;
  263. ret = sdev->ops->set_slave(schan, slave_id, 0, true);
  264. if (ret < 0)
  265. return false;
  266. schan->real_slave_id = slave_id;
  267. return true;
  268. }
  269. EXPORT_SYMBOL(shdma_chan_filter);
  270. static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all)
  271. {
  272. struct shdma_desc *desc, *_desc;
  273. /* Is the "exposed" head of a chain acked? */
  274. bool head_acked = false;
  275. dma_cookie_t cookie = 0;
  276. dma_async_tx_callback callback = NULL;
  277. struct dmaengine_desc_callback cb;
  278. unsigned long flags;
  279. LIST_HEAD(cyclic_list);
  280. memset(&cb, 0, sizeof(cb));
  281. spin_lock_irqsave(&schan->chan_lock, flags);
  282. list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) {
  283. struct dma_async_tx_descriptor *tx = &desc->async_tx;
  284. BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
  285. BUG_ON(desc->mark != DESC_SUBMITTED &&
  286. desc->mark != DESC_COMPLETED &&
  287. desc->mark != DESC_WAITING);
  288. /*
  289. * queue is ordered, and we use this loop to (1) clean up all
  290. * completed descriptors, and to (2) update descriptor flags of
  291. * any chunks in a (partially) completed chain
  292. */
  293. if (!all && desc->mark == DESC_SUBMITTED &&
  294. desc->cookie != cookie)
  295. break;
  296. if (tx->cookie > 0)
  297. cookie = tx->cookie;
  298. if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
  299. if (schan->dma_chan.completed_cookie != desc->cookie - 1)
  300. dev_dbg(schan->dev,
  301. "Completing cookie %d, expected %d\n",
  302. desc->cookie,
  303. schan->dma_chan.completed_cookie + 1);
  304. schan->dma_chan.completed_cookie = desc->cookie;
  305. }
  306. /* Call callback on the last chunk */
  307. if (desc->mark == DESC_COMPLETED && tx->callback) {
  308. desc->mark = DESC_WAITING;
  309. dmaengine_desc_get_callback(tx, &cb);
  310. callback = tx->callback;
  311. dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n",
  312. tx->cookie, tx, schan->id);
  313. BUG_ON(desc->chunks != 1);
  314. break;
  315. }
  316. if (tx->cookie > 0 || tx->cookie == -EBUSY) {
  317. if (desc->mark == DESC_COMPLETED) {
  318. BUG_ON(tx->cookie < 0);
  319. desc->mark = DESC_WAITING;
  320. }
  321. head_acked = async_tx_test_ack(tx);
  322. } else {
  323. switch (desc->mark) {
  324. case DESC_COMPLETED:
  325. desc->mark = DESC_WAITING;
  326. fallthrough;
  327. case DESC_WAITING:
  328. if (head_acked)
  329. async_tx_ack(&desc->async_tx);
  330. }
  331. }
  332. dev_dbg(schan->dev, "descriptor %p #%d completed.\n",
  333. tx, tx->cookie);
  334. if (((desc->mark == DESC_COMPLETED ||
  335. desc->mark == DESC_WAITING) &&
  336. async_tx_test_ack(&desc->async_tx)) || all) {
  337. if (all || !desc->cyclic) {
  338. /* Remove from ld_queue list */
  339. desc->mark = DESC_IDLE;
  340. list_move(&desc->node, &schan->ld_free);
  341. } else {
  342. /* reuse as cyclic */
  343. desc->mark = DESC_SUBMITTED;
  344. list_move_tail(&desc->node, &cyclic_list);
  345. }
  346. if (list_empty(&schan->ld_queue)) {
  347. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  348. pm_runtime_put(schan->dev);
  349. schan->pm_state = SHDMA_PM_ESTABLISHED;
  350. } else if (schan->pm_state == SHDMA_PM_PENDING) {
  351. shdma_chan_xfer_ld_queue(schan);
  352. }
  353. }
  354. }
  355. if (all && !callback)
  356. /*
  357. * Terminating and the loop completed normally: forgive
  358. * uncompleted cookies
  359. */
  360. schan->dma_chan.completed_cookie = schan->dma_chan.cookie;
  361. list_splice_tail(&cyclic_list, &schan->ld_queue);
  362. spin_unlock_irqrestore(&schan->chan_lock, flags);
  363. dmaengine_desc_callback_invoke(&cb, NULL);
  364. return callback;
  365. }
  366. /*
  367. * shdma_chan_ld_cleanup - Clean up link descriptors
  368. *
  369. * Clean up the ld_queue of DMA channel.
  370. */
  371. static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all)
  372. {
  373. while (__ld_cleanup(schan, all))
  374. ;
  375. }
  376. /*
  377. * shdma_free_chan_resources - Free all resources of the channel.
  378. */
  379. static void shdma_free_chan_resources(struct dma_chan *chan)
  380. {
  381. struct shdma_chan *schan = to_shdma_chan(chan);
  382. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  383. const struct shdma_ops *ops = sdev->ops;
  384. LIST_HEAD(list);
  385. /* Protect against ISR */
  386. spin_lock_irq(&schan->chan_lock);
  387. ops->halt_channel(schan);
  388. spin_unlock_irq(&schan->chan_lock);
  389. /* Now no new interrupts will occur */
  390. /* Prepared and not submitted descriptors can still be on the queue */
  391. if (!list_empty(&schan->ld_queue))
  392. shdma_chan_ld_cleanup(schan, true);
  393. if (schan->slave_id >= 0) {
  394. /* The caller is holding dma_list_mutex */
  395. clear_bit(schan->slave_id, shdma_slave_used);
  396. chan->private = NULL;
  397. }
  398. schan->real_slave_id = 0;
  399. spin_lock_irq(&schan->chan_lock);
  400. list_splice_init(&schan->ld_free, &list);
  401. schan->desc_num = 0;
  402. spin_unlock_irq(&schan->chan_lock);
  403. kfree(schan->desc);
  404. }
  405. /**
  406. * shdma_add_desc - get, set up and return one transfer descriptor
  407. * @schan: DMA channel
  408. * @flags: DMA transfer flags
  409. * @dst: destination DMA address, incremented when direction equals
  410. * DMA_DEV_TO_MEM or DMA_MEM_TO_MEM
  411. * @src: source DMA address, incremented when direction equals
  412. * DMA_MEM_TO_DEV or DMA_MEM_TO_MEM
  413. * @len: DMA transfer length
  414. * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
  415. * @direction: needed for slave DMA to decide which address to keep constant,
  416. * equals DMA_MEM_TO_MEM for MEMCPY
  417. * Returns 0 or an error
  418. * Locks: called with desc_lock held
  419. */
  420. static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan,
  421. unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len,
  422. struct shdma_desc **first, enum dma_transfer_direction direction)
  423. {
  424. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  425. const struct shdma_ops *ops = sdev->ops;
  426. struct shdma_desc *new;
  427. size_t copy_size = *len;
  428. if (!copy_size)
  429. return NULL;
  430. /* Allocate the link descriptor from the free list */
  431. new = shdma_get_desc(schan);
  432. if (!new) {
  433. dev_err(schan->dev, "No free link descriptor available\n");
  434. return NULL;
  435. }
  436. ops->desc_setup(schan, new, *src, *dst, &copy_size);
  437. if (!*first) {
  438. /* First desc */
  439. new->async_tx.cookie = -EBUSY;
  440. *first = new;
  441. } else {
  442. /* Other desc - invisible to the user */
  443. new->async_tx.cookie = -EINVAL;
  444. }
  445. dev_dbg(schan->dev,
  446. "chaining (%zu/%zu)@%pad -> %pad with %p, cookie %d\n",
  447. copy_size, *len, src, dst, &new->async_tx,
  448. new->async_tx.cookie);
  449. new->mark = DESC_PREPARED;
  450. new->async_tx.flags = flags;
  451. new->direction = direction;
  452. new->partial = 0;
  453. *len -= copy_size;
  454. if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
  455. *src += copy_size;
  456. if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
  457. *dst += copy_size;
  458. return new;
  459. }
  460. /*
  461. * shdma_prep_sg - prepare transfer descriptors from an SG list
  462. *
  463. * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
  464. * converted to scatter-gather to guarantee consistent locking and a correct
  465. * list manipulation. For slave DMA direction carries the usual meaning, and,
  466. * logically, the SG list is RAM and the addr variable contains slave address,
  467. * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
  468. * and the SG list contains only one element and points at the source buffer.
  469. */
  470. static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan,
  471. struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
  472. enum dma_transfer_direction direction, unsigned long flags, bool cyclic)
  473. {
  474. struct scatterlist *sg;
  475. struct shdma_desc *first = NULL, *new = NULL /* compiler... */;
  476. LIST_HEAD(tx_list);
  477. int chunks = 0;
  478. unsigned long irq_flags;
  479. int i;
  480. for_each_sg(sgl, sg, sg_len, i)
  481. chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len);
  482. /* Have to lock the whole loop to protect against concurrent release */
  483. spin_lock_irqsave(&schan->chan_lock, irq_flags);
  484. /*
  485. * Chaining:
  486. * first descriptor is what user is dealing with in all API calls, its
  487. * cookie is at first set to -EBUSY, at tx-submit to a positive
  488. * number
  489. * if more than one chunk is needed further chunks have cookie = -EINVAL
  490. * the last chunk, if not equal to the first, has cookie = -ENOSPC
  491. * all chunks are linked onto the tx_list head with their .node heads
  492. * only during this function, then they are immediately spliced
  493. * back onto the free list in form of a chain
  494. */
  495. for_each_sg(sgl, sg, sg_len, i) {
  496. dma_addr_t sg_addr = sg_dma_address(sg);
  497. size_t len = sg_dma_len(sg);
  498. if (!len)
  499. goto err_get_desc;
  500. do {
  501. dev_dbg(schan->dev, "Add SG #%d@%p[%zu], dma %pad\n",
  502. i, sg, len, &sg_addr);
  503. if (direction == DMA_DEV_TO_MEM)
  504. new = shdma_add_desc(schan, flags,
  505. &sg_addr, addr, &len, &first,
  506. direction);
  507. else
  508. new = shdma_add_desc(schan, flags,
  509. addr, &sg_addr, &len, &first,
  510. direction);
  511. if (!new)
  512. goto err_get_desc;
  513. new->cyclic = cyclic;
  514. if (cyclic)
  515. new->chunks = 1;
  516. else
  517. new->chunks = chunks--;
  518. list_add_tail(&new->node, &tx_list);
  519. } while (len);
  520. }
  521. if (new != first)
  522. new->async_tx.cookie = -ENOSPC;
  523. /* Put them back on the free list, so, they don't get lost */
  524. list_splice_tail(&tx_list, &schan->ld_free);
  525. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  526. return &first->async_tx;
  527. err_get_desc:
  528. list_for_each_entry(new, &tx_list, node)
  529. new->mark = DESC_IDLE;
  530. list_splice(&tx_list, &schan->ld_free);
  531. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  532. return NULL;
  533. }
  534. static struct dma_async_tx_descriptor *shdma_prep_memcpy(
  535. struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
  536. size_t len, unsigned long flags)
  537. {
  538. struct shdma_chan *schan = to_shdma_chan(chan);
  539. struct scatterlist sg;
  540. if (!chan || !len)
  541. return NULL;
  542. BUG_ON(!schan->desc_num);
  543. sg_init_table(&sg, 1);
  544. sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
  545. offset_in_page(dma_src));
  546. sg_dma_address(&sg) = dma_src;
  547. sg_dma_len(&sg) = len;
  548. return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM,
  549. flags, false);
  550. }
  551. static struct dma_async_tx_descriptor *shdma_prep_slave_sg(
  552. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
  553. enum dma_transfer_direction direction, unsigned long flags, void *context)
  554. {
  555. struct shdma_chan *schan = to_shdma_chan(chan);
  556. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  557. const struct shdma_ops *ops = sdev->ops;
  558. int slave_id = schan->slave_id;
  559. dma_addr_t slave_addr;
  560. if (!chan)
  561. return NULL;
  562. BUG_ON(!schan->desc_num);
  563. /* Someone calling slave DMA on a generic channel? */
  564. if (slave_id < 0 || !sg_len) {
  565. dev_warn(schan->dev, "%s: bad parameter: len=%d, id=%d\n",
  566. __func__, sg_len, slave_id);
  567. return NULL;
  568. }
  569. slave_addr = ops->slave_addr(schan);
  570. return shdma_prep_sg(schan, sgl, sg_len, &slave_addr,
  571. direction, flags, false);
  572. }
  573. #define SHDMA_MAX_SG_LEN 32
  574. static struct dma_async_tx_descriptor *shdma_prep_dma_cyclic(
  575. struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  576. size_t period_len, enum dma_transfer_direction direction,
  577. unsigned long flags)
  578. {
  579. struct shdma_chan *schan = to_shdma_chan(chan);
  580. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  581. struct dma_async_tx_descriptor *desc;
  582. const struct shdma_ops *ops = sdev->ops;
  583. unsigned int sg_len = buf_len / period_len;
  584. int slave_id = schan->slave_id;
  585. dma_addr_t slave_addr;
  586. struct scatterlist *sgl;
  587. int i;
  588. if (!chan)
  589. return NULL;
  590. BUG_ON(!schan->desc_num);
  591. if (sg_len > SHDMA_MAX_SG_LEN) {
  592. dev_err(schan->dev, "sg length %d exceeds limit %d",
  593. sg_len, SHDMA_MAX_SG_LEN);
  594. return NULL;
  595. }
  596. /* Someone calling slave DMA on a generic channel? */
  597. if (slave_id < 0 || (buf_len < period_len)) {
  598. dev_warn(schan->dev,
  599. "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n",
  600. __func__, buf_len, period_len, slave_id);
  601. return NULL;
  602. }
  603. slave_addr = ops->slave_addr(schan);
  604. /*
  605. * Allocate the sg list dynamically as it would consumer too much stack
  606. * space.
  607. */
  608. sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_KERNEL);
  609. if (!sgl)
  610. return NULL;
  611. sg_init_table(sgl, sg_len);
  612. for (i = 0; i < sg_len; i++) {
  613. dma_addr_t src = buf_addr + (period_len * i);
  614. sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len,
  615. offset_in_page(src));
  616. sg_dma_address(&sgl[i]) = src;
  617. sg_dma_len(&sgl[i]) = period_len;
  618. }
  619. desc = shdma_prep_sg(schan, sgl, sg_len, &slave_addr,
  620. direction, flags, true);
  621. kfree(sgl);
  622. return desc;
  623. }
  624. static int shdma_terminate_all(struct dma_chan *chan)
  625. {
  626. struct shdma_chan *schan = to_shdma_chan(chan);
  627. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  628. const struct shdma_ops *ops = sdev->ops;
  629. unsigned long flags;
  630. spin_lock_irqsave(&schan->chan_lock, flags);
  631. ops->halt_channel(schan);
  632. if (ops->get_partial && !list_empty(&schan->ld_queue)) {
  633. /* Record partial transfer */
  634. struct shdma_desc *desc = list_first_entry(&schan->ld_queue,
  635. struct shdma_desc, node);
  636. desc->partial = ops->get_partial(schan, desc);
  637. }
  638. spin_unlock_irqrestore(&schan->chan_lock, flags);
  639. shdma_chan_ld_cleanup(schan, true);
  640. return 0;
  641. }
  642. static int shdma_config(struct dma_chan *chan,
  643. struct dma_slave_config *config)
  644. {
  645. struct shdma_chan *schan = to_shdma_chan(chan);
  646. /*
  647. * So far only .slave_id is used, but the slave drivers are
  648. * encouraged to also set a transfer direction and an address.
  649. */
  650. if (!config)
  651. return -EINVAL;
  652. /*
  653. * overriding the slave_id through dma_slave_config is deprecated,
  654. * but possibly some out-of-tree drivers still do it.
  655. */
  656. if (WARN_ON_ONCE(config->slave_id &&
  657. config->slave_id != schan->real_slave_id))
  658. schan->real_slave_id = config->slave_id;
  659. /*
  660. * We could lock this, but you shouldn't be configuring the
  661. * channel, while using it...
  662. */
  663. return shdma_setup_slave(schan,
  664. config->direction == DMA_DEV_TO_MEM ?
  665. config->src_addr : config->dst_addr);
  666. }
  667. static void shdma_issue_pending(struct dma_chan *chan)
  668. {
  669. struct shdma_chan *schan = to_shdma_chan(chan);
  670. spin_lock_irq(&schan->chan_lock);
  671. if (schan->pm_state == SHDMA_PM_ESTABLISHED)
  672. shdma_chan_xfer_ld_queue(schan);
  673. else
  674. schan->pm_state = SHDMA_PM_PENDING;
  675. spin_unlock_irq(&schan->chan_lock);
  676. }
  677. static enum dma_status shdma_tx_status(struct dma_chan *chan,
  678. dma_cookie_t cookie,
  679. struct dma_tx_state *txstate)
  680. {
  681. struct shdma_chan *schan = to_shdma_chan(chan);
  682. enum dma_status status;
  683. unsigned long flags;
  684. shdma_chan_ld_cleanup(schan, false);
  685. spin_lock_irqsave(&schan->chan_lock, flags);
  686. status = dma_cookie_status(chan, cookie, txstate);
  687. /*
  688. * If we don't find cookie on the queue, it has been aborted and we have
  689. * to report error
  690. */
  691. if (status != DMA_COMPLETE) {
  692. struct shdma_desc *sdesc;
  693. status = DMA_ERROR;
  694. list_for_each_entry(sdesc, &schan->ld_queue, node)
  695. if (sdesc->cookie == cookie) {
  696. status = DMA_IN_PROGRESS;
  697. break;
  698. }
  699. }
  700. spin_unlock_irqrestore(&schan->chan_lock, flags);
  701. return status;
  702. }
  703. /* Called from error IRQ or NMI */
  704. bool shdma_reset(struct shdma_dev *sdev)
  705. {
  706. const struct shdma_ops *ops = sdev->ops;
  707. struct shdma_chan *schan;
  708. unsigned int handled = 0;
  709. int i;
  710. /* Reset all channels */
  711. shdma_for_each_chan(schan, sdev, i) {
  712. struct shdma_desc *sdesc;
  713. LIST_HEAD(dl);
  714. if (!schan)
  715. continue;
  716. spin_lock(&schan->chan_lock);
  717. /* Stop the channel */
  718. ops->halt_channel(schan);
  719. list_splice_init(&schan->ld_queue, &dl);
  720. if (!list_empty(&dl)) {
  721. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  722. pm_runtime_put(schan->dev);
  723. }
  724. schan->pm_state = SHDMA_PM_ESTABLISHED;
  725. spin_unlock(&schan->chan_lock);
  726. /* Complete all */
  727. list_for_each_entry(sdesc, &dl, node) {
  728. struct dma_async_tx_descriptor *tx = &sdesc->async_tx;
  729. sdesc->mark = DESC_IDLE;
  730. dmaengine_desc_get_callback_invoke(tx, NULL);
  731. }
  732. spin_lock(&schan->chan_lock);
  733. list_splice(&dl, &schan->ld_free);
  734. spin_unlock(&schan->chan_lock);
  735. handled++;
  736. }
  737. return !!handled;
  738. }
  739. EXPORT_SYMBOL(shdma_reset);
  740. static irqreturn_t chan_irq(int irq, void *dev)
  741. {
  742. struct shdma_chan *schan = dev;
  743. const struct shdma_ops *ops =
  744. to_shdma_dev(schan->dma_chan.device)->ops;
  745. irqreturn_t ret;
  746. spin_lock(&schan->chan_lock);
  747. ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE;
  748. spin_unlock(&schan->chan_lock);
  749. return ret;
  750. }
  751. static irqreturn_t chan_irqt(int irq, void *dev)
  752. {
  753. struct shdma_chan *schan = dev;
  754. const struct shdma_ops *ops =
  755. to_shdma_dev(schan->dma_chan.device)->ops;
  756. struct shdma_desc *sdesc;
  757. spin_lock_irq(&schan->chan_lock);
  758. list_for_each_entry(sdesc, &schan->ld_queue, node) {
  759. if (sdesc->mark == DESC_SUBMITTED &&
  760. ops->desc_completed(schan, sdesc)) {
  761. dev_dbg(schan->dev, "done #%d@%p\n",
  762. sdesc->async_tx.cookie, &sdesc->async_tx);
  763. sdesc->mark = DESC_COMPLETED;
  764. break;
  765. }
  766. }
  767. /* Next desc */
  768. shdma_chan_xfer_ld_queue(schan);
  769. spin_unlock_irq(&schan->chan_lock);
  770. shdma_chan_ld_cleanup(schan, false);
  771. return IRQ_HANDLED;
  772. }
  773. int shdma_request_irq(struct shdma_chan *schan, int irq,
  774. unsigned long flags, const char *name)
  775. {
  776. int ret = devm_request_threaded_irq(schan->dev, irq, chan_irq,
  777. chan_irqt, flags, name, schan);
  778. schan->irq = ret < 0 ? ret : irq;
  779. return ret;
  780. }
  781. EXPORT_SYMBOL(shdma_request_irq);
  782. void shdma_chan_probe(struct shdma_dev *sdev,
  783. struct shdma_chan *schan, int id)
  784. {
  785. schan->pm_state = SHDMA_PM_ESTABLISHED;
  786. /* reference struct dma_device */
  787. schan->dma_chan.device = &sdev->dma_dev;
  788. dma_cookie_init(&schan->dma_chan);
  789. schan->dev = sdev->dma_dev.dev;
  790. schan->id = id;
  791. if (!schan->max_xfer_len)
  792. schan->max_xfer_len = PAGE_SIZE;
  793. spin_lock_init(&schan->chan_lock);
  794. /* Init descripter manage list */
  795. INIT_LIST_HEAD(&schan->ld_queue);
  796. INIT_LIST_HEAD(&schan->ld_free);
  797. /* Add the channel to DMA device channel list */
  798. list_add_tail(&schan->dma_chan.device_node,
  799. &sdev->dma_dev.channels);
  800. sdev->schan[id] = schan;
  801. }
  802. EXPORT_SYMBOL(shdma_chan_probe);
  803. void shdma_chan_remove(struct shdma_chan *schan)
  804. {
  805. list_del(&schan->dma_chan.device_node);
  806. }
  807. EXPORT_SYMBOL(shdma_chan_remove);
  808. int shdma_init(struct device *dev, struct shdma_dev *sdev,
  809. int chan_num)
  810. {
  811. struct dma_device *dma_dev = &sdev->dma_dev;
  812. /*
  813. * Require all call-backs for now, they can trivially be made optional
  814. * later as required
  815. */
  816. if (!sdev->ops ||
  817. !sdev->desc_size ||
  818. !sdev->ops->embedded_desc ||
  819. !sdev->ops->start_xfer ||
  820. !sdev->ops->setup_xfer ||
  821. !sdev->ops->set_slave ||
  822. !sdev->ops->desc_setup ||
  823. !sdev->ops->slave_addr ||
  824. !sdev->ops->channel_busy ||
  825. !sdev->ops->halt_channel ||
  826. !sdev->ops->desc_completed)
  827. return -EINVAL;
  828. sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL);
  829. if (!sdev->schan)
  830. return -ENOMEM;
  831. INIT_LIST_HEAD(&dma_dev->channels);
  832. /* Common and MEMCPY operations */
  833. dma_dev->device_alloc_chan_resources
  834. = shdma_alloc_chan_resources;
  835. dma_dev->device_free_chan_resources = shdma_free_chan_resources;
  836. dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy;
  837. dma_dev->device_tx_status = shdma_tx_status;
  838. dma_dev->device_issue_pending = shdma_issue_pending;
  839. /* Compulsory for DMA_SLAVE fields */
  840. dma_dev->device_prep_slave_sg = shdma_prep_slave_sg;
  841. dma_dev->device_prep_dma_cyclic = shdma_prep_dma_cyclic;
  842. dma_dev->device_config = shdma_config;
  843. dma_dev->device_terminate_all = shdma_terminate_all;
  844. dma_dev->dev = dev;
  845. return 0;
  846. }
  847. EXPORT_SYMBOL(shdma_init);
  848. void shdma_cleanup(struct shdma_dev *sdev)
  849. {
  850. kfree(sdev->schan);
  851. }
  852. EXPORT_SYMBOL(shdma_cleanup);
  853. static int __init shdma_enter(void)
  854. {
  855. shdma_slave_used = kcalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG),
  856. sizeof(long),
  857. GFP_KERNEL);
  858. if (!shdma_slave_used)
  859. return -ENOMEM;
  860. return 0;
  861. }
  862. module_init(shdma_enter);
  863. static void __exit shdma_exit(void)
  864. {
  865. kfree(shdma_slave_used);
  866. }
  867. module_exit(shdma_exit);
  868. MODULE_LICENSE("GPL v2");
  869. MODULE_DESCRIPTION("SH-DMA driver base library");
  870. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");