pl330.c 73 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  7. * Jaswinder Singh <jassi.brar@samsung.com>
  8. */
  9. #include <linux/debugfs.h>
  10. #include <linux/kernel.h>
  11. #include <linux/io.h>
  12. #include <linux/init.h>
  13. #include <linux/slab.h>
  14. #include <linux/module.h>
  15. #include <linux/string.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/dmaengine.h>
  20. #include <linux/amba/bus.h>
  21. #include <linux/scatterlist.h>
  22. #include <linux/of.h>
  23. #include <linux/of_dma.h>
  24. #include <linux/err.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/bug.h>
  27. #include <linux/reset.h>
  28. #include "dmaengine.h"
  29. #define PL330_MAX_CHAN 8
  30. #define PL330_MAX_IRQS 32
  31. #define PL330_MAX_PERI 32
  32. #define PL330_MAX_BURST 16
  33. #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
  34. #define PL330_QUIRK_PERIPH_BURST BIT(1)
  35. enum pl330_cachectrl {
  36. CCTRL0, /* Noncacheable and nonbufferable */
  37. CCTRL1, /* Bufferable only */
  38. CCTRL2, /* Cacheable, but do not allocate */
  39. CCTRL3, /* Cacheable and bufferable, but do not allocate */
  40. INVALID1, /* AWCACHE = 0x1000 */
  41. INVALID2,
  42. CCTRL6, /* Cacheable write-through, allocate on writes only */
  43. CCTRL7, /* Cacheable write-back, allocate on writes only */
  44. };
  45. enum pl330_byteswap {
  46. SWAP_NO,
  47. SWAP_2,
  48. SWAP_4,
  49. SWAP_8,
  50. SWAP_16,
  51. };
  52. /* Register and Bit field Definitions */
  53. #define DS 0x0
  54. #define DS_ST_STOP 0x0
  55. #define DS_ST_EXEC 0x1
  56. #define DS_ST_CMISS 0x2
  57. #define DS_ST_UPDTPC 0x3
  58. #define DS_ST_WFE 0x4
  59. #define DS_ST_ATBRR 0x5
  60. #define DS_ST_QBUSY 0x6
  61. #define DS_ST_WFP 0x7
  62. #define DS_ST_KILL 0x8
  63. #define DS_ST_CMPLT 0x9
  64. #define DS_ST_FLTCMP 0xe
  65. #define DS_ST_FAULT 0xf
  66. #define DPC 0x4
  67. #define INTEN 0x20
  68. #define ES 0x24
  69. #define INTSTATUS 0x28
  70. #define INTCLR 0x2c
  71. #define FSM 0x30
  72. #define FSC 0x34
  73. #define FTM 0x38
  74. #define _FTC 0x40
  75. #define FTC(n) (_FTC + (n)*0x4)
  76. #define _CS 0x100
  77. #define CS(n) (_CS + (n)*0x8)
  78. #define CS_CNS (1 << 21)
  79. #define _CPC 0x104
  80. #define CPC(n) (_CPC + (n)*0x8)
  81. #define _SA 0x400
  82. #define SA(n) (_SA + (n)*0x20)
  83. #define _DA 0x404
  84. #define DA(n) (_DA + (n)*0x20)
  85. #define _CC 0x408
  86. #define CC(n) (_CC + (n)*0x20)
  87. #define CC_SRCINC (1 << 0)
  88. #define CC_DSTINC (1 << 14)
  89. #define CC_SRCPRI (1 << 8)
  90. #define CC_DSTPRI (1 << 22)
  91. #define CC_SRCNS (1 << 9)
  92. #define CC_DSTNS (1 << 23)
  93. #define CC_SRCIA (1 << 10)
  94. #define CC_DSTIA (1 << 24)
  95. #define CC_SRCBRSTLEN_SHFT 4
  96. #define CC_DSTBRSTLEN_SHFT 18
  97. #define CC_SRCBRSTSIZE_SHFT 1
  98. #define CC_DSTBRSTSIZE_SHFT 15
  99. #define CC_SRCCCTRL_SHFT 11
  100. #define CC_SRCCCTRL_MASK 0x7
  101. #define CC_DSTCCTRL_SHFT 25
  102. #define CC_DRCCCTRL_MASK 0x7
  103. #define CC_SWAP_SHFT 28
  104. #define _LC0 0x40c
  105. #define LC0(n) (_LC0 + (n)*0x20)
  106. #define _LC1 0x410
  107. #define LC1(n) (_LC1 + (n)*0x20)
  108. #define DBGSTATUS 0xd00
  109. #define DBG_BUSY (1 << 0)
  110. #define DBGCMD 0xd04
  111. #define DBGINST0 0xd08
  112. #define DBGINST1 0xd0c
  113. #define CR0 0xe00
  114. #define CR1 0xe04
  115. #define CR2 0xe08
  116. #define CR3 0xe0c
  117. #define CR4 0xe10
  118. #define CRD 0xe14
  119. #define PERIPH_ID 0xfe0
  120. #define PERIPH_REV_SHIFT 20
  121. #define PERIPH_REV_MASK 0xf
  122. #define PERIPH_REV_R0P0 0
  123. #define PERIPH_REV_R1P0 1
  124. #define PERIPH_REV_R1P1 2
  125. #define CR0_PERIPH_REQ_SET (1 << 0)
  126. #define CR0_BOOT_EN_SET (1 << 1)
  127. #define CR0_BOOT_MAN_NS (1 << 2)
  128. #define CR0_NUM_CHANS_SHIFT 4
  129. #define CR0_NUM_CHANS_MASK 0x7
  130. #define CR0_NUM_PERIPH_SHIFT 12
  131. #define CR0_NUM_PERIPH_MASK 0x1f
  132. #define CR0_NUM_EVENTS_SHIFT 17
  133. #define CR0_NUM_EVENTS_MASK 0x1f
  134. #define CR1_ICACHE_LEN_SHIFT 0
  135. #define CR1_ICACHE_LEN_MASK 0x7
  136. #define CR1_NUM_ICACHELINES_SHIFT 4
  137. #define CR1_NUM_ICACHELINES_MASK 0xf
  138. #define CRD_DATA_WIDTH_SHIFT 0
  139. #define CRD_DATA_WIDTH_MASK 0x7
  140. #define CRD_WR_CAP_SHIFT 4
  141. #define CRD_WR_CAP_MASK 0x7
  142. #define CRD_WR_Q_DEP_SHIFT 8
  143. #define CRD_WR_Q_DEP_MASK 0xf
  144. #define CRD_RD_CAP_SHIFT 12
  145. #define CRD_RD_CAP_MASK 0x7
  146. #define CRD_RD_Q_DEP_SHIFT 16
  147. #define CRD_RD_Q_DEP_MASK 0xf
  148. #define CRD_DATA_BUFF_SHIFT 20
  149. #define CRD_DATA_BUFF_MASK 0x3ff
  150. #define PART 0x330
  151. #define DESIGNER 0x41
  152. #define REVISION 0x0
  153. #define INTEG_CFG 0x0
  154. #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
  155. #define PL330_STATE_STOPPED (1 << 0)
  156. #define PL330_STATE_EXECUTING (1 << 1)
  157. #define PL330_STATE_WFE (1 << 2)
  158. #define PL330_STATE_FAULTING (1 << 3)
  159. #define PL330_STATE_COMPLETING (1 << 4)
  160. #define PL330_STATE_WFP (1 << 5)
  161. #define PL330_STATE_KILLING (1 << 6)
  162. #define PL330_STATE_FAULT_COMPLETING (1 << 7)
  163. #define PL330_STATE_CACHEMISS (1 << 8)
  164. #define PL330_STATE_UPDTPC (1 << 9)
  165. #define PL330_STATE_ATBARRIER (1 << 10)
  166. #define PL330_STATE_QUEUEBUSY (1 << 11)
  167. #define PL330_STATE_INVALID (1 << 15)
  168. #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
  169. | PL330_STATE_WFE | PL330_STATE_FAULTING)
  170. #define CMD_DMAADDH 0x54
  171. #define CMD_DMAEND 0x00
  172. #define CMD_DMAFLUSHP 0x35
  173. #define CMD_DMAGO 0xa0
  174. #define CMD_DMALD 0x04
  175. #define CMD_DMALDP 0x25
  176. #define CMD_DMALP 0x20
  177. #define CMD_DMALPEND 0x28
  178. #define CMD_DMAKILL 0x01
  179. #define CMD_DMAMOV 0xbc
  180. #define CMD_DMANOP 0x18
  181. #define CMD_DMARMB 0x12
  182. #define CMD_DMASEV 0x34
  183. #define CMD_DMAST 0x08
  184. #define CMD_DMASTP 0x29
  185. #define CMD_DMASTZ 0x0c
  186. #define CMD_DMAWFE 0x36
  187. #define CMD_DMAWFP 0x30
  188. #define CMD_DMAWMB 0x13
  189. #define SZ_DMAADDH 3
  190. #define SZ_DMAEND 1
  191. #define SZ_DMAFLUSHP 2
  192. #define SZ_DMALD 1
  193. #define SZ_DMALDP 2
  194. #define SZ_DMALP 2
  195. #define SZ_DMALPEND 2
  196. #define SZ_DMAKILL 1
  197. #define SZ_DMAMOV 6
  198. #define SZ_DMANOP 1
  199. #define SZ_DMARMB 1
  200. #define SZ_DMASEV 2
  201. #define SZ_DMAST 1
  202. #define SZ_DMASTP 2
  203. #define SZ_DMASTZ 1
  204. #define SZ_DMAWFE 2
  205. #define SZ_DMAWFP 2
  206. #define SZ_DMAWMB 1
  207. #define SZ_DMAGO 6
  208. #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
  209. #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
  210. #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
  211. #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
  212. /*
  213. * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
  214. * at 1byte/burst for P<->M and M<->M respectively.
  215. * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
  216. * should be enough for P<->M and M<->M respectively.
  217. */
  218. #define MCODE_BUFF_PER_REQ 256
  219. /* Use this _only_ to wait on transient states */
  220. #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
  221. #ifdef PL330_DEBUG_MCGEN
  222. static unsigned cmd_line;
  223. #define PL330_DBGCMD_DUMP(off, x...) do { \
  224. printk("%x:", cmd_line); \
  225. printk(KERN_CONT x); \
  226. cmd_line += off; \
  227. } while (0)
  228. #define PL330_DBGMC_START(addr) (cmd_line = addr)
  229. #else
  230. #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
  231. #define PL330_DBGMC_START(addr) do {} while (0)
  232. #endif
  233. /* The number of default descriptors */
  234. #define NR_DEFAULT_DESC 16
  235. /* Delay for runtime PM autosuspend, ms */
  236. #define PL330_AUTOSUSPEND_DELAY 20
  237. /* Populated by the PL330 core driver for DMA API driver's info */
  238. struct pl330_config {
  239. u32 periph_id;
  240. #define DMAC_MODE_NS (1 << 0)
  241. unsigned int mode;
  242. unsigned int data_bus_width:10; /* In number of bits */
  243. unsigned int data_buf_dep:11;
  244. unsigned int num_chan:4;
  245. unsigned int num_peri:6;
  246. u32 peri_ns;
  247. unsigned int num_events:6;
  248. u32 irq_ns;
  249. };
  250. /*
  251. * Request Configuration.
  252. * The PL330 core does not modify this and uses the last
  253. * working configuration if the request doesn't provide any.
  254. *
  255. * The Client may want to provide this info only for the
  256. * first request and a request with new settings.
  257. */
  258. struct pl330_reqcfg {
  259. /* Address Incrementing */
  260. unsigned dst_inc:1;
  261. unsigned src_inc:1;
  262. /*
  263. * For now, the SRC & DST protection levels
  264. * and burst size/length are assumed same.
  265. */
  266. bool nonsecure;
  267. bool privileged;
  268. bool insnaccess;
  269. unsigned brst_len:5;
  270. unsigned brst_size:3; /* in power of 2 */
  271. enum pl330_cachectrl dcctl;
  272. enum pl330_cachectrl scctl;
  273. enum pl330_byteswap swap;
  274. struct pl330_config *pcfg;
  275. };
  276. /*
  277. * One cycle of DMAC operation.
  278. * There may be more than one xfer in a request.
  279. */
  280. struct pl330_xfer {
  281. u32 src_addr;
  282. u32 dst_addr;
  283. /* Size to xfer */
  284. u32 bytes;
  285. };
  286. /* The xfer callbacks are made with one of these arguments. */
  287. enum pl330_op_err {
  288. /* The all xfers in the request were success. */
  289. PL330_ERR_NONE,
  290. /* If req aborted due to global error. */
  291. PL330_ERR_ABORT,
  292. /* If req failed due to problem with Channel. */
  293. PL330_ERR_FAIL,
  294. };
  295. enum dmamov_dst {
  296. SAR = 0,
  297. CCR,
  298. DAR,
  299. };
  300. enum pl330_dst {
  301. SRC = 0,
  302. DST,
  303. };
  304. enum pl330_cond {
  305. SINGLE,
  306. BURST,
  307. ALWAYS,
  308. };
  309. struct dma_pl330_desc;
  310. struct _pl330_req {
  311. u32 mc_bus;
  312. void *mc_cpu;
  313. struct dma_pl330_desc *desc;
  314. };
  315. /* ToBeDone for tasklet */
  316. struct _pl330_tbd {
  317. bool reset_dmac;
  318. bool reset_mngr;
  319. u8 reset_chan;
  320. };
  321. /* A DMAC Thread */
  322. struct pl330_thread {
  323. u8 id;
  324. int ev;
  325. /* If the channel is not yet acquired by any client */
  326. bool free;
  327. /* Parent DMAC */
  328. struct pl330_dmac *dmac;
  329. /* Only two at a time */
  330. struct _pl330_req req[2];
  331. /* Index of the last enqueued request */
  332. unsigned lstenq;
  333. /* Index of the last submitted request or -1 if the DMA is stopped */
  334. int req_running;
  335. };
  336. enum pl330_dmac_state {
  337. UNINIT,
  338. INIT,
  339. DYING,
  340. };
  341. enum desc_status {
  342. /* In the DMAC pool */
  343. FREE,
  344. /*
  345. * Allocated to some channel during prep_xxx
  346. * Also may be sitting on the work_list.
  347. */
  348. PREP,
  349. /*
  350. * Sitting on the work_list and already submitted
  351. * to the PL330 core. Not more than two descriptors
  352. * of a channel can be BUSY at any time.
  353. */
  354. BUSY,
  355. /*
  356. * Sitting on the channel work_list but xfer done
  357. * by PL330 core
  358. */
  359. DONE,
  360. };
  361. struct dma_pl330_chan {
  362. /* Schedule desc completion */
  363. struct tasklet_struct task;
  364. /* DMA-Engine Channel */
  365. struct dma_chan chan;
  366. /* List of submitted descriptors */
  367. struct list_head submitted_list;
  368. /* List of issued descriptors */
  369. struct list_head work_list;
  370. /* List of completed descriptors */
  371. struct list_head completed_list;
  372. /* Pointer to the DMAC that manages this channel,
  373. * NULL if the channel is available to be acquired.
  374. * As the parent, this DMAC also provides descriptors
  375. * to the channel.
  376. */
  377. struct pl330_dmac *dmac;
  378. /* To protect channel manipulation */
  379. spinlock_t lock;
  380. /*
  381. * Hardware channel thread of PL330 DMAC. NULL if the channel is
  382. * available.
  383. */
  384. struct pl330_thread *thread;
  385. /* For D-to-M and M-to-D channels */
  386. int burst_sz; /* the peripheral fifo width */
  387. int burst_len; /* the number of burst */
  388. phys_addr_t fifo_addr;
  389. /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
  390. dma_addr_t fifo_dma;
  391. enum dma_data_direction dir;
  392. struct dma_slave_config slave_config;
  393. /* for cyclic capability */
  394. bool cyclic;
  395. /* for runtime pm tracking */
  396. bool active;
  397. };
  398. struct pl330_dmac {
  399. /* DMA-Engine Device */
  400. struct dma_device ddma;
  401. /* Pool of descriptors available for the DMAC's channels */
  402. struct list_head desc_pool;
  403. /* To protect desc_pool manipulation */
  404. spinlock_t pool_lock;
  405. /* Size of MicroCode buffers for each channel. */
  406. unsigned mcbufsz;
  407. /* ioremap'ed address of PL330 registers. */
  408. void __iomem *base;
  409. /* Populated by the PL330 core driver during pl330_add */
  410. struct pl330_config pcfg;
  411. spinlock_t lock;
  412. /* Maximum possible events/irqs */
  413. int events[32];
  414. /* BUS address of MicroCode buffer */
  415. dma_addr_t mcode_bus;
  416. /* CPU address of MicroCode buffer */
  417. void *mcode_cpu;
  418. /* List of all Channel threads */
  419. struct pl330_thread *channels;
  420. /* Pointer to the MANAGER thread */
  421. struct pl330_thread *manager;
  422. /* To handle bad news in interrupt */
  423. struct tasklet_struct tasks;
  424. struct _pl330_tbd dmac_tbd;
  425. /* State of DMAC operation */
  426. enum pl330_dmac_state state;
  427. /* Holds list of reqs with due callbacks */
  428. struct list_head req_done;
  429. /* Peripheral channels connected to this DMAC */
  430. unsigned int num_peripherals;
  431. struct dma_pl330_chan *peripherals; /* keep at end */
  432. int quirks;
  433. struct reset_control *rstc;
  434. struct reset_control *rstc_ocp;
  435. };
  436. static struct pl330_of_quirks {
  437. char *quirk;
  438. int id;
  439. } of_quirks[] = {
  440. {
  441. .quirk = "arm,pl330-broken-no-flushp",
  442. .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
  443. },
  444. {
  445. .quirk = "arm,pl330-periph-burst",
  446. .id = PL330_QUIRK_PERIPH_BURST,
  447. }
  448. };
  449. struct dma_pl330_desc {
  450. /* To attach to a queue as child */
  451. struct list_head node;
  452. /* Descriptor for the DMA Engine API */
  453. struct dma_async_tx_descriptor txd;
  454. /* Xfer for PL330 core */
  455. struct pl330_xfer px;
  456. struct pl330_reqcfg rqcfg;
  457. enum desc_status status;
  458. int bytes_requested;
  459. bool last;
  460. /* The channel which currently holds this desc */
  461. struct dma_pl330_chan *pchan;
  462. enum dma_transfer_direction rqtype;
  463. /* Index of peripheral for the xfer. */
  464. unsigned peri:5;
  465. /* Hook to attach to DMAC's list of reqs with due callback */
  466. struct list_head rqd;
  467. };
  468. struct _xfer_spec {
  469. u32 ccr;
  470. struct dma_pl330_desc *desc;
  471. };
  472. static int pl330_config_write(struct dma_chan *chan,
  473. struct dma_slave_config *slave_config,
  474. enum dma_transfer_direction direction);
  475. static inline bool _queue_full(struct pl330_thread *thrd)
  476. {
  477. return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
  478. }
  479. static inline bool is_manager(struct pl330_thread *thrd)
  480. {
  481. return thrd->dmac->manager == thrd;
  482. }
  483. /* If manager of the thread is in Non-Secure mode */
  484. static inline bool _manager_ns(struct pl330_thread *thrd)
  485. {
  486. return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
  487. }
  488. static inline u32 get_revision(u32 periph_id)
  489. {
  490. return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
  491. }
  492. static inline u32 _emit_END(unsigned dry_run, u8 buf[])
  493. {
  494. if (dry_run)
  495. return SZ_DMAEND;
  496. buf[0] = CMD_DMAEND;
  497. PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
  498. return SZ_DMAEND;
  499. }
  500. static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
  501. {
  502. if (dry_run)
  503. return SZ_DMAFLUSHP;
  504. buf[0] = CMD_DMAFLUSHP;
  505. peri &= 0x1f;
  506. peri <<= 3;
  507. buf[1] = peri;
  508. PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
  509. return SZ_DMAFLUSHP;
  510. }
  511. static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
  512. {
  513. if (dry_run)
  514. return SZ_DMALD;
  515. buf[0] = CMD_DMALD;
  516. if (cond == SINGLE)
  517. buf[0] |= (0 << 1) | (1 << 0);
  518. else if (cond == BURST)
  519. buf[0] |= (1 << 1) | (1 << 0);
  520. PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
  521. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
  522. return SZ_DMALD;
  523. }
  524. static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
  525. enum pl330_cond cond, u8 peri)
  526. {
  527. if (dry_run)
  528. return SZ_DMALDP;
  529. buf[0] = CMD_DMALDP;
  530. if (cond == BURST)
  531. buf[0] |= (1 << 1);
  532. peri &= 0x1f;
  533. peri <<= 3;
  534. buf[1] = peri;
  535. PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
  536. cond == SINGLE ? 'S' : 'B', peri >> 3);
  537. return SZ_DMALDP;
  538. }
  539. static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
  540. unsigned loop, u8 cnt)
  541. {
  542. if (dry_run)
  543. return SZ_DMALP;
  544. buf[0] = CMD_DMALP;
  545. if (loop)
  546. buf[0] |= (1 << 1);
  547. cnt--; /* DMAC increments by 1 internally */
  548. buf[1] = cnt;
  549. PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
  550. return SZ_DMALP;
  551. }
  552. struct _arg_LPEND {
  553. enum pl330_cond cond;
  554. bool forever;
  555. unsigned loop;
  556. u8 bjump;
  557. };
  558. static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
  559. const struct _arg_LPEND *arg)
  560. {
  561. enum pl330_cond cond = arg->cond;
  562. bool forever = arg->forever;
  563. unsigned loop = arg->loop;
  564. u8 bjump = arg->bjump;
  565. if (dry_run)
  566. return SZ_DMALPEND;
  567. buf[0] = CMD_DMALPEND;
  568. if (loop)
  569. buf[0] |= (1 << 2);
  570. if (!forever)
  571. buf[0] |= (1 << 4);
  572. if (cond == SINGLE)
  573. buf[0] |= (0 << 1) | (1 << 0);
  574. else if (cond == BURST)
  575. buf[0] |= (1 << 1) | (1 << 0);
  576. buf[1] = bjump;
  577. PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
  578. forever ? "FE" : "END",
  579. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
  580. loop ? '1' : '0',
  581. bjump);
  582. return SZ_DMALPEND;
  583. }
  584. static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
  585. {
  586. if (dry_run)
  587. return SZ_DMAKILL;
  588. buf[0] = CMD_DMAKILL;
  589. return SZ_DMAKILL;
  590. }
  591. static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
  592. enum dmamov_dst dst, u32 val)
  593. {
  594. if (dry_run)
  595. return SZ_DMAMOV;
  596. buf[0] = CMD_DMAMOV;
  597. buf[1] = dst;
  598. buf[2] = val;
  599. buf[3] = val >> 8;
  600. buf[4] = val >> 16;
  601. buf[5] = val >> 24;
  602. PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
  603. dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
  604. return SZ_DMAMOV;
  605. }
  606. static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
  607. {
  608. if (dry_run)
  609. return SZ_DMARMB;
  610. buf[0] = CMD_DMARMB;
  611. PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
  612. return SZ_DMARMB;
  613. }
  614. static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
  615. {
  616. if (dry_run)
  617. return SZ_DMASEV;
  618. buf[0] = CMD_DMASEV;
  619. ev &= 0x1f;
  620. ev <<= 3;
  621. buf[1] = ev;
  622. PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
  623. return SZ_DMASEV;
  624. }
  625. static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
  626. {
  627. if (dry_run)
  628. return SZ_DMAST;
  629. buf[0] = CMD_DMAST;
  630. if (cond == SINGLE)
  631. buf[0] |= (0 << 1) | (1 << 0);
  632. else if (cond == BURST)
  633. buf[0] |= (1 << 1) | (1 << 0);
  634. PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
  635. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
  636. return SZ_DMAST;
  637. }
  638. static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
  639. enum pl330_cond cond, u8 peri)
  640. {
  641. if (dry_run)
  642. return SZ_DMASTP;
  643. buf[0] = CMD_DMASTP;
  644. if (cond == BURST)
  645. buf[0] |= (1 << 1);
  646. peri &= 0x1f;
  647. peri <<= 3;
  648. buf[1] = peri;
  649. PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
  650. cond == SINGLE ? 'S' : 'B', peri >> 3);
  651. return SZ_DMASTP;
  652. }
  653. static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
  654. enum pl330_cond cond, u8 peri)
  655. {
  656. if (dry_run)
  657. return SZ_DMAWFP;
  658. buf[0] = CMD_DMAWFP;
  659. if (cond == SINGLE)
  660. buf[0] |= (0 << 1) | (0 << 0);
  661. else if (cond == BURST)
  662. buf[0] |= (1 << 1) | (0 << 0);
  663. else
  664. buf[0] |= (0 << 1) | (1 << 0);
  665. peri &= 0x1f;
  666. peri <<= 3;
  667. buf[1] = peri;
  668. PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
  669. cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
  670. return SZ_DMAWFP;
  671. }
  672. static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
  673. {
  674. if (dry_run)
  675. return SZ_DMAWMB;
  676. buf[0] = CMD_DMAWMB;
  677. PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
  678. return SZ_DMAWMB;
  679. }
  680. struct _arg_GO {
  681. u8 chan;
  682. u32 addr;
  683. unsigned ns;
  684. };
  685. static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
  686. const struct _arg_GO *arg)
  687. {
  688. u8 chan = arg->chan;
  689. u32 addr = arg->addr;
  690. unsigned ns = arg->ns;
  691. if (dry_run)
  692. return SZ_DMAGO;
  693. buf[0] = CMD_DMAGO;
  694. buf[0] |= (ns << 1);
  695. buf[1] = chan & 0x7;
  696. buf[2] = addr;
  697. buf[3] = addr >> 8;
  698. buf[4] = addr >> 16;
  699. buf[5] = addr >> 24;
  700. return SZ_DMAGO;
  701. }
  702. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  703. /* Returns Time-Out */
  704. static bool _until_dmac_idle(struct pl330_thread *thrd)
  705. {
  706. void __iomem *regs = thrd->dmac->base;
  707. unsigned long loops = msecs_to_loops(5);
  708. do {
  709. /* Until Manager is Idle */
  710. if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
  711. break;
  712. cpu_relax();
  713. } while (--loops);
  714. if (!loops)
  715. return true;
  716. return false;
  717. }
  718. static inline void _execute_DBGINSN(struct pl330_thread *thrd,
  719. u8 insn[], bool as_manager)
  720. {
  721. void __iomem *regs = thrd->dmac->base;
  722. u32 val;
  723. /* If timed out due to halted state-machine */
  724. if (_until_dmac_idle(thrd)) {
  725. dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
  726. return;
  727. }
  728. val = (insn[0] << 16) | (insn[1] << 24);
  729. if (!as_manager) {
  730. val |= (1 << 0);
  731. val |= (thrd->id << 8); /* Channel Number */
  732. }
  733. writel(val, regs + DBGINST0);
  734. val = le32_to_cpu(*((__le32 *)&insn[2]));
  735. writel(val, regs + DBGINST1);
  736. /* Get going */
  737. writel(0, regs + DBGCMD);
  738. }
  739. static inline u32 _state(struct pl330_thread *thrd)
  740. {
  741. void __iomem *regs = thrd->dmac->base;
  742. u32 val;
  743. if (is_manager(thrd))
  744. val = readl(regs + DS) & 0xf;
  745. else
  746. val = readl(regs + CS(thrd->id)) & 0xf;
  747. switch (val) {
  748. case DS_ST_STOP:
  749. return PL330_STATE_STOPPED;
  750. case DS_ST_EXEC:
  751. return PL330_STATE_EXECUTING;
  752. case DS_ST_CMISS:
  753. return PL330_STATE_CACHEMISS;
  754. case DS_ST_UPDTPC:
  755. return PL330_STATE_UPDTPC;
  756. case DS_ST_WFE:
  757. return PL330_STATE_WFE;
  758. case DS_ST_FAULT:
  759. return PL330_STATE_FAULTING;
  760. case DS_ST_ATBRR:
  761. if (is_manager(thrd))
  762. return PL330_STATE_INVALID;
  763. else
  764. return PL330_STATE_ATBARRIER;
  765. case DS_ST_QBUSY:
  766. if (is_manager(thrd))
  767. return PL330_STATE_INVALID;
  768. else
  769. return PL330_STATE_QUEUEBUSY;
  770. case DS_ST_WFP:
  771. if (is_manager(thrd))
  772. return PL330_STATE_INVALID;
  773. else
  774. return PL330_STATE_WFP;
  775. case DS_ST_KILL:
  776. if (is_manager(thrd))
  777. return PL330_STATE_INVALID;
  778. else
  779. return PL330_STATE_KILLING;
  780. case DS_ST_CMPLT:
  781. if (is_manager(thrd))
  782. return PL330_STATE_INVALID;
  783. else
  784. return PL330_STATE_COMPLETING;
  785. case DS_ST_FLTCMP:
  786. if (is_manager(thrd))
  787. return PL330_STATE_INVALID;
  788. else
  789. return PL330_STATE_FAULT_COMPLETING;
  790. default:
  791. return PL330_STATE_INVALID;
  792. }
  793. }
  794. static void _stop(struct pl330_thread *thrd)
  795. {
  796. void __iomem *regs = thrd->dmac->base;
  797. u8 insn[6] = {0, 0, 0, 0, 0, 0};
  798. u32 inten = readl(regs + INTEN);
  799. if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
  800. UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
  801. /* Return if nothing needs to be done */
  802. if (_state(thrd) == PL330_STATE_COMPLETING
  803. || _state(thrd) == PL330_STATE_KILLING
  804. || _state(thrd) == PL330_STATE_STOPPED)
  805. return;
  806. _emit_KILL(0, insn);
  807. _execute_DBGINSN(thrd, insn, is_manager(thrd));
  808. /* clear the event */
  809. if (inten & (1 << thrd->ev))
  810. writel(1 << thrd->ev, regs + INTCLR);
  811. /* Stop generating interrupts for SEV */
  812. writel(inten & ~(1 << thrd->ev), regs + INTEN);
  813. }
  814. /* Start doing req 'idx' of thread 'thrd' */
  815. static bool _trigger(struct pl330_thread *thrd)
  816. {
  817. void __iomem *regs = thrd->dmac->base;
  818. struct _pl330_req *req;
  819. struct dma_pl330_desc *desc;
  820. struct _arg_GO go;
  821. unsigned ns;
  822. u8 insn[6] = {0, 0, 0, 0, 0, 0};
  823. int idx;
  824. /* Return if already ACTIVE */
  825. if (_state(thrd) != PL330_STATE_STOPPED)
  826. return true;
  827. idx = 1 - thrd->lstenq;
  828. if (thrd->req[idx].desc != NULL) {
  829. req = &thrd->req[idx];
  830. } else {
  831. idx = thrd->lstenq;
  832. if (thrd->req[idx].desc != NULL)
  833. req = &thrd->req[idx];
  834. else
  835. req = NULL;
  836. }
  837. /* Return if no request */
  838. if (!req)
  839. return true;
  840. /* Return if req is running */
  841. if (idx == thrd->req_running)
  842. return true;
  843. desc = req->desc;
  844. ns = desc->rqcfg.nonsecure ? 1 : 0;
  845. /* See 'Abort Sources' point-4 at Page 2-25 */
  846. if (_manager_ns(thrd) && !ns)
  847. dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
  848. __func__, __LINE__);
  849. go.chan = thrd->id;
  850. go.addr = req->mc_bus;
  851. go.ns = ns;
  852. _emit_GO(0, insn, &go);
  853. /* Set to generate interrupts for SEV */
  854. writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
  855. /* Only manager can execute GO */
  856. _execute_DBGINSN(thrd, insn, true);
  857. thrd->req_running = idx;
  858. return true;
  859. }
  860. static bool _start(struct pl330_thread *thrd)
  861. {
  862. switch (_state(thrd)) {
  863. case PL330_STATE_FAULT_COMPLETING:
  864. UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
  865. if (_state(thrd) == PL330_STATE_KILLING)
  866. UNTIL(thrd, PL330_STATE_STOPPED)
  867. fallthrough;
  868. case PL330_STATE_FAULTING:
  869. _stop(thrd);
  870. fallthrough;
  871. case PL330_STATE_KILLING:
  872. case PL330_STATE_COMPLETING:
  873. UNTIL(thrd, PL330_STATE_STOPPED)
  874. fallthrough;
  875. case PL330_STATE_STOPPED:
  876. return _trigger(thrd);
  877. case PL330_STATE_WFP:
  878. case PL330_STATE_QUEUEBUSY:
  879. case PL330_STATE_ATBARRIER:
  880. case PL330_STATE_UPDTPC:
  881. case PL330_STATE_CACHEMISS:
  882. case PL330_STATE_EXECUTING:
  883. return true;
  884. case PL330_STATE_WFE: /* For RESUME, nothing yet */
  885. default:
  886. return false;
  887. }
  888. }
  889. static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
  890. const struct _xfer_spec *pxs, int cyc)
  891. {
  892. int off = 0;
  893. struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
  894. /* check lock-up free version */
  895. if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
  896. while (cyc--) {
  897. off += _emit_LD(dry_run, &buf[off], ALWAYS);
  898. off += _emit_ST(dry_run, &buf[off], ALWAYS);
  899. }
  900. } else {
  901. while (cyc--) {
  902. off += _emit_LD(dry_run, &buf[off], ALWAYS);
  903. off += _emit_RMB(dry_run, &buf[off]);
  904. off += _emit_ST(dry_run, &buf[off], ALWAYS);
  905. off += _emit_WMB(dry_run, &buf[off]);
  906. }
  907. }
  908. return off;
  909. }
  910. static u32 _emit_load(unsigned int dry_run, u8 buf[],
  911. enum pl330_cond cond, enum dma_transfer_direction direction,
  912. u8 peri)
  913. {
  914. int off = 0;
  915. switch (direction) {
  916. case DMA_MEM_TO_MEM:
  917. case DMA_MEM_TO_DEV:
  918. off += _emit_LD(dry_run, &buf[off], cond);
  919. break;
  920. case DMA_DEV_TO_MEM:
  921. if (cond == ALWAYS) {
  922. off += _emit_LDP(dry_run, &buf[off], SINGLE,
  923. peri);
  924. off += _emit_LDP(dry_run, &buf[off], BURST,
  925. peri);
  926. } else {
  927. off += _emit_LDP(dry_run, &buf[off], cond,
  928. peri);
  929. }
  930. break;
  931. default:
  932. /* this code should be unreachable */
  933. WARN_ON(1);
  934. break;
  935. }
  936. return off;
  937. }
  938. static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
  939. enum pl330_cond cond, enum dma_transfer_direction direction,
  940. u8 peri)
  941. {
  942. int off = 0;
  943. switch (direction) {
  944. case DMA_MEM_TO_MEM:
  945. case DMA_DEV_TO_MEM:
  946. off += _emit_ST(dry_run, &buf[off], cond);
  947. break;
  948. case DMA_MEM_TO_DEV:
  949. if (cond == ALWAYS) {
  950. off += _emit_STP(dry_run, &buf[off], SINGLE,
  951. peri);
  952. off += _emit_STP(dry_run, &buf[off], BURST,
  953. peri);
  954. } else {
  955. off += _emit_STP(dry_run, &buf[off], cond,
  956. peri);
  957. }
  958. break;
  959. default:
  960. /* this code should be unreachable */
  961. WARN_ON(1);
  962. break;
  963. }
  964. return off;
  965. }
  966. static inline int _ldst_peripheral(struct pl330_dmac *pl330,
  967. unsigned dry_run, u8 buf[],
  968. const struct _xfer_spec *pxs, int cyc,
  969. enum pl330_cond cond)
  970. {
  971. int off = 0;
  972. /*
  973. * do FLUSHP at beginning to clear any stale dma requests before the
  974. * first WFP.
  975. */
  976. if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
  977. off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
  978. while (cyc--) {
  979. off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
  980. off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
  981. pxs->desc->peri);
  982. off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
  983. pxs->desc->peri);
  984. }
  985. return off;
  986. }
  987. static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
  988. const struct _xfer_spec *pxs, int cyc)
  989. {
  990. int off = 0;
  991. enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
  992. if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
  993. cond = BURST;
  994. switch (pxs->desc->rqtype) {
  995. case DMA_MEM_TO_DEV:
  996. case DMA_DEV_TO_MEM:
  997. off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
  998. cond);
  999. break;
  1000. case DMA_MEM_TO_MEM:
  1001. off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
  1002. break;
  1003. default:
  1004. /* this code should be unreachable */
  1005. WARN_ON(1);
  1006. break;
  1007. }
  1008. return off;
  1009. }
  1010. /*
  1011. * only the unaligned burst transfers have the dregs.
  1012. * so, still transfer dregs with a reduced size burst
  1013. * for mem-to-mem, mem-to-dev or dev-to-mem.
  1014. */
  1015. static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
  1016. const struct _xfer_spec *pxs, int transfer_length)
  1017. {
  1018. int off = 0;
  1019. int dregs_ccr;
  1020. if (transfer_length == 0)
  1021. return off;
  1022. /*
  1023. * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
  1024. * BRST_SIZE(ccr)
  1025. * the dregs len must be smaller than burst len,
  1026. * so, for higher efficiency, we can modify CCR
  1027. * to use a reduced size burst len for the dregs.
  1028. */
  1029. dregs_ccr = pxs->ccr;
  1030. dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
  1031. (0xf << CC_DSTBRSTLEN_SHFT));
  1032. dregs_ccr |= (((transfer_length - 1) & 0xf) <<
  1033. CC_SRCBRSTLEN_SHFT);
  1034. dregs_ccr |= (((transfer_length - 1) & 0xf) <<
  1035. CC_DSTBRSTLEN_SHFT);
  1036. switch (pxs->desc->rqtype) {
  1037. case DMA_MEM_TO_DEV:
  1038. case DMA_DEV_TO_MEM:
  1039. off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
  1040. off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
  1041. BURST);
  1042. break;
  1043. case DMA_MEM_TO_MEM:
  1044. off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
  1045. off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
  1046. break;
  1047. default:
  1048. /* this code should be unreachable */
  1049. WARN_ON(1);
  1050. break;
  1051. }
  1052. return off;
  1053. }
  1054. /* Returns bytes consumed and updates bursts */
  1055. static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
  1056. unsigned long *bursts, const struct _xfer_spec *pxs)
  1057. {
  1058. int cyc, cycmax, szlp, szlpend, szbrst, off;
  1059. unsigned lcnt0, lcnt1, ljmp0, ljmp1;
  1060. struct _arg_LPEND lpend;
  1061. if (*bursts == 1)
  1062. return _bursts(pl330, dry_run, buf, pxs, 1);
  1063. /* Max iterations possible in DMALP is 256 */
  1064. if (*bursts >= 256*256) {
  1065. lcnt1 = 256;
  1066. lcnt0 = 256;
  1067. cyc = *bursts / lcnt1 / lcnt0;
  1068. } else if (*bursts > 256) {
  1069. lcnt1 = 256;
  1070. lcnt0 = *bursts / lcnt1;
  1071. cyc = 1;
  1072. } else {
  1073. lcnt1 = *bursts;
  1074. lcnt0 = 0;
  1075. cyc = 1;
  1076. }
  1077. szlp = _emit_LP(1, buf, 0, 0);
  1078. szbrst = _bursts(pl330, 1, buf, pxs, 1);
  1079. lpend.cond = ALWAYS;
  1080. lpend.forever = false;
  1081. lpend.loop = 0;
  1082. lpend.bjump = 0;
  1083. szlpend = _emit_LPEND(1, buf, &lpend);
  1084. if (lcnt0) {
  1085. szlp *= 2;
  1086. szlpend *= 2;
  1087. }
  1088. /*
  1089. * Max bursts that we can unroll due to limit on the
  1090. * size of backward jump that can be encoded in DMALPEND
  1091. * which is 8-bits and hence 255
  1092. */
  1093. cycmax = (255 - (szlp + szlpend)) / szbrst;
  1094. cyc = (cycmax < cyc) ? cycmax : cyc;
  1095. off = 0;
  1096. if (lcnt0) {
  1097. off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
  1098. ljmp0 = off;
  1099. }
  1100. off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
  1101. ljmp1 = off;
  1102. off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
  1103. lpend.cond = ALWAYS;
  1104. lpend.forever = false;
  1105. lpend.loop = 1;
  1106. lpend.bjump = off - ljmp1;
  1107. off += _emit_LPEND(dry_run, &buf[off], &lpend);
  1108. if (lcnt0) {
  1109. lpend.cond = ALWAYS;
  1110. lpend.forever = false;
  1111. lpend.loop = 0;
  1112. lpend.bjump = off - ljmp0;
  1113. off += _emit_LPEND(dry_run, &buf[off], &lpend);
  1114. }
  1115. *bursts = lcnt1 * cyc;
  1116. if (lcnt0)
  1117. *bursts *= lcnt0;
  1118. return off;
  1119. }
  1120. static inline int _setup_loops(struct pl330_dmac *pl330,
  1121. unsigned dry_run, u8 buf[],
  1122. const struct _xfer_spec *pxs)
  1123. {
  1124. struct pl330_xfer *x = &pxs->desc->px;
  1125. u32 ccr = pxs->ccr;
  1126. unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
  1127. int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
  1128. BRST_SIZE(ccr);
  1129. int off = 0;
  1130. while (bursts) {
  1131. c = bursts;
  1132. off += _loop(pl330, dry_run, &buf[off], &c, pxs);
  1133. bursts -= c;
  1134. }
  1135. off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
  1136. return off;
  1137. }
  1138. static inline int _setup_xfer(struct pl330_dmac *pl330,
  1139. unsigned dry_run, u8 buf[],
  1140. const struct _xfer_spec *pxs)
  1141. {
  1142. struct pl330_xfer *x = &pxs->desc->px;
  1143. int off = 0;
  1144. /* DMAMOV SAR, x->src_addr */
  1145. off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
  1146. /* DMAMOV DAR, x->dst_addr */
  1147. off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
  1148. /* Setup Loop(s) */
  1149. off += _setup_loops(pl330, dry_run, &buf[off], pxs);
  1150. return off;
  1151. }
  1152. /*
  1153. * A req is a sequence of one or more xfer units.
  1154. * Returns the number of bytes taken to setup the MC for the req.
  1155. */
  1156. static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
  1157. struct pl330_thread *thrd, unsigned index,
  1158. struct _xfer_spec *pxs)
  1159. {
  1160. struct _pl330_req *req = &thrd->req[index];
  1161. u8 *buf = req->mc_cpu;
  1162. int off = 0;
  1163. PL330_DBGMC_START(req->mc_bus);
  1164. /* DMAMOV CCR, ccr */
  1165. off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
  1166. off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
  1167. /* DMASEV peripheral/event */
  1168. off += _emit_SEV(dry_run, &buf[off], thrd->ev);
  1169. /* DMAEND */
  1170. off += _emit_END(dry_run, &buf[off]);
  1171. return off;
  1172. }
  1173. static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
  1174. {
  1175. u32 ccr = 0;
  1176. if (rqc->src_inc)
  1177. ccr |= CC_SRCINC;
  1178. if (rqc->dst_inc)
  1179. ccr |= CC_DSTINC;
  1180. /* We set same protection levels for Src and DST for now */
  1181. if (rqc->privileged)
  1182. ccr |= CC_SRCPRI | CC_DSTPRI;
  1183. if (rqc->nonsecure)
  1184. ccr |= CC_SRCNS | CC_DSTNS;
  1185. if (rqc->insnaccess)
  1186. ccr |= CC_SRCIA | CC_DSTIA;
  1187. ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
  1188. ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
  1189. ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
  1190. ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
  1191. ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
  1192. ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
  1193. ccr |= (rqc->swap << CC_SWAP_SHFT);
  1194. return ccr;
  1195. }
  1196. /*
  1197. * Submit a list of xfers after which the client wants notification.
  1198. * Client is not notified after each xfer unit, just once after all
  1199. * xfer units are done or some error occurs.
  1200. */
  1201. static int pl330_submit_req(struct pl330_thread *thrd,
  1202. struct dma_pl330_desc *desc)
  1203. {
  1204. struct pl330_dmac *pl330 = thrd->dmac;
  1205. struct _xfer_spec xs;
  1206. unsigned long flags;
  1207. unsigned idx;
  1208. u32 ccr;
  1209. int ret = 0;
  1210. switch (desc->rqtype) {
  1211. case DMA_MEM_TO_DEV:
  1212. break;
  1213. case DMA_DEV_TO_MEM:
  1214. break;
  1215. case DMA_MEM_TO_MEM:
  1216. break;
  1217. default:
  1218. return -ENOTSUPP;
  1219. }
  1220. if (pl330->state == DYING
  1221. || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
  1222. dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
  1223. __func__, __LINE__);
  1224. return -EAGAIN;
  1225. }
  1226. /* If request for non-existing peripheral */
  1227. if (desc->rqtype != DMA_MEM_TO_MEM &&
  1228. desc->peri >= pl330->pcfg.num_peri) {
  1229. dev_info(thrd->dmac->ddma.dev,
  1230. "%s:%d Invalid peripheral(%u)!\n",
  1231. __func__, __LINE__, desc->peri);
  1232. return -EINVAL;
  1233. }
  1234. spin_lock_irqsave(&pl330->lock, flags);
  1235. if (_queue_full(thrd)) {
  1236. ret = -EAGAIN;
  1237. goto xfer_exit;
  1238. }
  1239. /* Prefer Secure Channel */
  1240. if (!_manager_ns(thrd))
  1241. desc->rqcfg.nonsecure = 0;
  1242. else
  1243. desc->rqcfg.nonsecure = 1;
  1244. ccr = _prepare_ccr(&desc->rqcfg);
  1245. idx = thrd->req[0].desc == NULL ? 0 : 1;
  1246. xs.ccr = ccr;
  1247. xs.desc = desc;
  1248. /* First dry run to check if req is acceptable */
  1249. ret = _setup_req(pl330, 1, thrd, idx, &xs);
  1250. if (ret < 0)
  1251. goto xfer_exit;
  1252. if (ret > pl330->mcbufsz / 2) {
  1253. dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
  1254. __func__, __LINE__, ret, pl330->mcbufsz / 2);
  1255. ret = -ENOMEM;
  1256. goto xfer_exit;
  1257. }
  1258. /* Hook the request */
  1259. thrd->lstenq = idx;
  1260. thrd->req[idx].desc = desc;
  1261. _setup_req(pl330, 0, thrd, idx, &xs);
  1262. ret = 0;
  1263. xfer_exit:
  1264. spin_unlock_irqrestore(&pl330->lock, flags);
  1265. return ret;
  1266. }
  1267. static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
  1268. {
  1269. struct dma_pl330_chan *pch;
  1270. unsigned long flags;
  1271. if (!desc)
  1272. return;
  1273. pch = desc->pchan;
  1274. /* If desc aborted */
  1275. if (!pch)
  1276. return;
  1277. spin_lock_irqsave(&pch->lock, flags);
  1278. desc->status = DONE;
  1279. spin_unlock_irqrestore(&pch->lock, flags);
  1280. tasklet_schedule(&pch->task);
  1281. }
  1282. static void pl330_dotask(struct tasklet_struct *t)
  1283. {
  1284. struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
  1285. unsigned long flags;
  1286. int i;
  1287. spin_lock_irqsave(&pl330->lock, flags);
  1288. /* The DMAC itself gone nuts */
  1289. if (pl330->dmac_tbd.reset_dmac) {
  1290. pl330->state = DYING;
  1291. /* Reset the manager too */
  1292. pl330->dmac_tbd.reset_mngr = true;
  1293. /* Clear the reset flag */
  1294. pl330->dmac_tbd.reset_dmac = false;
  1295. }
  1296. if (pl330->dmac_tbd.reset_mngr) {
  1297. _stop(pl330->manager);
  1298. /* Reset all channels */
  1299. pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
  1300. /* Clear the reset flag */
  1301. pl330->dmac_tbd.reset_mngr = false;
  1302. }
  1303. for (i = 0; i < pl330->pcfg.num_chan; i++) {
  1304. if (pl330->dmac_tbd.reset_chan & (1 << i)) {
  1305. struct pl330_thread *thrd = &pl330->channels[i];
  1306. void __iomem *regs = pl330->base;
  1307. enum pl330_op_err err;
  1308. _stop(thrd);
  1309. if (readl(regs + FSC) & (1 << thrd->id))
  1310. err = PL330_ERR_FAIL;
  1311. else
  1312. err = PL330_ERR_ABORT;
  1313. spin_unlock_irqrestore(&pl330->lock, flags);
  1314. dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
  1315. dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
  1316. spin_lock_irqsave(&pl330->lock, flags);
  1317. thrd->req[0].desc = NULL;
  1318. thrd->req[1].desc = NULL;
  1319. thrd->req_running = -1;
  1320. /* Clear the reset flag */
  1321. pl330->dmac_tbd.reset_chan &= ~(1 << i);
  1322. }
  1323. }
  1324. spin_unlock_irqrestore(&pl330->lock, flags);
  1325. return;
  1326. }
  1327. /* Returns 1 if state was updated, 0 otherwise */
  1328. static int pl330_update(struct pl330_dmac *pl330)
  1329. {
  1330. struct dma_pl330_desc *descdone;
  1331. unsigned long flags;
  1332. void __iomem *regs;
  1333. u32 val;
  1334. int id, ev, ret = 0;
  1335. regs = pl330->base;
  1336. spin_lock_irqsave(&pl330->lock, flags);
  1337. val = readl(regs + FSM) & 0x1;
  1338. if (val)
  1339. pl330->dmac_tbd.reset_mngr = true;
  1340. else
  1341. pl330->dmac_tbd.reset_mngr = false;
  1342. val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
  1343. pl330->dmac_tbd.reset_chan |= val;
  1344. if (val) {
  1345. int i = 0;
  1346. while (i < pl330->pcfg.num_chan) {
  1347. if (val & (1 << i)) {
  1348. dev_info(pl330->ddma.dev,
  1349. "Reset Channel-%d\t CS-%x FTC-%x\n",
  1350. i, readl(regs + CS(i)),
  1351. readl(regs + FTC(i)));
  1352. _stop(&pl330->channels[i]);
  1353. }
  1354. i++;
  1355. }
  1356. }
  1357. /* Check which event happened i.e, thread notified */
  1358. val = readl(regs + ES);
  1359. if (pl330->pcfg.num_events < 32
  1360. && val & ~((1 << pl330->pcfg.num_events) - 1)) {
  1361. pl330->dmac_tbd.reset_dmac = true;
  1362. dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
  1363. __LINE__);
  1364. ret = 1;
  1365. goto updt_exit;
  1366. }
  1367. for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
  1368. if (val & (1 << ev)) { /* Event occurred */
  1369. struct pl330_thread *thrd;
  1370. u32 inten = readl(regs + INTEN);
  1371. int active;
  1372. /* Clear the event */
  1373. if (inten & (1 << ev))
  1374. writel(1 << ev, regs + INTCLR);
  1375. ret = 1;
  1376. id = pl330->events[ev];
  1377. thrd = &pl330->channels[id];
  1378. active = thrd->req_running;
  1379. if (active == -1) /* Aborted */
  1380. continue;
  1381. /* Detach the req */
  1382. descdone = thrd->req[active].desc;
  1383. thrd->req[active].desc = NULL;
  1384. thrd->req_running = -1;
  1385. /* Get going again ASAP */
  1386. _start(thrd);
  1387. /* For now, just make a list of callbacks to be done */
  1388. list_add_tail(&descdone->rqd, &pl330->req_done);
  1389. }
  1390. }
  1391. /* Now that we are in no hurry, do the callbacks */
  1392. while (!list_empty(&pl330->req_done)) {
  1393. descdone = list_first_entry(&pl330->req_done,
  1394. struct dma_pl330_desc, rqd);
  1395. list_del(&descdone->rqd);
  1396. spin_unlock_irqrestore(&pl330->lock, flags);
  1397. dma_pl330_rqcb(descdone, PL330_ERR_NONE);
  1398. spin_lock_irqsave(&pl330->lock, flags);
  1399. }
  1400. updt_exit:
  1401. spin_unlock_irqrestore(&pl330->lock, flags);
  1402. if (pl330->dmac_tbd.reset_dmac
  1403. || pl330->dmac_tbd.reset_mngr
  1404. || pl330->dmac_tbd.reset_chan) {
  1405. ret = 1;
  1406. tasklet_schedule(&pl330->tasks);
  1407. }
  1408. return ret;
  1409. }
  1410. /* Reserve an event */
  1411. static inline int _alloc_event(struct pl330_thread *thrd)
  1412. {
  1413. struct pl330_dmac *pl330 = thrd->dmac;
  1414. int ev;
  1415. for (ev = 0; ev < pl330->pcfg.num_events; ev++)
  1416. if (pl330->events[ev] == -1) {
  1417. pl330->events[ev] = thrd->id;
  1418. return ev;
  1419. }
  1420. return -1;
  1421. }
  1422. static bool _chan_ns(const struct pl330_dmac *pl330, int i)
  1423. {
  1424. return pl330->pcfg.irq_ns & (1 << i);
  1425. }
  1426. /* Upon success, returns IdentityToken for the
  1427. * allocated channel, NULL otherwise.
  1428. */
  1429. static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
  1430. {
  1431. struct pl330_thread *thrd = NULL;
  1432. int chans, i;
  1433. if (pl330->state == DYING)
  1434. return NULL;
  1435. chans = pl330->pcfg.num_chan;
  1436. for (i = 0; i < chans; i++) {
  1437. thrd = &pl330->channels[i];
  1438. if ((thrd->free) && (!_manager_ns(thrd) ||
  1439. _chan_ns(pl330, i))) {
  1440. thrd->ev = _alloc_event(thrd);
  1441. if (thrd->ev >= 0) {
  1442. thrd->free = false;
  1443. thrd->lstenq = 1;
  1444. thrd->req[0].desc = NULL;
  1445. thrd->req[1].desc = NULL;
  1446. thrd->req_running = -1;
  1447. break;
  1448. }
  1449. }
  1450. thrd = NULL;
  1451. }
  1452. return thrd;
  1453. }
  1454. /* Release an event */
  1455. static inline void _free_event(struct pl330_thread *thrd, int ev)
  1456. {
  1457. struct pl330_dmac *pl330 = thrd->dmac;
  1458. /* If the event is valid and was held by the thread */
  1459. if (ev >= 0 && ev < pl330->pcfg.num_events
  1460. && pl330->events[ev] == thrd->id)
  1461. pl330->events[ev] = -1;
  1462. }
  1463. static void pl330_release_channel(struct pl330_thread *thrd)
  1464. {
  1465. if (!thrd || thrd->free)
  1466. return;
  1467. _stop(thrd);
  1468. dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
  1469. dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
  1470. _free_event(thrd, thrd->ev);
  1471. thrd->free = true;
  1472. }
  1473. /* Initialize the structure for PL330 configuration, that can be used
  1474. * by the client driver the make best use of the DMAC
  1475. */
  1476. static void read_dmac_config(struct pl330_dmac *pl330)
  1477. {
  1478. void __iomem *regs = pl330->base;
  1479. u32 val;
  1480. val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
  1481. val &= CRD_DATA_WIDTH_MASK;
  1482. pl330->pcfg.data_bus_width = 8 * (1 << val);
  1483. val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
  1484. val &= CRD_DATA_BUFF_MASK;
  1485. pl330->pcfg.data_buf_dep = val + 1;
  1486. val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
  1487. val &= CR0_NUM_CHANS_MASK;
  1488. val += 1;
  1489. pl330->pcfg.num_chan = val;
  1490. val = readl(regs + CR0);
  1491. if (val & CR0_PERIPH_REQ_SET) {
  1492. val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
  1493. val += 1;
  1494. pl330->pcfg.num_peri = val;
  1495. pl330->pcfg.peri_ns = readl(regs + CR4);
  1496. } else {
  1497. pl330->pcfg.num_peri = 0;
  1498. }
  1499. val = readl(regs + CR0);
  1500. if (val & CR0_BOOT_MAN_NS)
  1501. pl330->pcfg.mode |= DMAC_MODE_NS;
  1502. else
  1503. pl330->pcfg.mode &= ~DMAC_MODE_NS;
  1504. val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
  1505. val &= CR0_NUM_EVENTS_MASK;
  1506. val += 1;
  1507. pl330->pcfg.num_events = val;
  1508. pl330->pcfg.irq_ns = readl(regs + CR3);
  1509. }
  1510. static inline void _reset_thread(struct pl330_thread *thrd)
  1511. {
  1512. struct pl330_dmac *pl330 = thrd->dmac;
  1513. thrd->req[0].mc_cpu = pl330->mcode_cpu
  1514. + (thrd->id * pl330->mcbufsz);
  1515. thrd->req[0].mc_bus = pl330->mcode_bus
  1516. + (thrd->id * pl330->mcbufsz);
  1517. thrd->req[0].desc = NULL;
  1518. thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
  1519. + pl330->mcbufsz / 2;
  1520. thrd->req[1].mc_bus = thrd->req[0].mc_bus
  1521. + pl330->mcbufsz / 2;
  1522. thrd->req[1].desc = NULL;
  1523. thrd->req_running = -1;
  1524. }
  1525. static int dmac_alloc_threads(struct pl330_dmac *pl330)
  1526. {
  1527. int chans = pl330->pcfg.num_chan;
  1528. struct pl330_thread *thrd;
  1529. int i;
  1530. /* Allocate 1 Manager and 'chans' Channel threads */
  1531. pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
  1532. GFP_KERNEL);
  1533. if (!pl330->channels)
  1534. return -ENOMEM;
  1535. /* Init Channel threads */
  1536. for (i = 0; i < chans; i++) {
  1537. thrd = &pl330->channels[i];
  1538. thrd->id = i;
  1539. thrd->dmac = pl330;
  1540. _reset_thread(thrd);
  1541. thrd->free = true;
  1542. }
  1543. /* MANAGER is indexed at the end */
  1544. thrd = &pl330->channels[chans];
  1545. thrd->id = chans;
  1546. thrd->dmac = pl330;
  1547. thrd->free = false;
  1548. pl330->manager = thrd;
  1549. return 0;
  1550. }
  1551. static int dmac_alloc_resources(struct pl330_dmac *pl330)
  1552. {
  1553. int chans = pl330->pcfg.num_chan;
  1554. int ret;
  1555. /*
  1556. * Alloc MicroCode buffer for 'chans' Channel threads.
  1557. * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
  1558. */
  1559. pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
  1560. chans * pl330->mcbufsz,
  1561. &pl330->mcode_bus, GFP_KERNEL,
  1562. DMA_ATTR_PRIVILEGED);
  1563. if (!pl330->mcode_cpu) {
  1564. dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
  1565. __func__, __LINE__);
  1566. return -ENOMEM;
  1567. }
  1568. ret = dmac_alloc_threads(pl330);
  1569. if (ret) {
  1570. dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
  1571. __func__, __LINE__);
  1572. dma_free_attrs(pl330->ddma.dev,
  1573. chans * pl330->mcbufsz,
  1574. pl330->mcode_cpu, pl330->mcode_bus,
  1575. DMA_ATTR_PRIVILEGED);
  1576. return ret;
  1577. }
  1578. return 0;
  1579. }
  1580. static int pl330_add(struct pl330_dmac *pl330)
  1581. {
  1582. int i, ret;
  1583. /* Check if we can handle this DMAC */
  1584. if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
  1585. dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
  1586. pl330->pcfg.periph_id);
  1587. return -EINVAL;
  1588. }
  1589. /* Read the configuration of the DMAC */
  1590. read_dmac_config(pl330);
  1591. if (pl330->pcfg.num_events == 0) {
  1592. dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
  1593. __func__, __LINE__);
  1594. return -EINVAL;
  1595. }
  1596. spin_lock_init(&pl330->lock);
  1597. INIT_LIST_HEAD(&pl330->req_done);
  1598. /* Use default MC buffer size if not provided */
  1599. if (!pl330->mcbufsz)
  1600. pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
  1601. /* Mark all events as free */
  1602. for (i = 0; i < pl330->pcfg.num_events; i++)
  1603. pl330->events[i] = -1;
  1604. /* Allocate resources needed by the DMAC */
  1605. ret = dmac_alloc_resources(pl330);
  1606. if (ret) {
  1607. dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
  1608. return ret;
  1609. }
  1610. tasklet_setup(&pl330->tasks, pl330_dotask);
  1611. pl330->state = INIT;
  1612. return 0;
  1613. }
  1614. static int dmac_free_threads(struct pl330_dmac *pl330)
  1615. {
  1616. struct pl330_thread *thrd;
  1617. int i;
  1618. /* Release Channel threads */
  1619. for (i = 0; i < pl330->pcfg.num_chan; i++) {
  1620. thrd = &pl330->channels[i];
  1621. pl330_release_channel(thrd);
  1622. }
  1623. /* Free memory */
  1624. kfree(pl330->channels);
  1625. return 0;
  1626. }
  1627. static void pl330_del(struct pl330_dmac *pl330)
  1628. {
  1629. pl330->state = UNINIT;
  1630. tasklet_kill(&pl330->tasks);
  1631. /* Free DMAC resources */
  1632. dmac_free_threads(pl330);
  1633. dma_free_attrs(pl330->ddma.dev,
  1634. pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
  1635. pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
  1636. }
  1637. /* forward declaration */
  1638. static struct amba_driver pl330_driver;
  1639. static inline struct dma_pl330_chan *
  1640. to_pchan(struct dma_chan *ch)
  1641. {
  1642. if (!ch)
  1643. return NULL;
  1644. return container_of(ch, struct dma_pl330_chan, chan);
  1645. }
  1646. static inline struct dma_pl330_desc *
  1647. to_desc(struct dma_async_tx_descriptor *tx)
  1648. {
  1649. return container_of(tx, struct dma_pl330_desc, txd);
  1650. }
  1651. static inline void fill_queue(struct dma_pl330_chan *pch)
  1652. {
  1653. struct dma_pl330_desc *desc;
  1654. int ret;
  1655. list_for_each_entry(desc, &pch->work_list, node) {
  1656. /* If already submitted */
  1657. if (desc->status == BUSY)
  1658. continue;
  1659. ret = pl330_submit_req(pch->thread, desc);
  1660. if (!ret) {
  1661. desc->status = BUSY;
  1662. } else if (ret == -EAGAIN) {
  1663. /* QFull or DMAC Dying */
  1664. break;
  1665. } else {
  1666. /* Unacceptable request */
  1667. desc->status = DONE;
  1668. dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
  1669. __func__, __LINE__, desc->txd.cookie);
  1670. tasklet_schedule(&pch->task);
  1671. }
  1672. }
  1673. }
  1674. static void pl330_tasklet(struct tasklet_struct *t)
  1675. {
  1676. struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
  1677. struct dma_pl330_desc *desc, *_dt;
  1678. unsigned long flags;
  1679. bool power_down = false;
  1680. spin_lock_irqsave(&pch->lock, flags);
  1681. /* Pick up ripe tomatoes */
  1682. list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
  1683. if (desc->status == DONE) {
  1684. if (!pch->cyclic)
  1685. dma_cookie_complete(&desc->txd);
  1686. list_move_tail(&desc->node, &pch->completed_list);
  1687. }
  1688. /* Try to submit a req imm. next to the last completed cookie */
  1689. fill_queue(pch);
  1690. if (list_empty(&pch->work_list)) {
  1691. spin_lock(&pch->thread->dmac->lock);
  1692. _stop(pch->thread);
  1693. spin_unlock(&pch->thread->dmac->lock);
  1694. power_down = true;
  1695. pch->active = false;
  1696. } else {
  1697. /* Make sure the PL330 Channel thread is active */
  1698. spin_lock(&pch->thread->dmac->lock);
  1699. _start(pch->thread);
  1700. spin_unlock(&pch->thread->dmac->lock);
  1701. }
  1702. while (!list_empty(&pch->completed_list)) {
  1703. struct dmaengine_desc_callback cb;
  1704. desc = list_first_entry(&pch->completed_list,
  1705. struct dma_pl330_desc, node);
  1706. dmaengine_desc_get_callback(&desc->txd, &cb);
  1707. if (pch->cyclic) {
  1708. desc->status = PREP;
  1709. list_move_tail(&desc->node, &pch->work_list);
  1710. if (power_down) {
  1711. pch->active = true;
  1712. spin_lock(&pch->thread->dmac->lock);
  1713. _start(pch->thread);
  1714. spin_unlock(&pch->thread->dmac->lock);
  1715. power_down = false;
  1716. }
  1717. } else {
  1718. desc->status = FREE;
  1719. list_move_tail(&desc->node, &pch->dmac->desc_pool);
  1720. }
  1721. dma_descriptor_unmap(&desc->txd);
  1722. if (dmaengine_desc_callback_valid(&cb)) {
  1723. spin_unlock_irqrestore(&pch->lock, flags);
  1724. dmaengine_desc_callback_invoke(&cb, NULL);
  1725. spin_lock_irqsave(&pch->lock, flags);
  1726. }
  1727. }
  1728. spin_unlock_irqrestore(&pch->lock, flags);
  1729. /* If work list empty, power down */
  1730. if (power_down) {
  1731. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1732. pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
  1733. }
  1734. }
  1735. static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
  1736. struct of_dma *ofdma)
  1737. {
  1738. int count = dma_spec->args_count;
  1739. struct pl330_dmac *pl330 = ofdma->of_dma_data;
  1740. unsigned int chan_id;
  1741. if (!pl330)
  1742. return NULL;
  1743. if (count != 1)
  1744. return NULL;
  1745. chan_id = dma_spec->args[0];
  1746. if (chan_id >= pl330->num_peripherals)
  1747. return NULL;
  1748. return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
  1749. }
  1750. static int pl330_alloc_chan_resources(struct dma_chan *chan)
  1751. {
  1752. struct dma_pl330_chan *pch = to_pchan(chan);
  1753. struct pl330_dmac *pl330 = pch->dmac;
  1754. unsigned long flags;
  1755. spin_lock_irqsave(&pl330->lock, flags);
  1756. dma_cookie_init(chan);
  1757. pch->cyclic = false;
  1758. pch->thread = pl330_request_channel(pl330);
  1759. if (!pch->thread) {
  1760. spin_unlock_irqrestore(&pl330->lock, flags);
  1761. return -ENOMEM;
  1762. }
  1763. tasklet_setup(&pch->task, pl330_tasklet);
  1764. spin_unlock_irqrestore(&pl330->lock, flags);
  1765. return 1;
  1766. }
  1767. /*
  1768. * We need the data direction between the DMAC (the dma-mapping "device") and
  1769. * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
  1770. */
  1771. static enum dma_data_direction
  1772. pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
  1773. {
  1774. switch (dir) {
  1775. case DMA_MEM_TO_DEV:
  1776. return DMA_FROM_DEVICE;
  1777. case DMA_DEV_TO_MEM:
  1778. return DMA_TO_DEVICE;
  1779. case DMA_DEV_TO_DEV:
  1780. return DMA_BIDIRECTIONAL;
  1781. default:
  1782. return DMA_NONE;
  1783. }
  1784. }
  1785. static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
  1786. {
  1787. if (pch->dir != DMA_NONE)
  1788. dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
  1789. 1 << pch->burst_sz, pch->dir, 0);
  1790. pch->dir = DMA_NONE;
  1791. }
  1792. static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
  1793. enum dma_transfer_direction dir)
  1794. {
  1795. struct device *dev = pch->chan.device->dev;
  1796. enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
  1797. /* Already mapped for this config? */
  1798. if (pch->dir == dma_dir)
  1799. return true;
  1800. pl330_unprep_slave_fifo(pch);
  1801. pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
  1802. 1 << pch->burst_sz, dma_dir, 0);
  1803. if (dma_mapping_error(dev, pch->fifo_dma))
  1804. return false;
  1805. pch->dir = dma_dir;
  1806. return true;
  1807. }
  1808. static int fixup_burst_len(int max_burst_len, int quirks)
  1809. {
  1810. if (max_burst_len > PL330_MAX_BURST)
  1811. return PL330_MAX_BURST;
  1812. else if (max_burst_len < 1)
  1813. return 1;
  1814. else
  1815. return max_burst_len;
  1816. }
  1817. static int pl330_config_write(struct dma_chan *chan,
  1818. struct dma_slave_config *slave_config,
  1819. enum dma_transfer_direction direction)
  1820. {
  1821. struct dma_pl330_chan *pch = to_pchan(chan);
  1822. pl330_unprep_slave_fifo(pch);
  1823. if (direction == DMA_MEM_TO_DEV) {
  1824. if (slave_config->dst_addr)
  1825. pch->fifo_addr = slave_config->dst_addr;
  1826. if (slave_config->dst_addr_width)
  1827. pch->burst_sz = __ffs(slave_config->dst_addr_width);
  1828. pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
  1829. pch->dmac->quirks);
  1830. } else if (direction == DMA_DEV_TO_MEM) {
  1831. if (slave_config->src_addr)
  1832. pch->fifo_addr = slave_config->src_addr;
  1833. if (slave_config->src_addr_width)
  1834. pch->burst_sz = __ffs(slave_config->src_addr_width);
  1835. pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
  1836. pch->dmac->quirks);
  1837. }
  1838. return 0;
  1839. }
  1840. static int pl330_config(struct dma_chan *chan,
  1841. struct dma_slave_config *slave_config)
  1842. {
  1843. struct dma_pl330_chan *pch = to_pchan(chan);
  1844. memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
  1845. return 0;
  1846. }
  1847. static int pl330_terminate_all(struct dma_chan *chan)
  1848. {
  1849. struct dma_pl330_chan *pch = to_pchan(chan);
  1850. struct dma_pl330_desc *desc;
  1851. unsigned long flags;
  1852. struct pl330_dmac *pl330 = pch->dmac;
  1853. bool power_down = false;
  1854. pm_runtime_get_sync(pl330->ddma.dev);
  1855. spin_lock_irqsave(&pch->lock, flags);
  1856. spin_lock(&pl330->lock);
  1857. _stop(pch->thread);
  1858. pch->thread->req[0].desc = NULL;
  1859. pch->thread->req[1].desc = NULL;
  1860. pch->thread->req_running = -1;
  1861. spin_unlock(&pl330->lock);
  1862. power_down = pch->active;
  1863. pch->active = false;
  1864. /* Mark all desc done */
  1865. list_for_each_entry(desc, &pch->submitted_list, node) {
  1866. desc->status = FREE;
  1867. dma_cookie_complete(&desc->txd);
  1868. }
  1869. list_for_each_entry(desc, &pch->work_list , node) {
  1870. desc->status = FREE;
  1871. dma_cookie_complete(&desc->txd);
  1872. }
  1873. list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
  1874. list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
  1875. list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
  1876. spin_unlock_irqrestore(&pch->lock, flags);
  1877. pm_runtime_mark_last_busy(pl330->ddma.dev);
  1878. if (power_down)
  1879. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1880. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1881. return 0;
  1882. }
  1883. /*
  1884. * We don't support DMA_RESUME command because of hardware
  1885. * limitations, so after pausing the channel we cannot restore
  1886. * it to active state. We have to terminate channel and setup
  1887. * DMA transfer again. This pause feature was implemented to
  1888. * allow safely read residue before channel termination.
  1889. */
  1890. static int pl330_pause(struct dma_chan *chan)
  1891. {
  1892. struct dma_pl330_chan *pch = to_pchan(chan);
  1893. struct pl330_dmac *pl330 = pch->dmac;
  1894. unsigned long flags;
  1895. pm_runtime_get_sync(pl330->ddma.dev);
  1896. spin_lock_irqsave(&pch->lock, flags);
  1897. spin_lock(&pl330->lock);
  1898. _stop(pch->thread);
  1899. spin_unlock(&pl330->lock);
  1900. spin_unlock_irqrestore(&pch->lock, flags);
  1901. pm_runtime_mark_last_busy(pl330->ddma.dev);
  1902. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1903. return 0;
  1904. }
  1905. static void pl330_free_chan_resources(struct dma_chan *chan)
  1906. {
  1907. struct dma_pl330_chan *pch = to_pchan(chan);
  1908. struct pl330_dmac *pl330 = pch->dmac;
  1909. unsigned long flags;
  1910. tasklet_kill(&pch->task);
  1911. pm_runtime_get_sync(pch->dmac->ddma.dev);
  1912. spin_lock_irqsave(&pl330->lock, flags);
  1913. pl330_release_channel(pch->thread);
  1914. pch->thread = NULL;
  1915. if (pch->cyclic)
  1916. list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
  1917. spin_unlock_irqrestore(&pl330->lock, flags);
  1918. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1919. pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
  1920. pl330_unprep_slave_fifo(pch);
  1921. }
  1922. static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
  1923. struct dma_pl330_desc *desc)
  1924. {
  1925. struct pl330_thread *thrd = pch->thread;
  1926. struct pl330_dmac *pl330 = pch->dmac;
  1927. void __iomem *regs = thrd->dmac->base;
  1928. u32 val, addr;
  1929. pm_runtime_get_sync(pl330->ddma.dev);
  1930. val = addr = 0;
  1931. if (desc->rqcfg.src_inc) {
  1932. val = readl(regs + SA(thrd->id));
  1933. addr = desc->px.src_addr;
  1934. } else {
  1935. val = readl(regs + DA(thrd->id));
  1936. addr = desc->px.dst_addr;
  1937. }
  1938. pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
  1939. pm_runtime_put_autosuspend(pl330->ddma.dev);
  1940. /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
  1941. if (!val)
  1942. return 0;
  1943. return val - addr;
  1944. }
  1945. static enum dma_status
  1946. pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  1947. struct dma_tx_state *txstate)
  1948. {
  1949. enum dma_status ret;
  1950. unsigned long flags;
  1951. struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
  1952. struct dma_pl330_chan *pch = to_pchan(chan);
  1953. unsigned int transferred, residual = 0;
  1954. ret = dma_cookie_status(chan, cookie, txstate);
  1955. if (!txstate)
  1956. return ret;
  1957. if (ret == DMA_COMPLETE)
  1958. goto out;
  1959. spin_lock_irqsave(&pch->lock, flags);
  1960. spin_lock(&pch->thread->dmac->lock);
  1961. if (pch->thread->req_running != -1)
  1962. running = pch->thread->req[pch->thread->req_running].desc;
  1963. last_enq = pch->thread->req[pch->thread->lstenq].desc;
  1964. /* Check in pending list */
  1965. list_for_each_entry(desc, &pch->work_list, node) {
  1966. if (desc->status == DONE)
  1967. transferred = desc->bytes_requested;
  1968. else if (running && desc == running)
  1969. transferred =
  1970. pl330_get_current_xferred_count(pch, desc);
  1971. else if (desc->status == BUSY)
  1972. /*
  1973. * Busy but not running means either just enqueued,
  1974. * or finished and not yet marked done
  1975. */
  1976. if (desc == last_enq)
  1977. transferred = 0;
  1978. else
  1979. transferred = desc->bytes_requested;
  1980. else
  1981. transferred = 0;
  1982. residual += desc->bytes_requested - transferred;
  1983. if (desc->txd.cookie == cookie) {
  1984. switch (desc->status) {
  1985. case DONE:
  1986. ret = DMA_COMPLETE;
  1987. break;
  1988. case PREP:
  1989. case BUSY:
  1990. ret = DMA_IN_PROGRESS;
  1991. break;
  1992. default:
  1993. WARN_ON(1);
  1994. }
  1995. break;
  1996. }
  1997. if (desc->last)
  1998. residual = 0;
  1999. }
  2000. spin_unlock(&pch->thread->dmac->lock);
  2001. spin_unlock_irqrestore(&pch->lock, flags);
  2002. out:
  2003. dma_set_residue(txstate, residual);
  2004. return ret;
  2005. }
  2006. static void pl330_issue_pending(struct dma_chan *chan)
  2007. {
  2008. struct dma_pl330_chan *pch = to_pchan(chan);
  2009. unsigned long flags;
  2010. spin_lock_irqsave(&pch->lock, flags);
  2011. if (list_empty(&pch->work_list)) {
  2012. /*
  2013. * Warn on nothing pending. Empty submitted_list may
  2014. * break our pm_runtime usage counter as it is
  2015. * updated on work_list emptiness status.
  2016. */
  2017. WARN_ON(list_empty(&pch->submitted_list));
  2018. pch->active = true;
  2019. pm_runtime_get_sync(pch->dmac->ddma.dev);
  2020. }
  2021. list_splice_tail_init(&pch->submitted_list, &pch->work_list);
  2022. spin_unlock_irqrestore(&pch->lock, flags);
  2023. pl330_tasklet(&pch->task);
  2024. }
  2025. /*
  2026. * We returned the last one of the circular list of descriptor(s)
  2027. * from prep_xxx, so the argument to submit corresponds to the last
  2028. * descriptor of the list.
  2029. */
  2030. static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
  2031. {
  2032. struct dma_pl330_desc *desc, *last = to_desc(tx);
  2033. struct dma_pl330_chan *pch = to_pchan(tx->chan);
  2034. dma_cookie_t cookie;
  2035. unsigned long flags;
  2036. spin_lock_irqsave(&pch->lock, flags);
  2037. /* Assign cookies to all nodes */
  2038. while (!list_empty(&last->node)) {
  2039. desc = list_entry(last->node.next, struct dma_pl330_desc, node);
  2040. if (pch->cyclic) {
  2041. desc->txd.callback = last->txd.callback;
  2042. desc->txd.callback_param = last->txd.callback_param;
  2043. }
  2044. desc->last = false;
  2045. dma_cookie_assign(&desc->txd);
  2046. list_move_tail(&desc->node, &pch->submitted_list);
  2047. }
  2048. last->last = true;
  2049. cookie = dma_cookie_assign(&last->txd);
  2050. list_add_tail(&last->node, &pch->submitted_list);
  2051. spin_unlock_irqrestore(&pch->lock, flags);
  2052. return cookie;
  2053. }
  2054. static inline void _init_desc(struct dma_pl330_desc *desc)
  2055. {
  2056. desc->rqcfg.swap = SWAP_NO;
  2057. desc->rqcfg.scctl = CCTRL0;
  2058. desc->rqcfg.dcctl = CCTRL0;
  2059. desc->txd.tx_submit = pl330_tx_submit;
  2060. INIT_LIST_HEAD(&desc->node);
  2061. }
  2062. /* Returns the number of descriptors added to the DMAC pool */
  2063. static int add_desc(struct list_head *pool, spinlock_t *lock,
  2064. gfp_t flg, int count)
  2065. {
  2066. struct dma_pl330_desc *desc;
  2067. unsigned long flags;
  2068. int i;
  2069. desc = kcalloc(count, sizeof(*desc), flg);
  2070. if (!desc)
  2071. return 0;
  2072. spin_lock_irqsave(lock, flags);
  2073. for (i = 0; i < count; i++) {
  2074. _init_desc(&desc[i]);
  2075. list_add_tail(&desc[i].node, pool);
  2076. }
  2077. spin_unlock_irqrestore(lock, flags);
  2078. return count;
  2079. }
  2080. static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
  2081. spinlock_t *lock)
  2082. {
  2083. struct dma_pl330_desc *desc = NULL;
  2084. unsigned long flags;
  2085. spin_lock_irqsave(lock, flags);
  2086. if (!list_empty(pool)) {
  2087. desc = list_entry(pool->next,
  2088. struct dma_pl330_desc, node);
  2089. list_del_init(&desc->node);
  2090. desc->status = PREP;
  2091. desc->txd.callback = NULL;
  2092. }
  2093. spin_unlock_irqrestore(lock, flags);
  2094. return desc;
  2095. }
  2096. static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
  2097. {
  2098. struct pl330_dmac *pl330 = pch->dmac;
  2099. u8 *peri_id = pch->chan.private;
  2100. struct dma_pl330_desc *desc;
  2101. /* Pluck one desc from the pool of DMAC */
  2102. desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
  2103. /* If the DMAC pool is empty, alloc new */
  2104. if (!desc) {
  2105. DEFINE_SPINLOCK(lock);
  2106. LIST_HEAD(pool);
  2107. if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
  2108. return NULL;
  2109. desc = pluck_desc(&pool, &lock);
  2110. WARN_ON(!desc || !list_empty(&pool));
  2111. }
  2112. /* Initialize the descriptor */
  2113. desc->pchan = pch;
  2114. desc->txd.cookie = 0;
  2115. async_tx_ack(&desc->txd);
  2116. desc->peri = peri_id ? pch->chan.chan_id : 0;
  2117. desc->rqcfg.pcfg = &pch->dmac->pcfg;
  2118. dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
  2119. return desc;
  2120. }
  2121. static inline void fill_px(struct pl330_xfer *px,
  2122. dma_addr_t dst, dma_addr_t src, size_t len)
  2123. {
  2124. px->bytes = len;
  2125. px->dst_addr = dst;
  2126. px->src_addr = src;
  2127. }
  2128. static struct dma_pl330_desc *
  2129. __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
  2130. dma_addr_t src, size_t len)
  2131. {
  2132. struct dma_pl330_desc *desc = pl330_get_desc(pch);
  2133. if (!desc) {
  2134. dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
  2135. __func__, __LINE__);
  2136. return NULL;
  2137. }
  2138. /*
  2139. * Ideally we should lookout for reqs bigger than
  2140. * those that can be programmed with 256 bytes of
  2141. * MC buffer, but considering a req size is seldom
  2142. * going to be word-unaligned and more than 200MB,
  2143. * we take it easy.
  2144. * Also, should the limit is reached we'd rather
  2145. * have the platform increase MC buffer size than
  2146. * complicating this API driver.
  2147. */
  2148. fill_px(&desc->px, dst, src, len);
  2149. return desc;
  2150. }
  2151. /* Call after fixing burst size */
  2152. static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
  2153. {
  2154. struct dma_pl330_chan *pch = desc->pchan;
  2155. struct pl330_dmac *pl330 = pch->dmac;
  2156. int burst_len;
  2157. burst_len = pl330->pcfg.data_bus_width / 8;
  2158. burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
  2159. burst_len >>= desc->rqcfg.brst_size;
  2160. /* src/dst_burst_len can't be more than 16 */
  2161. if (burst_len > PL330_MAX_BURST)
  2162. burst_len = PL330_MAX_BURST;
  2163. return burst_len;
  2164. }
  2165. static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
  2166. struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
  2167. size_t period_len, enum dma_transfer_direction direction,
  2168. unsigned long flags)
  2169. {
  2170. struct dma_pl330_desc *desc = NULL, *first = NULL;
  2171. struct dma_pl330_chan *pch = to_pchan(chan);
  2172. struct pl330_dmac *pl330 = pch->dmac;
  2173. unsigned int i;
  2174. dma_addr_t dst;
  2175. dma_addr_t src;
  2176. if (len % period_len != 0)
  2177. return NULL;
  2178. if (!is_slave_direction(direction)) {
  2179. dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
  2180. __func__, __LINE__);
  2181. return NULL;
  2182. }
  2183. pl330_config_write(chan, &pch->slave_config, direction);
  2184. if (!pl330_prep_slave_fifo(pch, direction))
  2185. return NULL;
  2186. for (i = 0; i < len / period_len; i++) {
  2187. desc = pl330_get_desc(pch);
  2188. if (!desc) {
  2189. unsigned long iflags;
  2190. dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
  2191. __func__, __LINE__);
  2192. if (!first)
  2193. return NULL;
  2194. spin_lock_irqsave(&pl330->pool_lock, iflags);
  2195. while (!list_empty(&first->node)) {
  2196. desc = list_entry(first->node.next,
  2197. struct dma_pl330_desc, node);
  2198. list_move_tail(&desc->node, &pl330->desc_pool);
  2199. }
  2200. list_move_tail(&first->node, &pl330->desc_pool);
  2201. spin_unlock_irqrestore(&pl330->pool_lock, iflags);
  2202. return NULL;
  2203. }
  2204. switch (direction) {
  2205. case DMA_MEM_TO_DEV:
  2206. desc->rqcfg.src_inc = 1;
  2207. desc->rqcfg.dst_inc = 0;
  2208. src = dma_addr;
  2209. dst = pch->fifo_dma;
  2210. break;
  2211. case DMA_DEV_TO_MEM:
  2212. desc->rqcfg.src_inc = 0;
  2213. desc->rqcfg.dst_inc = 1;
  2214. src = pch->fifo_dma;
  2215. dst = dma_addr;
  2216. break;
  2217. default:
  2218. break;
  2219. }
  2220. desc->rqtype = direction;
  2221. desc->rqcfg.brst_size = pch->burst_sz;
  2222. desc->rqcfg.brst_len = pch->burst_len;
  2223. desc->bytes_requested = period_len;
  2224. fill_px(&desc->px, dst, src, period_len);
  2225. if (!first)
  2226. first = desc;
  2227. else
  2228. list_add_tail(&desc->node, &first->node);
  2229. dma_addr += period_len;
  2230. }
  2231. if (!desc)
  2232. return NULL;
  2233. pch->cyclic = true;
  2234. desc->txd.flags = flags;
  2235. return &desc->txd;
  2236. }
  2237. static struct dma_async_tx_descriptor *
  2238. pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
  2239. dma_addr_t src, size_t len, unsigned long flags)
  2240. {
  2241. struct dma_pl330_desc *desc;
  2242. struct dma_pl330_chan *pch = to_pchan(chan);
  2243. struct pl330_dmac *pl330;
  2244. int burst;
  2245. if (unlikely(!pch || !len))
  2246. return NULL;
  2247. pl330 = pch->dmac;
  2248. desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
  2249. if (!desc)
  2250. return NULL;
  2251. desc->rqcfg.src_inc = 1;
  2252. desc->rqcfg.dst_inc = 1;
  2253. desc->rqtype = DMA_MEM_TO_MEM;
  2254. /* Select max possible burst size */
  2255. burst = pl330->pcfg.data_bus_width / 8;
  2256. /*
  2257. * Make sure we use a burst size that aligns with all the memcpy
  2258. * parameters because our DMA programming algorithm doesn't cope with
  2259. * transfers which straddle an entry in the DMA device's MFIFO.
  2260. */
  2261. while ((src | dst | len) & (burst - 1))
  2262. burst /= 2;
  2263. desc->rqcfg.brst_size = 0;
  2264. while (burst != (1 << desc->rqcfg.brst_size))
  2265. desc->rqcfg.brst_size++;
  2266. desc->rqcfg.brst_len = get_burst_len(desc, len);
  2267. /*
  2268. * If burst size is smaller than bus width then make sure we only
  2269. * transfer one at a time to avoid a burst stradling an MFIFO entry.
  2270. */
  2271. if (burst * 8 < pl330->pcfg.data_bus_width)
  2272. desc->rqcfg.brst_len = 1;
  2273. desc->bytes_requested = len;
  2274. desc->txd.flags = flags;
  2275. return &desc->txd;
  2276. }
  2277. static void __pl330_giveback_desc(struct pl330_dmac *pl330,
  2278. struct dma_pl330_desc *first)
  2279. {
  2280. unsigned long flags;
  2281. struct dma_pl330_desc *desc;
  2282. if (!first)
  2283. return;
  2284. spin_lock_irqsave(&pl330->pool_lock, flags);
  2285. while (!list_empty(&first->node)) {
  2286. desc = list_entry(first->node.next,
  2287. struct dma_pl330_desc, node);
  2288. list_move_tail(&desc->node, &pl330->desc_pool);
  2289. }
  2290. list_move_tail(&first->node, &pl330->desc_pool);
  2291. spin_unlock_irqrestore(&pl330->pool_lock, flags);
  2292. }
  2293. static struct dma_async_tx_descriptor *
  2294. pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  2295. unsigned int sg_len, enum dma_transfer_direction direction,
  2296. unsigned long flg, void *context)
  2297. {
  2298. struct dma_pl330_desc *first, *desc = NULL;
  2299. struct dma_pl330_chan *pch = to_pchan(chan);
  2300. struct scatterlist *sg;
  2301. int i;
  2302. if (unlikely(!pch || !sgl || !sg_len))
  2303. return NULL;
  2304. pl330_config_write(chan, &pch->slave_config, direction);
  2305. if (!pl330_prep_slave_fifo(pch, direction))
  2306. return NULL;
  2307. first = NULL;
  2308. for_each_sg(sgl, sg, sg_len, i) {
  2309. desc = pl330_get_desc(pch);
  2310. if (!desc) {
  2311. struct pl330_dmac *pl330 = pch->dmac;
  2312. dev_err(pch->dmac->ddma.dev,
  2313. "%s:%d Unable to fetch desc\n",
  2314. __func__, __LINE__);
  2315. __pl330_giveback_desc(pl330, first);
  2316. return NULL;
  2317. }
  2318. if (!first)
  2319. first = desc;
  2320. else
  2321. list_add_tail(&desc->node, &first->node);
  2322. if (direction == DMA_MEM_TO_DEV) {
  2323. desc->rqcfg.src_inc = 1;
  2324. desc->rqcfg.dst_inc = 0;
  2325. fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
  2326. sg_dma_len(sg));
  2327. } else {
  2328. desc->rqcfg.src_inc = 0;
  2329. desc->rqcfg.dst_inc = 1;
  2330. fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
  2331. sg_dma_len(sg));
  2332. }
  2333. desc->rqcfg.brst_size = pch->burst_sz;
  2334. desc->rqcfg.brst_len = pch->burst_len;
  2335. desc->rqtype = direction;
  2336. desc->bytes_requested = sg_dma_len(sg);
  2337. }
  2338. /* Return the last desc in the chain */
  2339. desc->txd.flags = flg;
  2340. return &desc->txd;
  2341. }
  2342. static irqreturn_t pl330_irq_handler(int irq, void *data)
  2343. {
  2344. if (pl330_update(data))
  2345. return IRQ_HANDLED;
  2346. else
  2347. return IRQ_NONE;
  2348. }
  2349. #define PL330_DMA_BUSWIDTHS \
  2350. BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  2351. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  2352. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  2353. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  2354. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
  2355. #ifdef CONFIG_DEBUG_FS
  2356. static int pl330_debugfs_show(struct seq_file *s, void *data)
  2357. {
  2358. struct pl330_dmac *pl330 = s->private;
  2359. int chans, pchs, ch, pr;
  2360. chans = pl330->pcfg.num_chan;
  2361. pchs = pl330->num_peripherals;
  2362. seq_puts(s, "PL330 physical channels:\n");
  2363. seq_puts(s, "THREAD:\t\tCHANNEL:\n");
  2364. seq_puts(s, "--------\t-----\n");
  2365. for (ch = 0; ch < chans; ch++) {
  2366. struct pl330_thread *thrd = &pl330->channels[ch];
  2367. int found = -1;
  2368. for (pr = 0; pr < pchs; pr++) {
  2369. struct dma_pl330_chan *pch = &pl330->peripherals[pr];
  2370. if (!pch->thread || thrd->id != pch->thread->id)
  2371. continue;
  2372. found = pr;
  2373. }
  2374. seq_printf(s, "%d\t\t", thrd->id);
  2375. if (found == -1)
  2376. seq_puts(s, "--\n");
  2377. else
  2378. seq_printf(s, "%d\n", found);
  2379. }
  2380. return 0;
  2381. }
  2382. DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
  2383. static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
  2384. {
  2385. debugfs_create_file(dev_name(pl330->ddma.dev),
  2386. S_IFREG | 0444, NULL, pl330,
  2387. &pl330_debugfs_fops);
  2388. }
  2389. #else
  2390. static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
  2391. {
  2392. }
  2393. #endif
  2394. /*
  2395. * Runtime PM callbacks are provided by amba/bus.c driver.
  2396. *
  2397. * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
  2398. * bus driver will only disable/enable the clock in runtime PM callbacks.
  2399. */
  2400. static int __maybe_unused pl330_suspend(struct device *dev)
  2401. {
  2402. struct amba_device *pcdev = to_amba_device(dev);
  2403. pm_runtime_force_suspend(dev);
  2404. amba_pclk_unprepare(pcdev);
  2405. return 0;
  2406. }
  2407. static int __maybe_unused pl330_resume(struct device *dev)
  2408. {
  2409. struct amba_device *pcdev = to_amba_device(dev);
  2410. int ret;
  2411. ret = amba_pclk_prepare(pcdev);
  2412. if (ret)
  2413. return ret;
  2414. pm_runtime_force_resume(dev);
  2415. return ret;
  2416. }
  2417. static const struct dev_pm_ops pl330_pm = {
  2418. SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
  2419. };
  2420. static int
  2421. pl330_probe(struct amba_device *adev, const struct amba_id *id)
  2422. {
  2423. struct pl330_config *pcfg;
  2424. struct pl330_dmac *pl330;
  2425. struct dma_pl330_chan *pch, *_p;
  2426. struct dma_device *pd;
  2427. struct resource *res;
  2428. int i, ret, irq;
  2429. int num_chan;
  2430. struct device_node *np = adev->dev.of_node;
  2431. ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
  2432. if (ret)
  2433. return ret;
  2434. /* Allocate a new DMAC and its Channels */
  2435. pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
  2436. if (!pl330)
  2437. return -ENOMEM;
  2438. pd = &pl330->ddma;
  2439. pd->dev = &adev->dev;
  2440. pl330->mcbufsz = 0;
  2441. /* get quirk */
  2442. for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
  2443. if (of_property_read_bool(np, of_quirks[i].quirk))
  2444. pl330->quirks |= of_quirks[i].id;
  2445. res = &adev->res;
  2446. pl330->base = devm_ioremap_resource(&adev->dev, res);
  2447. if (IS_ERR(pl330->base))
  2448. return PTR_ERR(pl330->base);
  2449. amba_set_drvdata(adev, pl330);
  2450. pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
  2451. if (IS_ERR(pl330->rstc)) {
  2452. return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
  2453. } else {
  2454. ret = reset_control_deassert(pl330->rstc);
  2455. if (ret) {
  2456. dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
  2457. return ret;
  2458. }
  2459. }
  2460. pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
  2461. if (IS_ERR(pl330->rstc_ocp)) {
  2462. return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
  2463. "Failed to get OCP reset!\n");
  2464. } else {
  2465. ret = reset_control_deassert(pl330->rstc_ocp);
  2466. if (ret) {
  2467. dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
  2468. return ret;
  2469. }
  2470. }
  2471. for (i = 0; i < AMBA_NR_IRQS; i++) {
  2472. irq = adev->irq[i];
  2473. if (irq) {
  2474. ret = devm_request_irq(&adev->dev, irq,
  2475. pl330_irq_handler, 0,
  2476. dev_name(&adev->dev), pl330);
  2477. if (ret)
  2478. return ret;
  2479. } else {
  2480. break;
  2481. }
  2482. }
  2483. pcfg = &pl330->pcfg;
  2484. pcfg->periph_id = adev->periphid;
  2485. ret = pl330_add(pl330);
  2486. if (ret)
  2487. return ret;
  2488. INIT_LIST_HEAD(&pl330->desc_pool);
  2489. spin_lock_init(&pl330->pool_lock);
  2490. /* Create a descriptor pool of default size */
  2491. if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
  2492. GFP_KERNEL, NR_DEFAULT_DESC))
  2493. dev_warn(&adev->dev, "unable to allocate desc\n");
  2494. INIT_LIST_HEAD(&pd->channels);
  2495. /* Initialize channel parameters */
  2496. num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
  2497. pl330->num_peripherals = num_chan;
  2498. pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
  2499. if (!pl330->peripherals) {
  2500. ret = -ENOMEM;
  2501. goto probe_err2;
  2502. }
  2503. for (i = 0; i < num_chan; i++) {
  2504. pch = &pl330->peripherals[i];
  2505. pch->chan.private = adev->dev.of_node;
  2506. INIT_LIST_HEAD(&pch->submitted_list);
  2507. INIT_LIST_HEAD(&pch->work_list);
  2508. INIT_LIST_HEAD(&pch->completed_list);
  2509. spin_lock_init(&pch->lock);
  2510. pch->thread = NULL;
  2511. pch->chan.device = pd;
  2512. pch->dmac = pl330;
  2513. pch->dir = DMA_NONE;
  2514. /* Add the channel to the DMAC list */
  2515. list_add_tail(&pch->chan.device_node, &pd->channels);
  2516. }
  2517. dma_cap_set(DMA_MEMCPY, pd->cap_mask);
  2518. if (pcfg->num_peri) {
  2519. dma_cap_set(DMA_SLAVE, pd->cap_mask);
  2520. dma_cap_set(DMA_CYCLIC, pd->cap_mask);
  2521. dma_cap_set(DMA_PRIVATE, pd->cap_mask);
  2522. }
  2523. pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
  2524. pd->device_free_chan_resources = pl330_free_chan_resources;
  2525. pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
  2526. pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
  2527. pd->device_tx_status = pl330_tx_status;
  2528. pd->device_prep_slave_sg = pl330_prep_slave_sg;
  2529. pd->device_config = pl330_config;
  2530. pd->device_pause = pl330_pause;
  2531. pd->device_terminate_all = pl330_terminate_all;
  2532. pd->device_issue_pending = pl330_issue_pending;
  2533. pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
  2534. pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
  2535. pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  2536. pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  2537. pd->max_burst = PL330_MAX_BURST;
  2538. ret = dma_async_device_register(pd);
  2539. if (ret) {
  2540. dev_err(&adev->dev, "unable to register DMAC\n");
  2541. goto probe_err3;
  2542. }
  2543. if (adev->dev.of_node) {
  2544. ret = of_dma_controller_register(adev->dev.of_node,
  2545. of_dma_pl330_xlate, pl330);
  2546. if (ret) {
  2547. dev_err(&adev->dev,
  2548. "unable to register DMA to the generic DT DMA helpers\n");
  2549. }
  2550. }
  2551. /*
  2552. * This is the limit for transfers with a buswidth of 1, larger
  2553. * buswidths will have larger limits.
  2554. */
  2555. ret = dma_set_max_seg_size(&adev->dev, 1900800);
  2556. if (ret)
  2557. dev_err(&adev->dev, "unable to set the seg size\n");
  2558. init_pl330_debugfs(pl330);
  2559. dev_info(&adev->dev,
  2560. "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
  2561. dev_info(&adev->dev,
  2562. "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
  2563. pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
  2564. pcfg->num_peri, pcfg->num_events);
  2565. pm_runtime_irq_safe(&adev->dev);
  2566. pm_runtime_use_autosuspend(&adev->dev);
  2567. pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
  2568. pm_runtime_mark_last_busy(&adev->dev);
  2569. pm_runtime_put_autosuspend(&adev->dev);
  2570. return 0;
  2571. probe_err3:
  2572. /* Idle the DMAC */
  2573. list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
  2574. chan.device_node) {
  2575. /* Remove the channel */
  2576. list_del(&pch->chan.device_node);
  2577. /* Flush the channel */
  2578. if (pch->thread) {
  2579. pl330_terminate_all(&pch->chan);
  2580. pl330_free_chan_resources(&pch->chan);
  2581. }
  2582. }
  2583. probe_err2:
  2584. pl330_del(pl330);
  2585. if (pl330->rstc_ocp)
  2586. reset_control_assert(pl330->rstc_ocp);
  2587. if (pl330->rstc)
  2588. reset_control_assert(pl330->rstc);
  2589. return ret;
  2590. }
  2591. static void pl330_remove(struct amba_device *adev)
  2592. {
  2593. struct pl330_dmac *pl330 = amba_get_drvdata(adev);
  2594. struct dma_pl330_chan *pch, *_p;
  2595. int i, irq;
  2596. pm_runtime_get_noresume(pl330->ddma.dev);
  2597. if (adev->dev.of_node)
  2598. of_dma_controller_free(adev->dev.of_node);
  2599. for (i = 0; i < AMBA_NR_IRQS; i++) {
  2600. irq = adev->irq[i];
  2601. if (irq)
  2602. devm_free_irq(&adev->dev, irq, pl330);
  2603. }
  2604. dma_async_device_unregister(&pl330->ddma);
  2605. /* Idle the DMAC */
  2606. list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
  2607. chan.device_node) {
  2608. /* Remove the channel */
  2609. list_del(&pch->chan.device_node);
  2610. /* Flush the channel */
  2611. if (pch->thread) {
  2612. pl330_terminate_all(&pch->chan);
  2613. pl330_free_chan_resources(&pch->chan);
  2614. }
  2615. }
  2616. pl330_del(pl330);
  2617. if (pl330->rstc_ocp)
  2618. reset_control_assert(pl330->rstc_ocp);
  2619. if (pl330->rstc)
  2620. reset_control_assert(pl330->rstc);
  2621. }
  2622. static const struct amba_id pl330_ids[] = {
  2623. {
  2624. .id = 0x00041330,
  2625. .mask = 0x000fffff,
  2626. },
  2627. { 0, 0 },
  2628. };
  2629. MODULE_DEVICE_TABLE(amba, pl330_ids);
  2630. static struct amba_driver pl330_driver = {
  2631. .drv = {
  2632. .owner = THIS_MODULE,
  2633. .name = "dma-pl330",
  2634. .pm = &pl330_pm,
  2635. },
  2636. .id_table = pl330_ids,
  2637. .probe = pl330_probe,
  2638. .remove = pl330_remove,
  2639. };
  2640. module_amba_driver(pl330_driver);
  2641. MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
  2642. MODULE_DESCRIPTION("API Driver for PL330 DMAC");
  2643. MODULE_LICENSE("GPL");