nbpfaxi.c 40 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
  4. * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. */
  6. #include <linux/bitmap.h>
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/log2.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_dma.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/slab.h>
  21. #include <dt-bindings/dma/nbpfaxi.h>
  22. #include "dmaengine.h"
  23. #define NBPF_REG_CHAN_OFFSET 0
  24. #define NBPF_REG_CHAN_SIZE 0x40
  25. /* Channel Current Transaction Byte register */
  26. #define NBPF_CHAN_CUR_TR_BYTE 0x20
  27. /* Channel Status register */
  28. #define NBPF_CHAN_STAT 0x24
  29. #define NBPF_CHAN_STAT_EN 1
  30. #define NBPF_CHAN_STAT_TACT 4
  31. #define NBPF_CHAN_STAT_ERR 0x10
  32. #define NBPF_CHAN_STAT_END 0x20
  33. #define NBPF_CHAN_STAT_TC 0x40
  34. #define NBPF_CHAN_STAT_DER 0x400
  35. /* Channel Control register */
  36. #define NBPF_CHAN_CTRL 0x28
  37. #define NBPF_CHAN_CTRL_SETEN 1
  38. #define NBPF_CHAN_CTRL_CLREN 2
  39. #define NBPF_CHAN_CTRL_STG 4
  40. #define NBPF_CHAN_CTRL_SWRST 8
  41. #define NBPF_CHAN_CTRL_CLRRQ 0x10
  42. #define NBPF_CHAN_CTRL_CLREND 0x20
  43. #define NBPF_CHAN_CTRL_CLRTC 0x40
  44. #define NBPF_CHAN_CTRL_SETSUS 0x100
  45. #define NBPF_CHAN_CTRL_CLRSUS 0x200
  46. /* Channel Configuration register */
  47. #define NBPF_CHAN_CFG 0x2c
  48. #define NBPF_CHAN_CFG_SEL 7 /* terminal SELect: 0..7 */
  49. #define NBPF_CHAN_CFG_REQD 8 /* REQuest Direction: DMAREQ is 0: input, 1: output */
  50. #define NBPF_CHAN_CFG_LOEN 0x10 /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
  51. #define NBPF_CHAN_CFG_HIEN 0x20 /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
  52. #define NBPF_CHAN_CFG_LVL 0x40 /* LeVeL: DMA request line is sensed as 0: edge, 1: level */
  53. #define NBPF_CHAN_CFG_AM 0x700 /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */
  54. #define NBPF_CHAN_CFG_SDS 0xf000 /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
  55. #define NBPF_CHAN_CFG_DDS 0xf0000 /* Destination Data Size: as above */
  56. #define NBPF_CHAN_CFG_SAD 0x100000 /* Source ADdress counting: 0: increment, 1: fixed */
  57. #define NBPF_CHAN_CFG_DAD 0x200000 /* Destination ADdress counting: 0: increment, 1: fixed */
  58. #define NBPF_CHAN_CFG_TM 0x400000 /* Transfer Mode: 0: single, 1: block TM */
  59. #define NBPF_CHAN_CFG_DEM 0x1000000 /* DMAEND interrupt Mask */
  60. #define NBPF_CHAN_CFG_TCM 0x2000000 /* DMATCO interrupt Mask */
  61. #define NBPF_CHAN_CFG_SBE 0x8000000 /* Sweep Buffer Enable */
  62. #define NBPF_CHAN_CFG_RSEL 0x10000000 /* RM: Register Set sELect */
  63. #define NBPF_CHAN_CFG_RSW 0x20000000 /* RM: Register Select sWitch */
  64. #define NBPF_CHAN_CFG_REN 0x40000000 /* RM: Register Set Enable */
  65. #define NBPF_CHAN_CFG_DMS 0x80000000 /* 0: register mode (RM), 1: link mode (LM) */
  66. #define NBPF_CHAN_NXLA 0x38
  67. #define NBPF_CHAN_CRLA 0x3c
  68. /* Link Header field */
  69. #define NBPF_HEADER_LV 1
  70. #define NBPF_HEADER_LE 2
  71. #define NBPF_HEADER_WBD 4
  72. #define NBPF_HEADER_DIM 8
  73. #define NBPF_CTRL 0x300
  74. #define NBPF_CTRL_PR 1 /* 0: fixed priority, 1: round robin */
  75. #define NBPF_CTRL_LVINT 2 /* DMAEND and DMAERR signalling: 0: pulse, 1: level */
  76. #define NBPF_DSTAT_ER 0x314
  77. #define NBPF_DSTAT_END 0x318
  78. #define NBPF_DMA_BUSWIDTHS \
  79. (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  80. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  81. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  82. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  83. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  84. struct nbpf_config {
  85. int num_channels;
  86. int buffer_size;
  87. };
  88. /*
  89. * We've got 3 types of objects, used to describe DMA transfers:
  90. * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
  91. * in it, used to communicate with the user
  92. * 2. hardware DMA link descriptors, that we pass to DMAC for DMA transfer
  93. * queuing, these must be DMAable, using either the streaming DMA API or
  94. * allocated from coherent memory - one per SG segment
  95. * 3. one per SG segment descriptors, used to manage HW link descriptors from
  96. * (2). They do not have to be DMAable. They can either be (a) allocated
  97. * together with link descriptors as mixed (DMA / CPU) objects, or (b)
  98. * separately. Even if allocated separately it would be best to link them
  99. * to link descriptors once during channel resource allocation and always
  100. * use them as a single object.
  101. * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
  102. * treated as a single SG segment descriptor.
  103. */
  104. struct nbpf_link_reg {
  105. u32 header;
  106. u32 src_addr;
  107. u32 dst_addr;
  108. u32 transaction_size;
  109. u32 config;
  110. u32 interval;
  111. u32 extension;
  112. u32 next;
  113. } __packed;
  114. struct nbpf_device;
  115. struct nbpf_channel;
  116. struct nbpf_desc;
  117. struct nbpf_link_desc {
  118. struct nbpf_link_reg *hwdesc;
  119. dma_addr_t hwdesc_dma_addr;
  120. struct nbpf_desc *desc;
  121. struct list_head node;
  122. };
  123. /**
  124. * struct nbpf_desc - DMA transfer descriptor
  125. * @async_tx: dmaengine object
  126. * @user_wait: waiting for a user ack
  127. * @length: total transfer length
  128. * @chan: associated DMAC channel
  129. * @sg: list of hardware descriptors, represented by struct nbpf_link_desc
  130. * @node: member in channel descriptor lists
  131. */
  132. struct nbpf_desc {
  133. struct dma_async_tx_descriptor async_tx;
  134. bool user_wait;
  135. size_t length;
  136. struct nbpf_channel *chan;
  137. struct list_head sg;
  138. struct list_head node;
  139. };
  140. /* Take a wild guess: allocate 4 segments per descriptor */
  141. #define NBPF_SEGMENTS_PER_DESC 4
  142. #define NBPF_DESCS_PER_PAGE ((PAGE_SIZE - sizeof(struct list_head)) / \
  143. (sizeof(struct nbpf_desc) + \
  144. NBPF_SEGMENTS_PER_DESC * \
  145. (sizeof(struct nbpf_link_desc) + sizeof(struct nbpf_link_reg))))
  146. #define NBPF_SEGMENTS_PER_PAGE (NBPF_SEGMENTS_PER_DESC * NBPF_DESCS_PER_PAGE)
  147. struct nbpf_desc_page {
  148. struct list_head node;
  149. struct nbpf_desc desc[NBPF_DESCS_PER_PAGE];
  150. struct nbpf_link_desc ldesc[NBPF_SEGMENTS_PER_PAGE];
  151. struct nbpf_link_reg hwdesc[NBPF_SEGMENTS_PER_PAGE];
  152. };
  153. /**
  154. * struct nbpf_channel - one DMAC channel
  155. * @dma_chan: standard dmaengine channel object
  156. * @tasklet: channel specific tasklet used for callbacks
  157. * @base: register address base
  158. * @nbpf: DMAC
  159. * @name: IRQ name
  160. * @irq: IRQ number
  161. * @slave_src_addr: source address for slave DMA
  162. * @slave_src_width: source slave data size in bytes
  163. * @slave_src_burst: maximum source slave burst size in bytes
  164. * @slave_dst_addr: destination address for slave DMA
  165. * @slave_dst_width: destination slave data size in bytes
  166. * @slave_dst_burst: maximum destination slave burst size in bytes
  167. * @terminal: DMA terminal, assigned to this channel
  168. * @dmarq_cfg: DMA request line configuration - high / low, edge / level for NBPF_CHAN_CFG
  169. * @flags: configuration flags from DT
  170. * @lock: protect descriptor lists
  171. * @free_links: list of free link descriptors
  172. * @free: list of free descriptors
  173. * @queued: list of queued descriptors
  174. * @active: list of descriptors, scheduled for processing
  175. * @done: list of completed descriptors, waiting post-processing
  176. * @desc_page: list of additionally allocated descriptor pages - if any
  177. * @running: linked descriptor of running transaction
  178. * @paused: are translations on this channel paused?
  179. */
  180. struct nbpf_channel {
  181. struct dma_chan dma_chan;
  182. struct tasklet_struct tasklet;
  183. void __iomem *base;
  184. struct nbpf_device *nbpf;
  185. char name[16];
  186. int irq;
  187. dma_addr_t slave_src_addr;
  188. size_t slave_src_width;
  189. size_t slave_src_burst;
  190. dma_addr_t slave_dst_addr;
  191. size_t slave_dst_width;
  192. size_t slave_dst_burst;
  193. unsigned int terminal;
  194. u32 dmarq_cfg;
  195. unsigned long flags;
  196. spinlock_t lock;
  197. struct list_head free_links;
  198. struct list_head free;
  199. struct list_head queued;
  200. struct list_head active;
  201. struct list_head done;
  202. struct list_head desc_page;
  203. struct nbpf_desc *running;
  204. bool paused;
  205. };
  206. struct nbpf_device {
  207. struct dma_device dma_dev;
  208. void __iomem *base;
  209. u32 max_burst_mem_read;
  210. u32 max_burst_mem_write;
  211. struct clk *clk;
  212. const struct nbpf_config *config;
  213. unsigned int eirq;
  214. struct nbpf_channel chan[];
  215. };
  216. enum nbpf_model {
  217. NBPF1B4,
  218. NBPF1B8,
  219. NBPF1B16,
  220. NBPF4B4,
  221. NBPF4B8,
  222. NBPF4B16,
  223. NBPF8B4,
  224. NBPF8B8,
  225. NBPF8B16,
  226. };
  227. static struct nbpf_config nbpf_cfg[] = {
  228. [NBPF1B4] = {
  229. .num_channels = 1,
  230. .buffer_size = 4,
  231. },
  232. [NBPF1B8] = {
  233. .num_channels = 1,
  234. .buffer_size = 8,
  235. },
  236. [NBPF1B16] = {
  237. .num_channels = 1,
  238. .buffer_size = 16,
  239. },
  240. [NBPF4B4] = {
  241. .num_channels = 4,
  242. .buffer_size = 4,
  243. },
  244. [NBPF4B8] = {
  245. .num_channels = 4,
  246. .buffer_size = 8,
  247. },
  248. [NBPF4B16] = {
  249. .num_channels = 4,
  250. .buffer_size = 16,
  251. },
  252. [NBPF8B4] = {
  253. .num_channels = 8,
  254. .buffer_size = 4,
  255. },
  256. [NBPF8B8] = {
  257. .num_channels = 8,
  258. .buffer_size = 8,
  259. },
  260. [NBPF8B16] = {
  261. .num_channels = 8,
  262. .buffer_size = 16,
  263. },
  264. };
  265. #define nbpf_to_chan(d) container_of(d, struct nbpf_channel, dma_chan)
  266. /*
  267. * dmaengine drivers seem to have a lot in common and instead of sharing more
  268. * code, they reimplement those common algorithms independently. In this driver
  269. * we try to separate the hardware-specific part from the (largely) generic
  270. * part. This improves code readability and makes it possible in the future to
  271. * reuse the generic code in form of a helper library. That generic code should
  272. * be suitable for various DMA controllers, using transfer descriptors in RAM
  273. * and pushing one SG list at a time to the DMA controller.
  274. */
  275. /* Hardware-specific part */
  276. static inline u32 nbpf_chan_read(struct nbpf_channel *chan,
  277. unsigned int offset)
  278. {
  279. u32 data = ioread32(chan->base + offset);
  280. dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
  281. __func__, chan->base, offset, data);
  282. return data;
  283. }
  284. static inline void nbpf_chan_write(struct nbpf_channel *chan,
  285. unsigned int offset, u32 data)
  286. {
  287. iowrite32(data, chan->base + offset);
  288. dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
  289. __func__, chan->base, offset, data);
  290. }
  291. static inline u32 nbpf_read(struct nbpf_device *nbpf,
  292. unsigned int offset)
  293. {
  294. u32 data = ioread32(nbpf->base + offset);
  295. dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
  296. __func__, nbpf->base, offset, data);
  297. return data;
  298. }
  299. static inline void nbpf_write(struct nbpf_device *nbpf,
  300. unsigned int offset, u32 data)
  301. {
  302. iowrite32(data, nbpf->base + offset);
  303. dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
  304. __func__, nbpf->base, offset, data);
  305. }
  306. static void nbpf_chan_halt(struct nbpf_channel *chan)
  307. {
  308. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
  309. }
  310. static bool nbpf_status_get(struct nbpf_channel *chan)
  311. {
  312. u32 status = nbpf_read(chan->nbpf, NBPF_DSTAT_END);
  313. return status & BIT(chan - chan->nbpf->chan);
  314. }
  315. static void nbpf_status_ack(struct nbpf_channel *chan)
  316. {
  317. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREND);
  318. }
  319. static u32 nbpf_error_get(struct nbpf_device *nbpf)
  320. {
  321. return nbpf_read(nbpf, NBPF_DSTAT_ER);
  322. }
  323. static struct nbpf_channel *nbpf_error_get_channel(struct nbpf_device *nbpf, u32 error)
  324. {
  325. return nbpf->chan + __ffs(error);
  326. }
  327. static void nbpf_error_clear(struct nbpf_channel *chan)
  328. {
  329. u32 status;
  330. int i;
  331. /* Stop the channel, make sure DMA has been aborted */
  332. nbpf_chan_halt(chan);
  333. for (i = 1000; i; i--) {
  334. status = nbpf_chan_read(chan, NBPF_CHAN_STAT);
  335. if (!(status & NBPF_CHAN_STAT_TACT))
  336. break;
  337. cpu_relax();
  338. }
  339. if (!i)
  340. dev_err(chan->dma_chan.device->dev,
  341. "%s(): abort timeout, channel status 0x%x\n", __func__, status);
  342. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SWRST);
  343. }
  344. static int nbpf_start(struct nbpf_desc *desc)
  345. {
  346. struct nbpf_channel *chan = desc->chan;
  347. struct nbpf_link_desc *ldesc = list_first_entry(&desc->sg, struct nbpf_link_desc, node);
  348. nbpf_chan_write(chan, NBPF_CHAN_NXLA, (u32)ldesc->hwdesc_dma_addr);
  349. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETEN | NBPF_CHAN_CTRL_CLRSUS);
  350. chan->paused = false;
  351. /* Software trigger MEMCPY - only MEMCPY uses the block mode */
  352. if (ldesc->hwdesc->config & NBPF_CHAN_CFG_TM)
  353. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_STG);
  354. dev_dbg(chan->nbpf->dma_dev.dev, "%s(): next 0x%x, cur 0x%x\n", __func__,
  355. nbpf_chan_read(chan, NBPF_CHAN_NXLA), nbpf_chan_read(chan, NBPF_CHAN_CRLA));
  356. return 0;
  357. }
  358. static void nbpf_chan_prepare(struct nbpf_channel *chan)
  359. {
  360. chan->dmarq_cfg = (chan->flags & NBPF_SLAVE_RQ_HIGH ? NBPF_CHAN_CFG_HIEN : 0) |
  361. (chan->flags & NBPF_SLAVE_RQ_LOW ? NBPF_CHAN_CFG_LOEN : 0) |
  362. (chan->flags & NBPF_SLAVE_RQ_LEVEL ?
  363. NBPF_CHAN_CFG_LVL | (NBPF_CHAN_CFG_AM & 0x200) : 0) |
  364. chan->terminal;
  365. }
  366. static void nbpf_chan_prepare_default(struct nbpf_channel *chan)
  367. {
  368. /* Don't output DMAACK */
  369. chan->dmarq_cfg = NBPF_CHAN_CFG_AM & 0x400;
  370. chan->terminal = 0;
  371. chan->flags = 0;
  372. }
  373. static void nbpf_chan_configure(struct nbpf_channel *chan)
  374. {
  375. /*
  376. * We assume, that only the link mode and DMA request line configuration
  377. * have to be set in the configuration register manually. Dynamic
  378. * per-transfer configuration will be loaded from transfer descriptors.
  379. */
  380. nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
  381. }
  382. static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size,
  383. enum dma_transfer_direction direction)
  384. {
  385. int max_burst = nbpf->config->buffer_size * 8;
  386. if (nbpf->max_burst_mem_read || nbpf->max_burst_mem_write) {
  387. switch (direction) {
  388. case DMA_MEM_TO_MEM:
  389. max_burst = min_not_zero(nbpf->max_burst_mem_read,
  390. nbpf->max_burst_mem_write);
  391. break;
  392. case DMA_MEM_TO_DEV:
  393. if (nbpf->max_burst_mem_read)
  394. max_burst = nbpf->max_burst_mem_read;
  395. break;
  396. case DMA_DEV_TO_MEM:
  397. if (nbpf->max_burst_mem_write)
  398. max_burst = nbpf->max_burst_mem_write;
  399. break;
  400. case DMA_DEV_TO_DEV:
  401. default:
  402. break;
  403. }
  404. }
  405. /* Maximum supported bursts depend on the buffer size */
  406. return min_t(int, __ffs(size), ilog2(max_burst));
  407. }
  408. static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
  409. enum dma_slave_buswidth width, u32 burst)
  410. {
  411. size_t size;
  412. if (!burst)
  413. burst = 1;
  414. switch (width) {
  415. case DMA_SLAVE_BUSWIDTH_8_BYTES:
  416. size = 8 * burst;
  417. break;
  418. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  419. size = 4 * burst;
  420. break;
  421. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  422. size = 2 * burst;
  423. break;
  424. default:
  425. pr_warn("%s(): invalid bus width %u\n", __func__, width);
  426. fallthrough;
  427. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  428. size = burst;
  429. }
  430. return nbpf_xfer_ds(nbpf, size, DMA_TRANS_NONE);
  431. }
  432. /*
  433. * We need a way to recognise slaves, whose data is sent "raw" over the bus,
  434. * i.e. it isn't known in advance how many bytes will be received. Therefore
  435. * the slave driver has to provide a "large enough" buffer and either read the
  436. * buffer, when it is full, or detect, that some data has arrived, then wait for
  437. * a timeout, if no more data arrives - receive what's already there. We want to
  438. * handle such slaves in a special way to allow an optimised mode for other
  439. * users, for whom the amount of data is known in advance. So far there's no way
  440. * to recognise such slaves. We use a data-width check to distinguish between
  441. * the SD host and the PL011 UART.
  442. */
  443. static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
  444. enum dma_transfer_direction direction,
  445. dma_addr_t src, dma_addr_t dst, size_t size, bool last)
  446. {
  447. struct nbpf_link_reg *hwdesc = ldesc->hwdesc;
  448. struct nbpf_desc *desc = ldesc->desc;
  449. struct nbpf_channel *chan = desc->chan;
  450. struct device *dev = chan->dma_chan.device->dev;
  451. size_t mem_xfer, slave_xfer;
  452. bool can_burst;
  453. hwdesc->header = NBPF_HEADER_WBD | NBPF_HEADER_LV |
  454. (last ? NBPF_HEADER_LE : 0);
  455. hwdesc->src_addr = src;
  456. hwdesc->dst_addr = dst;
  457. hwdesc->transaction_size = size;
  458. /*
  459. * set config: SAD, DAD, DDS, SDS, etc.
  460. * Note on transfer sizes: the DMAC can perform unaligned DMA transfers,
  461. * but it is important to have transaction size a multiple of both
  462. * receiver and transmitter transfer sizes. It is also possible to use
  463. * different RAM and device transfer sizes, and it does work well with
  464. * some devices, e.g. with V08R07S01E SD host controllers, which can use
  465. * 128 byte transfers. But this doesn't work with other devices,
  466. * especially when the transaction size is unknown. This is the case,
  467. * e.g. with serial drivers like amba-pl011.c. For reception it sets up
  468. * the transaction size of 4K and if fewer bytes are received, it
  469. * pauses DMA and reads out data received via DMA as well as those left
  470. * in the Rx FIFO. For this to work with the RAM side using burst
  471. * transfers we enable the SBE bit and terminate the transfer in our
  472. * .device_pause handler.
  473. */
  474. mem_xfer = nbpf_xfer_ds(chan->nbpf, size, direction);
  475. switch (direction) {
  476. case DMA_DEV_TO_MEM:
  477. can_burst = chan->slave_src_width >= 3;
  478. slave_xfer = min(mem_xfer, can_burst ?
  479. chan->slave_src_burst : chan->slave_src_width);
  480. /*
  481. * Is the slave narrower than 64 bits, i.e. isn't using the full
  482. * bus width and cannot use bursts?
  483. */
  484. if (mem_xfer > chan->slave_src_burst && !can_burst)
  485. mem_xfer = chan->slave_src_burst;
  486. /* Device-to-RAM DMA is unreliable without REQD set */
  487. hwdesc->config = NBPF_CHAN_CFG_SAD | (NBPF_CHAN_CFG_DDS & (mem_xfer << 16)) |
  488. (NBPF_CHAN_CFG_SDS & (slave_xfer << 12)) | NBPF_CHAN_CFG_REQD |
  489. NBPF_CHAN_CFG_SBE;
  490. break;
  491. case DMA_MEM_TO_DEV:
  492. slave_xfer = min(mem_xfer, chan->slave_dst_width >= 3 ?
  493. chan->slave_dst_burst : chan->slave_dst_width);
  494. hwdesc->config = NBPF_CHAN_CFG_DAD | (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
  495. (NBPF_CHAN_CFG_DDS & (slave_xfer << 16)) | NBPF_CHAN_CFG_REQD;
  496. break;
  497. case DMA_MEM_TO_MEM:
  498. hwdesc->config = NBPF_CHAN_CFG_TCM | NBPF_CHAN_CFG_TM |
  499. (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
  500. (NBPF_CHAN_CFG_DDS & (mem_xfer << 16));
  501. break;
  502. default:
  503. return -EINVAL;
  504. }
  505. hwdesc->config |= chan->dmarq_cfg | (last ? 0 : NBPF_CHAN_CFG_DEM) |
  506. NBPF_CHAN_CFG_DMS;
  507. dev_dbg(dev, "%s(): desc @ %pad: hdr 0x%x, cfg 0x%x, %zu @ %pad -> %pad\n",
  508. __func__, &ldesc->hwdesc_dma_addr, hwdesc->header,
  509. hwdesc->config, size, &src, &dst);
  510. dma_sync_single_for_device(dev, ldesc->hwdesc_dma_addr, sizeof(*hwdesc),
  511. DMA_TO_DEVICE);
  512. return 0;
  513. }
  514. static size_t nbpf_bytes_left(struct nbpf_channel *chan)
  515. {
  516. return nbpf_chan_read(chan, NBPF_CHAN_CUR_TR_BYTE);
  517. }
  518. static void nbpf_configure(struct nbpf_device *nbpf)
  519. {
  520. nbpf_write(nbpf, NBPF_CTRL, NBPF_CTRL_LVINT);
  521. }
  522. /* Generic part */
  523. /* DMA ENGINE functions */
  524. static void nbpf_issue_pending(struct dma_chan *dchan)
  525. {
  526. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  527. unsigned long flags;
  528. dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
  529. spin_lock_irqsave(&chan->lock, flags);
  530. if (list_empty(&chan->queued))
  531. goto unlock;
  532. list_splice_tail_init(&chan->queued, &chan->active);
  533. if (!chan->running) {
  534. struct nbpf_desc *desc = list_first_entry(&chan->active,
  535. struct nbpf_desc, node);
  536. if (!nbpf_start(desc))
  537. chan->running = desc;
  538. }
  539. unlock:
  540. spin_unlock_irqrestore(&chan->lock, flags);
  541. }
  542. static enum dma_status nbpf_tx_status(struct dma_chan *dchan,
  543. dma_cookie_t cookie, struct dma_tx_state *state)
  544. {
  545. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  546. enum dma_status status = dma_cookie_status(dchan, cookie, state);
  547. if (state) {
  548. dma_cookie_t running;
  549. unsigned long flags;
  550. spin_lock_irqsave(&chan->lock, flags);
  551. running = chan->running ? chan->running->async_tx.cookie : -EINVAL;
  552. if (cookie == running) {
  553. state->residue = nbpf_bytes_left(chan);
  554. dev_dbg(dchan->device->dev, "%s(): residue %u\n", __func__,
  555. state->residue);
  556. } else if (status == DMA_IN_PROGRESS) {
  557. struct nbpf_desc *desc;
  558. bool found = false;
  559. list_for_each_entry(desc, &chan->active, node)
  560. if (desc->async_tx.cookie == cookie) {
  561. found = true;
  562. break;
  563. }
  564. if (!found)
  565. list_for_each_entry(desc, &chan->queued, node)
  566. if (desc->async_tx.cookie == cookie) {
  567. found = true;
  568. break;
  569. }
  570. state->residue = found ? desc->length : 0;
  571. }
  572. spin_unlock_irqrestore(&chan->lock, flags);
  573. }
  574. if (chan->paused)
  575. status = DMA_PAUSED;
  576. return status;
  577. }
  578. static dma_cookie_t nbpf_tx_submit(struct dma_async_tx_descriptor *tx)
  579. {
  580. struct nbpf_desc *desc = container_of(tx, struct nbpf_desc, async_tx);
  581. struct nbpf_channel *chan = desc->chan;
  582. unsigned long flags;
  583. dma_cookie_t cookie;
  584. spin_lock_irqsave(&chan->lock, flags);
  585. cookie = dma_cookie_assign(tx);
  586. list_add_tail(&desc->node, &chan->queued);
  587. spin_unlock_irqrestore(&chan->lock, flags);
  588. dev_dbg(chan->dma_chan.device->dev, "Entry %s(%d)\n", __func__, cookie);
  589. return cookie;
  590. }
  591. static int nbpf_desc_page_alloc(struct nbpf_channel *chan)
  592. {
  593. struct dma_chan *dchan = &chan->dma_chan;
  594. struct nbpf_desc_page *dpage = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
  595. struct nbpf_link_desc *ldesc;
  596. struct nbpf_link_reg *hwdesc;
  597. struct nbpf_desc *desc;
  598. LIST_HEAD(head);
  599. LIST_HEAD(lhead);
  600. int i;
  601. struct device *dev = dchan->device->dev;
  602. if (!dpage)
  603. return -ENOMEM;
  604. dev_dbg(dev, "%s(): alloc %lu descriptors, %lu segments, total alloc %zu\n",
  605. __func__, NBPF_DESCS_PER_PAGE, NBPF_SEGMENTS_PER_PAGE, sizeof(*dpage));
  606. for (i = 0, ldesc = dpage->ldesc, hwdesc = dpage->hwdesc;
  607. i < ARRAY_SIZE(dpage->ldesc);
  608. i++, ldesc++, hwdesc++) {
  609. ldesc->hwdesc = hwdesc;
  610. list_add_tail(&ldesc->node, &lhead);
  611. ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev,
  612. hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE);
  613. dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__,
  614. hwdesc, &ldesc->hwdesc_dma_addr);
  615. }
  616. for (i = 0, desc = dpage->desc;
  617. i < ARRAY_SIZE(dpage->desc);
  618. i++, desc++) {
  619. dma_async_tx_descriptor_init(&desc->async_tx, dchan);
  620. desc->async_tx.tx_submit = nbpf_tx_submit;
  621. desc->chan = chan;
  622. INIT_LIST_HEAD(&desc->sg);
  623. list_add_tail(&desc->node, &head);
  624. }
  625. /*
  626. * This function cannot be called from interrupt context, so, no need to
  627. * save flags
  628. */
  629. spin_lock_irq(&chan->lock);
  630. list_splice_tail(&lhead, &chan->free_links);
  631. list_splice_tail(&head, &chan->free);
  632. list_add(&dpage->node, &chan->desc_page);
  633. spin_unlock_irq(&chan->lock);
  634. return ARRAY_SIZE(dpage->desc);
  635. }
  636. static void nbpf_desc_put(struct nbpf_desc *desc)
  637. {
  638. struct nbpf_channel *chan = desc->chan;
  639. struct nbpf_link_desc *ldesc, *tmp;
  640. unsigned long flags;
  641. spin_lock_irqsave(&chan->lock, flags);
  642. list_for_each_entry_safe(ldesc, tmp, &desc->sg, node)
  643. list_move(&ldesc->node, &chan->free_links);
  644. list_add(&desc->node, &chan->free);
  645. spin_unlock_irqrestore(&chan->lock, flags);
  646. }
  647. static void nbpf_scan_acked(struct nbpf_channel *chan)
  648. {
  649. struct nbpf_desc *desc, *tmp;
  650. unsigned long flags;
  651. LIST_HEAD(head);
  652. spin_lock_irqsave(&chan->lock, flags);
  653. list_for_each_entry_safe(desc, tmp, &chan->done, node)
  654. if (async_tx_test_ack(&desc->async_tx) && desc->user_wait) {
  655. list_move(&desc->node, &head);
  656. desc->user_wait = false;
  657. }
  658. spin_unlock_irqrestore(&chan->lock, flags);
  659. list_for_each_entry_safe(desc, tmp, &head, node) {
  660. list_del(&desc->node);
  661. nbpf_desc_put(desc);
  662. }
  663. }
  664. /*
  665. * We have to allocate descriptors with the channel lock dropped. This means,
  666. * before we re-acquire the lock buffers can be taken already, so we have to
  667. * re-check after re-acquiring the lock and possibly retry, if buffers are gone
  668. * again.
  669. */
  670. static struct nbpf_desc *nbpf_desc_get(struct nbpf_channel *chan, size_t len)
  671. {
  672. struct nbpf_desc *desc = NULL;
  673. struct nbpf_link_desc *ldesc, *prev = NULL;
  674. nbpf_scan_acked(chan);
  675. spin_lock_irq(&chan->lock);
  676. do {
  677. int i = 0, ret;
  678. if (list_empty(&chan->free)) {
  679. /* No more free descriptors */
  680. spin_unlock_irq(&chan->lock);
  681. ret = nbpf_desc_page_alloc(chan);
  682. if (ret < 0)
  683. return NULL;
  684. spin_lock_irq(&chan->lock);
  685. continue;
  686. }
  687. desc = list_first_entry(&chan->free, struct nbpf_desc, node);
  688. list_del(&desc->node);
  689. do {
  690. if (list_empty(&chan->free_links)) {
  691. /* No more free link descriptors */
  692. spin_unlock_irq(&chan->lock);
  693. ret = nbpf_desc_page_alloc(chan);
  694. if (ret < 0) {
  695. nbpf_desc_put(desc);
  696. return NULL;
  697. }
  698. spin_lock_irq(&chan->lock);
  699. continue;
  700. }
  701. ldesc = list_first_entry(&chan->free_links,
  702. struct nbpf_link_desc, node);
  703. ldesc->desc = desc;
  704. if (prev)
  705. prev->hwdesc->next = (u32)ldesc->hwdesc_dma_addr;
  706. prev = ldesc;
  707. list_move_tail(&ldesc->node, &desc->sg);
  708. i++;
  709. } while (i < len);
  710. } while (!desc);
  711. prev->hwdesc->next = 0;
  712. spin_unlock_irq(&chan->lock);
  713. return desc;
  714. }
  715. static void nbpf_chan_idle(struct nbpf_channel *chan)
  716. {
  717. struct nbpf_desc *desc, *tmp;
  718. unsigned long flags;
  719. LIST_HEAD(head);
  720. spin_lock_irqsave(&chan->lock, flags);
  721. list_splice_init(&chan->done, &head);
  722. list_splice_init(&chan->active, &head);
  723. list_splice_init(&chan->queued, &head);
  724. chan->running = NULL;
  725. spin_unlock_irqrestore(&chan->lock, flags);
  726. list_for_each_entry_safe(desc, tmp, &head, node) {
  727. dev_dbg(chan->nbpf->dma_dev.dev, "%s(): force-free desc %p cookie %d\n",
  728. __func__, desc, desc->async_tx.cookie);
  729. list_del(&desc->node);
  730. nbpf_desc_put(desc);
  731. }
  732. }
  733. static int nbpf_pause(struct dma_chan *dchan)
  734. {
  735. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  736. dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
  737. chan->paused = true;
  738. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETSUS);
  739. /* See comment in nbpf_prep_one() */
  740. nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
  741. return 0;
  742. }
  743. static int nbpf_terminate_all(struct dma_chan *dchan)
  744. {
  745. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  746. dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
  747. dev_dbg(dchan->device->dev, "Terminating\n");
  748. nbpf_chan_halt(chan);
  749. nbpf_chan_idle(chan);
  750. return 0;
  751. }
  752. static int nbpf_config(struct dma_chan *dchan,
  753. struct dma_slave_config *config)
  754. {
  755. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  756. dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
  757. /*
  758. * We could check config->slave_id to match chan->terminal here,
  759. * but with DT they would be coming from the same source, so
  760. * such a check would be superflous
  761. */
  762. chan->slave_dst_addr = config->dst_addr;
  763. chan->slave_dst_width = nbpf_xfer_size(chan->nbpf,
  764. config->dst_addr_width, 1);
  765. chan->slave_dst_burst = nbpf_xfer_size(chan->nbpf,
  766. config->dst_addr_width,
  767. config->dst_maxburst);
  768. chan->slave_src_addr = config->src_addr;
  769. chan->slave_src_width = nbpf_xfer_size(chan->nbpf,
  770. config->src_addr_width, 1);
  771. chan->slave_src_burst = nbpf_xfer_size(chan->nbpf,
  772. config->src_addr_width,
  773. config->src_maxburst);
  774. return 0;
  775. }
  776. static struct dma_async_tx_descriptor *nbpf_prep_sg(struct nbpf_channel *chan,
  777. struct scatterlist *src_sg, struct scatterlist *dst_sg,
  778. size_t len, enum dma_transfer_direction direction,
  779. unsigned long flags)
  780. {
  781. struct nbpf_link_desc *ldesc;
  782. struct scatterlist *mem_sg;
  783. struct nbpf_desc *desc;
  784. bool inc_src, inc_dst;
  785. size_t data_len = 0;
  786. int i = 0;
  787. switch (direction) {
  788. case DMA_DEV_TO_MEM:
  789. mem_sg = dst_sg;
  790. inc_src = false;
  791. inc_dst = true;
  792. break;
  793. case DMA_MEM_TO_DEV:
  794. mem_sg = src_sg;
  795. inc_src = true;
  796. inc_dst = false;
  797. break;
  798. default:
  799. case DMA_MEM_TO_MEM:
  800. mem_sg = src_sg;
  801. inc_src = true;
  802. inc_dst = true;
  803. }
  804. desc = nbpf_desc_get(chan, len);
  805. if (!desc)
  806. return NULL;
  807. desc->async_tx.flags = flags;
  808. desc->async_tx.cookie = -EBUSY;
  809. desc->user_wait = false;
  810. /*
  811. * This is a private descriptor list, and we own the descriptor. No need
  812. * to lock.
  813. */
  814. list_for_each_entry(ldesc, &desc->sg, node) {
  815. int ret = nbpf_prep_one(ldesc, direction,
  816. sg_dma_address(src_sg),
  817. sg_dma_address(dst_sg),
  818. sg_dma_len(mem_sg),
  819. i == len - 1);
  820. if (ret < 0) {
  821. nbpf_desc_put(desc);
  822. return NULL;
  823. }
  824. data_len += sg_dma_len(mem_sg);
  825. if (inc_src)
  826. src_sg = sg_next(src_sg);
  827. if (inc_dst)
  828. dst_sg = sg_next(dst_sg);
  829. mem_sg = direction == DMA_DEV_TO_MEM ? dst_sg : src_sg;
  830. i++;
  831. }
  832. desc->length = data_len;
  833. /* The user has to return the descriptor to us ASAP via .tx_submit() */
  834. return &desc->async_tx;
  835. }
  836. static struct dma_async_tx_descriptor *nbpf_prep_memcpy(
  837. struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
  838. size_t len, unsigned long flags)
  839. {
  840. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  841. struct scatterlist dst_sg;
  842. struct scatterlist src_sg;
  843. sg_init_table(&dst_sg, 1);
  844. sg_init_table(&src_sg, 1);
  845. sg_dma_address(&dst_sg) = dst;
  846. sg_dma_address(&src_sg) = src;
  847. sg_dma_len(&dst_sg) = len;
  848. sg_dma_len(&src_sg) = len;
  849. dev_dbg(dchan->device->dev, "%s(): %zu @ %pad -> %pad\n",
  850. __func__, len, &src, &dst);
  851. return nbpf_prep_sg(chan, &src_sg, &dst_sg, 1,
  852. DMA_MEM_TO_MEM, flags);
  853. }
  854. static struct dma_async_tx_descriptor *nbpf_prep_slave_sg(
  855. struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
  856. enum dma_transfer_direction direction, unsigned long flags, void *context)
  857. {
  858. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  859. struct scatterlist slave_sg;
  860. dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
  861. sg_init_table(&slave_sg, 1);
  862. switch (direction) {
  863. case DMA_MEM_TO_DEV:
  864. sg_dma_address(&slave_sg) = chan->slave_dst_addr;
  865. return nbpf_prep_sg(chan, sgl, &slave_sg, sg_len,
  866. direction, flags);
  867. case DMA_DEV_TO_MEM:
  868. sg_dma_address(&slave_sg) = chan->slave_src_addr;
  869. return nbpf_prep_sg(chan, &slave_sg, sgl, sg_len,
  870. direction, flags);
  871. default:
  872. return NULL;
  873. }
  874. }
  875. static int nbpf_alloc_chan_resources(struct dma_chan *dchan)
  876. {
  877. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  878. int ret;
  879. INIT_LIST_HEAD(&chan->free);
  880. INIT_LIST_HEAD(&chan->free_links);
  881. INIT_LIST_HEAD(&chan->queued);
  882. INIT_LIST_HEAD(&chan->active);
  883. INIT_LIST_HEAD(&chan->done);
  884. ret = nbpf_desc_page_alloc(chan);
  885. if (ret < 0)
  886. return ret;
  887. dev_dbg(dchan->device->dev, "Entry %s(): terminal %u\n", __func__,
  888. chan->terminal);
  889. nbpf_chan_configure(chan);
  890. return ret;
  891. }
  892. static void nbpf_free_chan_resources(struct dma_chan *dchan)
  893. {
  894. struct nbpf_channel *chan = nbpf_to_chan(dchan);
  895. struct nbpf_desc_page *dpage, *tmp;
  896. dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
  897. nbpf_chan_halt(chan);
  898. nbpf_chan_idle(chan);
  899. /* Clean up for if a channel is re-used for MEMCPY after slave DMA */
  900. nbpf_chan_prepare_default(chan);
  901. list_for_each_entry_safe(dpage, tmp, &chan->desc_page, node) {
  902. struct nbpf_link_desc *ldesc;
  903. int i;
  904. list_del(&dpage->node);
  905. for (i = 0, ldesc = dpage->ldesc;
  906. i < ARRAY_SIZE(dpage->ldesc);
  907. i++, ldesc++)
  908. dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr,
  909. sizeof(*ldesc->hwdesc), DMA_TO_DEVICE);
  910. free_page((unsigned long)dpage);
  911. }
  912. }
  913. static struct dma_chan *nbpf_of_xlate(struct of_phandle_args *dma_spec,
  914. struct of_dma *ofdma)
  915. {
  916. struct nbpf_device *nbpf = ofdma->of_dma_data;
  917. struct dma_chan *dchan;
  918. struct nbpf_channel *chan;
  919. if (dma_spec->args_count != 2)
  920. return NULL;
  921. dchan = dma_get_any_slave_channel(&nbpf->dma_dev);
  922. if (!dchan)
  923. return NULL;
  924. dev_dbg(dchan->device->dev, "Entry %s(%pOFn)\n", __func__,
  925. dma_spec->np);
  926. chan = nbpf_to_chan(dchan);
  927. chan->terminal = dma_spec->args[0];
  928. chan->flags = dma_spec->args[1];
  929. nbpf_chan_prepare(chan);
  930. nbpf_chan_configure(chan);
  931. return dchan;
  932. }
  933. static void nbpf_chan_tasklet(struct tasklet_struct *t)
  934. {
  935. struct nbpf_channel *chan = from_tasklet(chan, t, tasklet);
  936. struct nbpf_desc *desc, *tmp;
  937. struct dmaengine_desc_callback cb;
  938. while (!list_empty(&chan->done)) {
  939. bool found = false, must_put, recycling = false;
  940. spin_lock_irq(&chan->lock);
  941. list_for_each_entry_safe(desc, tmp, &chan->done, node) {
  942. if (!desc->user_wait) {
  943. /* Newly completed descriptor, have to process */
  944. found = true;
  945. break;
  946. } else if (async_tx_test_ack(&desc->async_tx)) {
  947. /*
  948. * This descriptor was waiting for a user ACK,
  949. * it can be recycled now.
  950. */
  951. list_del(&desc->node);
  952. spin_unlock_irq(&chan->lock);
  953. nbpf_desc_put(desc);
  954. recycling = true;
  955. break;
  956. }
  957. }
  958. if (recycling)
  959. continue;
  960. if (!found) {
  961. /* This can happen if TERMINATE_ALL has been called */
  962. spin_unlock_irq(&chan->lock);
  963. break;
  964. }
  965. dma_cookie_complete(&desc->async_tx);
  966. /*
  967. * With released lock we cannot dereference desc, maybe it's
  968. * still on the "done" list
  969. */
  970. if (async_tx_test_ack(&desc->async_tx)) {
  971. list_del(&desc->node);
  972. must_put = true;
  973. } else {
  974. desc->user_wait = true;
  975. must_put = false;
  976. }
  977. dmaengine_desc_get_callback(&desc->async_tx, &cb);
  978. /* ack and callback completed descriptor */
  979. spin_unlock_irq(&chan->lock);
  980. dmaengine_desc_callback_invoke(&cb, NULL);
  981. if (must_put)
  982. nbpf_desc_put(desc);
  983. }
  984. }
  985. static irqreturn_t nbpf_chan_irq(int irq, void *dev)
  986. {
  987. struct nbpf_channel *chan = dev;
  988. bool done = nbpf_status_get(chan);
  989. struct nbpf_desc *desc;
  990. irqreturn_t ret;
  991. bool bh = false;
  992. if (!done)
  993. return IRQ_NONE;
  994. nbpf_status_ack(chan);
  995. dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__);
  996. spin_lock(&chan->lock);
  997. desc = chan->running;
  998. if (WARN_ON(!desc)) {
  999. ret = IRQ_NONE;
  1000. goto unlock;
  1001. } else {
  1002. ret = IRQ_HANDLED;
  1003. bh = true;
  1004. }
  1005. list_move_tail(&desc->node, &chan->done);
  1006. chan->running = NULL;
  1007. if (!list_empty(&chan->active)) {
  1008. desc = list_first_entry(&chan->active,
  1009. struct nbpf_desc, node);
  1010. if (!nbpf_start(desc))
  1011. chan->running = desc;
  1012. }
  1013. unlock:
  1014. spin_unlock(&chan->lock);
  1015. if (bh)
  1016. tasklet_schedule(&chan->tasklet);
  1017. return ret;
  1018. }
  1019. static irqreturn_t nbpf_err_irq(int irq, void *dev)
  1020. {
  1021. struct nbpf_device *nbpf = dev;
  1022. u32 error = nbpf_error_get(nbpf);
  1023. dev_warn(nbpf->dma_dev.dev, "DMA error IRQ %u\n", irq);
  1024. if (!error)
  1025. return IRQ_NONE;
  1026. do {
  1027. struct nbpf_channel *chan = nbpf_error_get_channel(nbpf, error);
  1028. /* On error: abort all queued transfers, no callback */
  1029. nbpf_error_clear(chan);
  1030. nbpf_chan_idle(chan);
  1031. error = nbpf_error_get(nbpf);
  1032. } while (error);
  1033. return IRQ_HANDLED;
  1034. }
  1035. static int nbpf_chan_probe(struct nbpf_device *nbpf, int n)
  1036. {
  1037. struct dma_device *dma_dev = &nbpf->dma_dev;
  1038. struct nbpf_channel *chan = nbpf->chan + n;
  1039. int ret;
  1040. chan->nbpf = nbpf;
  1041. chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n;
  1042. INIT_LIST_HEAD(&chan->desc_page);
  1043. spin_lock_init(&chan->lock);
  1044. chan->dma_chan.device = dma_dev;
  1045. dma_cookie_init(&chan->dma_chan);
  1046. nbpf_chan_prepare_default(chan);
  1047. dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base);
  1048. snprintf(chan->name, sizeof(chan->name), "nbpf %d", n);
  1049. tasklet_setup(&chan->tasklet, nbpf_chan_tasklet);
  1050. ret = devm_request_irq(dma_dev->dev, chan->irq,
  1051. nbpf_chan_irq, IRQF_SHARED,
  1052. chan->name, chan);
  1053. if (ret < 0)
  1054. return ret;
  1055. /* Add the channel to DMA device channel list */
  1056. list_add_tail(&chan->dma_chan.device_node,
  1057. &dma_dev->channels);
  1058. return 0;
  1059. }
  1060. static const struct of_device_id nbpf_match[] = {
  1061. {.compatible = "renesas,nbpfaxi64dmac1b4", .data = &nbpf_cfg[NBPF1B4]},
  1062. {.compatible = "renesas,nbpfaxi64dmac1b8", .data = &nbpf_cfg[NBPF1B8]},
  1063. {.compatible = "renesas,nbpfaxi64dmac1b16", .data = &nbpf_cfg[NBPF1B16]},
  1064. {.compatible = "renesas,nbpfaxi64dmac4b4", .data = &nbpf_cfg[NBPF4B4]},
  1065. {.compatible = "renesas,nbpfaxi64dmac4b8", .data = &nbpf_cfg[NBPF4B8]},
  1066. {.compatible = "renesas,nbpfaxi64dmac4b16", .data = &nbpf_cfg[NBPF4B16]},
  1067. {.compatible = "renesas,nbpfaxi64dmac8b4", .data = &nbpf_cfg[NBPF8B4]},
  1068. {.compatible = "renesas,nbpfaxi64dmac8b8", .data = &nbpf_cfg[NBPF8B8]},
  1069. {.compatible = "renesas,nbpfaxi64dmac8b16", .data = &nbpf_cfg[NBPF8B16]},
  1070. {}
  1071. };
  1072. MODULE_DEVICE_TABLE(of, nbpf_match);
  1073. static int nbpf_probe(struct platform_device *pdev)
  1074. {
  1075. struct device *dev = &pdev->dev;
  1076. struct device_node *np = dev->of_node;
  1077. struct nbpf_device *nbpf;
  1078. struct dma_device *dma_dev;
  1079. struct resource *iomem, *irq_res;
  1080. const struct nbpf_config *cfg;
  1081. int num_channels;
  1082. int ret, irq, eirq, i;
  1083. int irqbuf[9] /* maximum 8 channels + error IRQ */;
  1084. unsigned int irqs = 0;
  1085. BUILD_BUG_ON(sizeof(struct nbpf_desc_page) > PAGE_SIZE);
  1086. /* DT only */
  1087. if (!np)
  1088. return -ENODEV;
  1089. cfg = of_device_get_match_data(dev);
  1090. num_channels = cfg->num_channels;
  1091. nbpf = devm_kzalloc(dev, struct_size(nbpf, chan, num_channels),
  1092. GFP_KERNEL);
  1093. if (!nbpf)
  1094. return -ENOMEM;
  1095. dma_dev = &nbpf->dma_dev;
  1096. dma_dev->dev = dev;
  1097. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1098. nbpf->base = devm_ioremap_resource(dev, iomem);
  1099. if (IS_ERR(nbpf->base))
  1100. return PTR_ERR(nbpf->base);
  1101. nbpf->clk = devm_clk_get(dev, NULL);
  1102. if (IS_ERR(nbpf->clk))
  1103. return PTR_ERR(nbpf->clk);
  1104. of_property_read_u32(np, "max-burst-mem-read",
  1105. &nbpf->max_burst_mem_read);
  1106. of_property_read_u32(np, "max-burst-mem-write",
  1107. &nbpf->max_burst_mem_write);
  1108. nbpf->config = cfg;
  1109. for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
  1110. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
  1111. if (!irq_res)
  1112. break;
  1113. for (irq = irq_res->start; irq <= irq_res->end;
  1114. irq++, irqs++)
  1115. irqbuf[irqs] = irq;
  1116. }
  1117. /*
  1118. * 3 IRQ resource schemes are supported:
  1119. * 1. 1 shared IRQ for error and all channels
  1120. * 2. 2 IRQs: one for error and one shared for all channels
  1121. * 3. 1 IRQ for error and an own IRQ for each channel
  1122. */
  1123. if (irqs != 1 && irqs != 2 && irqs != num_channels + 1)
  1124. return -ENXIO;
  1125. if (irqs == 1) {
  1126. eirq = irqbuf[0];
  1127. for (i = 0; i <= num_channels; i++)
  1128. nbpf->chan[i].irq = irqbuf[0];
  1129. } else {
  1130. eirq = platform_get_irq_byname(pdev, "error");
  1131. if (eirq < 0)
  1132. return eirq;
  1133. if (irqs == num_channels + 1) {
  1134. struct nbpf_channel *chan;
  1135. for (i = 0, chan = nbpf->chan; i <= num_channels;
  1136. i++, chan++) {
  1137. /* Skip the error IRQ */
  1138. if (irqbuf[i] == eirq)
  1139. i++;
  1140. chan->irq = irqbuf[i];
  1141. }
  1142. if (chan != nbpf->chan + num_channels)
  1143. return -EINVAL;
  1144. } else {
  1145. /* 2 IRQs and more than one channel */
  1146. if (irqbuf[0] == eirq)
  1147. irq = irqbuf[1];
  1148. else
  1149. irq = irqbuf[0];
  1150. for (i = 0; i <= num_channels; i++)
  1151. nbpf->chan[i].irq = irq;
  1152. }
  1153. }
  1154. ret = devm_request_irq(dev, eirq, nbpf_err_irq,
  1155. IRQF_SHARED, "dma error", nbpf);
  1156. if (ret < 0)
  1157. return ret;
  1158. nbpf->eirq = eirq;
  1159. INIT_LIST_HEAD(&dma_dev->channels);
  1160. /* Create DMA Channel */
  1161. for (i = 0; i < num_channels; i++) {
  1162. ret = nbpf_chan_probe(nbpf, i);
  1163. if (ret < 0)
  1164. return ret;
  1165. }
  1166. dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
  1167. dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
  1168. dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
  1169. /* Common and MEMCPY operations */
  1170. dma_dev->device_alloc_chan_resources
  1171. = nbpf_alloc_chan_resources;
  1172. dma_dev->device_free_chan_resources = nbpf_free_chan_resources;
  1173. dma_dev->device_prep_dma_memcpy = nbpf_prep_memcpy;
  1174. dma_dev->device_tx_status = nbpf_tx_status;
  1175. dma_dev->device_issue_pending = nbpf_issue_pending;
  1176. /*
  1177. * If we drop support for unaligned MEMCPY buffer addresses and / or
  1178. * lengths by setting
  1179. * dma_dev->copy_align = 4;
  1180. * then we can set transfer length to 4 bytes in nbpf_prep_one() for
  1181. * DMA_MEM_TO_MEM
  1182. */
  1183. /* Compulsory for DMA_SLAVE fields */
  1184. dma_dev->device_prep_slave_sg = nbpf_prep_slave_sg;
  1185. dma_dev->device_config = nbpf_config;
  1186. dma_dev->device_pause = nbpf_pause;
  1187. dma_dev->device_terminate_all = nbpf_terminate_all;
  1188. dma_dev->src_addr_widths = NBPF_DMA_BUSWIDTHS;
  1189. dma_dev->dst_addr_widths = NBPF_DMA_BUSWIDTHS;
  1190. dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  1191. platform_set_drvdata(pdev, nbpf);
  1192. ret = clk_prepare_enable(nbpf->clk);
  1193. if (ret < 0)
  1194. return ret;
  1195. nbpf_configure(nbpf);
  1196. ret = dma_async_device_register(dma_dev);
  1197. if (ret < 0)
  1198. goto e_clk_off;
  1199. ret = of_dma_controller_register(np, nbpf_of_xlate, nbpf);
  1200. if (ret < 0)
  1201. goto e_dma_dev_unreg;
  1202. return 0;
  1203. e_dma_dev_unreg:
  1204. dma_async_device_unregister(dma_dev);
  1205. e_clk_off:
  1206. clk_disable_unprepare(nbpf->clk);
  1207. return ret;
  1208. }
  1209. static int nbpf_remove(struct platform_device *pdev)
  1210. {
  1211. struct nbpf_device *nbpf = platform_get_drvdata(pdev);
  1212. int i;
  1213. devm_free_irq(&pdev->dev, nbpf->eirq, nbpf);
  1214. for (i = 0; i < nbpf->config->num_channels; i++) {
  1215. struct nbpf_channel *chan = nbpf->chan + i;
  1216. devm_free_irq(&pdev->dev, chan->irq, chan);
  1217. tasklet_kill(&chan->tasklet);
  1218. }
  1219. of_dma_controller_free(pdev->dev.of_node);
  1220. dma_async_device_unregister(&nbpf->dma_dev);
  1221. clk_disable_unprepare(nbpf->clk);
  1222. return 0;
  1223. }
  1224. static const struct platform_device_id nbpf_ids[] = {
  1225. {"nbpfaxi64dmac1b4", (kernel_ulong_t)&nbpf_cfg[NBPF1B4]},
  1226. {"nbpfaxi64dmac1b8", (kernel_ulong_t)&nbpf_cfg[NBPF1B8]},
  1227. {"nbpfaxi64dmac1b16", (kernel_ulong_t)&nbpf_cfg[NBPF1B16]},
  1228. {"nbpfaxi64dmac4b4", (kernel_ulong_t)&nbpf_cfg[NBPF4B4]},
  1229. {"nbpfaxi64dmac4b8", (kernel_ulong_t)&nbpf_cfg[NBPF4B8]},
  1230. {"nbpfaxi64dmac4b16", (kernel_ulong_t)&nbpf_cfg[NBPF4B16]},
  1231. {"nbpfaxi64dmac8b4", (kernel_ulong_t)&nbpf_cfg[NBPF8B4]},
  1232. {"nbpfaxi64dmac8b8", (kernel_ulong_t)&nbpf_cfg[NBPF8B8]},
  1233. {"nbpfaxi64dmac8b16", (kernel_ulong_t)&nbpf_cfg[NBPF8B16]},
  1234. {},
  1235. };
  1236. MODULE_DEVICE_TABLE(platform, nbpf_ids);
  1237. #ifdef CONFIG_PM
  1238. static int nbpf_runtime_suspend(struct device *dev)
  1239. {
  1240. struct nbpf_device *nbpf = dev_get_drvdata(dev);
  1241. clk_disable_unprepare(nbpf->clk);
  1242. return 0;
  1243. }
  1244. static int nbpf_runtime_resume(struct device *dev)
  1245. {
  1246. struct nbpf_device *nbpf = dev_get_drvdata(dev);
  1247. return clk_prepare_enable(nbpf->clk);
  1248. }
  1249. #endif
  1250. static const struct dev_pm_ops nbpf_pm_ops = {
  1251. SET_RUNTIME_PM_OPS(nbpf_runtime_suspend, nbpf_runtime_resume, NULL)
  1252. };
  1253. static struct platform_driver nbpf_driver = {
  1254. .driver = {
  1255. .name = "dma-nbpf",
  1256. .of_match_table = nbpf_match,
  1257. .pm = &nbpf_pm_ops,
  1258. },
  1259. .id_table = nbpf_ids,
  1260. .probe = nbpf_probe,
  1261. .remove = nbpf_remove,
  1262. };
  1263. module_platform_driver(nbpf_driver);
  1264. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  1265. MODULE_DESCRIPTION("dmaengine driver for NBPFAXI64* DMACs");
  1266. MODULE_LICENSE("GPL v2");