mv_xor.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2007, 2008, Marvell International Ltd.
  4. */
  5. #ifndef MV_XOR_H
  6. #define MV_XOR_H
  7. #include <linux/types.h>
  8. #include <linux/io.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/interrupt.h>
  11. #define MV_XOR_POOL_SIZE (MV_XOR_SLOT_SIZE * 3072)
  12. #define MV_XOR_SLOT_SIZE 64
  13. #define MV_XOR_THRESHOLD 1
  14. #define MV_XOR_MAX_CHANNELS 2
  15. #define MV_XOR_MIN_BYTE_COUNT SZ_128
  16. #define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1)
  17. /* Values for the XOR_CONFIG register */
  18. #define XOR_OPERATION_MODE_XOR 0
  19. #define XOR_OPERATION_MODE_MEMCPY 2
  20. #define XOR_OPERATION_MODE_IN_DESC 7
  21. #define XOR_DESCRIPTOR_SWAP BIT(14)
  22. #define XOR_DESC_SUCCESS 0x40000000
  23. #define XOR_DESC_OPERATION_XOR (0 << 24)
  24. #define XOR_DESC_OPERATION_CRC32C (1 << 24)
  25. #define XOR_DESC_OPERATION_MEMCPY (2 << 24)
  26. #define XOR_DESC_DMA_OWNED BIT(31)
  27. #define XOR_DESC_EOD_INT_EN BIT(31)
  28. #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
  29. #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
  30. #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
  31. #define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
  32. #define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
  33. #define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
  34. #define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
  35. #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
  36. #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
  37. #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
  38. #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
  39. #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
  40. #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
  41. #define XOR_INT_END_OF_DESC BIT(0)
  42. #define XOR_INT_END_OF_CHAIN BIT(1)
  43. #define XOR_INT_STOPPED BIT(2)
  44. #define XOR_INT_PAUSED BIT(3)
  45. #define XOR_INT_ERR_DECODE BIT(4)
  46. #define XOR_INT_ERR_RDPROT BIT(5)
  47. #define XOR_INT_ERR_WRPROT BIT(6)
  48. #define XOR_INT_ERR_OWN BIT(7)
  49. #define XOR_INT_ERR_PAR BIT(8)
  50. #define XOR_INT_ERR_MBUS BIT(9)
  51. #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
  52. XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \
  53. XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS)
  54. #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
  55. XOR_INT_STOPPED | XOR_INTR_ERRORS)
  56. #define WINDOW_BASE(w) (0x50 + ((w) << 2))
  57. #define WINDOW_SIZE(w) (0x70 + ((w) << 2))
  58. #define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
  59. #define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
  60. #define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
  61. #define WINDOW_COUNT 8
  62. struct mv_xor_device {
  63. void __iomem *xor_base;
  64. void __iomem *xor_high_base;
  65. struct clk *clk;
  66. struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
  67. int xor_type;
  68. u32 win_start[WINDOW_COUNT];
  69. u32 win_end[WINDOW_COUNT];
  70. };
  71. /**
  72. * struct mv_xor_chan - internal representation of a XOR channel
  73. * @pending: allows batching of hardware operations
  74. * @lock: serializes enqueue/dequeue operations to the descriptors pool
  75. * @mmr_base: memory mapped register base
  76. * @idx: the index of the xor channel
  77. * @chain: device chain view of the descriptors
  78. * @free_slots: free slots usable by the channel
  79. * @allocated_slots: slots allocated by the driver
  80. * @completed_slots: slots completed by HW but still need to be acked
  81. * @device: parent device
  82. * @common: common dmaengine channel object members
  83. * @slots_allocated: records the actual size of the descriptor slot pool
  84. * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
  85. * @op_in_desc: new mode of driver, each op is writen to descriptor.
  86. */
  87. struct mv_xor_chan {
  88. int pending;
  89. spinlock_t lock; /* protects the descriptor slot pool */
  90. void __iomem *mmr_base;
  91. void __iomem *mmr_high_base;
  92. unsigned int idx;
  93. int irq;
  94. struct list_head chain;
  95. struct list_head free_slots;
  96. struct list_head allocated_slots;
  97. struct list_head completed_slots;
  98. dma_addr_t dma_desc_pool;
  99. void *dma_desc_pool_virt;
  100. size_t pool_size;
  101. struct dma_device dmadev;
  102. struct dma_chan dmachan;
  103. int slots_allocated;
  104. struct tasklet_struct irq_tasklet;
  105. int op_in_desc;
  106. char dummy_src[MV_XOR_MIN_BYTE_COUNT];
  107. char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
  108. dma_addr_t dummy_src_addr, dummy_dst_addr;
  109. u32 saved_config_reg, saved_int_mask_reg;
  110. struct mv_xor_device *xordev;
  111. };
  112. /**
  113. * struct mv_xor_desc_slot - software descriptor
  114. * @node: node on the mv_xor_chan lists
  115. * @hw_desc: virtual address of the hardware descriptor chain
  116. * @phys: hardware address of the hardware descriptor chain
  117. * @slot_used: slot in use or not
  118. * @idx: pool index
  119. * @tx_list: list of slots that make up a multi-descriptor transaction
  120. * @async_tx: support for the async_tx api
  121. */
  122. struct mv_xor_desc_slot {
  123. struct list_head node;
  124. struct list_head sg_tx_list;
  125. enum dma_transaction_type type;
  126. void *hw_desc;
  127. u16 idx;
  128. struct dma_async_tx_descriptor async_tx;
  129. };
  130. /*
  131. * This structure describes XOR descriptor size 64bytes. The
  132. * mv_phy_src_idx() macro must be used when indexing the values of the
  133. * phy_src_addr[] array. This is due to the fact that the 'descriptor
  134. * swap' feature, used on big endian systems, swaps descriptors data
  135. * within blocks of 8 bytes. So two consecutive values of the
  136. * phy_src_addr[] array are actually swapped in big-endian, which
  137. * explains the different mv_phy_src_idx() implementation.
  138. */
  139. #if defined(__LITTLE_ENDIAN)
  140. struct mv_xor_desc {
  141. u32 status; /* descriptor execution status */
  142. u32 crc32_result; /* result of CRC-32 calculation */
  143. u32 desc_command; /* type of operation to be carried out */
  144. u32 phy_next_desc; /* next descriptor address pointer */
  145. u32 byte_count; /* size of src/dst blocks in bytes */
  146. u32 phy_dest_addr; /* destination block address */
  147. u32 phy_src_addr[8]; /* source block addresses */
  148. u32 reserved0;
  149. u32 reserved1;
  150. };
  151. #define mv_phy_src_idx(src_idx) (src_idx)
  152. #else
  153. struct mv_xor_desc {
  154. u32 crc32_result; /* result of CRC-32 calculation */
  155. u32 status; /* descriptor execution status */
  156. u32 phy_next_desc; /* next descriptor address pointer */
  157. u32 desc_command; /* type of operation to be carried out */
  158. u32 phy_dest_addr; /* destination block address */
  159. u32 byte_count; /* size of src/dst blocks in bytes */
  160. u32 phy_src_addr[8]; /* source block addresses */
  161. u32 reserved1;
  162. u32 reserved0;
  163. };
  164. #define mv_phy_src_idx(src_idx) (src_idx ^ 1)
  165. #endif
  166. #define to_mv_sw_desc(addr_hw_desc) \
  167. container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
  168. #define mv_hw_desc_slot_idx(hw_desc, idx) \
  169. ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
  170. #endif