mv_xor.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * offload engine driver for the Marvell XOR engine
  4. * Copyright (C) 2007, 2008, Marvell International Ltd.
  5. */
  6. #include <linux/init.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/memory.h>
  15. #include <linux/clk.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/cpumask.h>
  20. #include <linux/platform_data/dma-mv_xor.h>
  21. #include "dmaengine.h"
  22. #include "mv_xor.h"
  23. enum mv_xor_type {
  24. XOR_ORION,
  25. XOR_ARMADA_38X,
  26. XOR_ARMADA_37XX,
  27. };
  28. enum mv_xor_mode {
  29. XOR_MODE_IN_REG,
  30. XOR_MODE_IN_DESC,
  31. };
  32. static void mv_xor_issue_pending(struct dma_chan *chan);
  33. #define to_mv_xor_chan(chan) \
  34. container_of(chan, struct mv_xor_chan, dmachan)
  35. #define to_mv_xor_slot(tx) \
  36. container_of(tx, struct mv_xor_desc_slot, async_tx)
  37. #define mv_chan_to_devp(chan) \
  38. ((chan)->dmadev.dev)
  39. static void mv_desc_init(struct mv_xor_desc_slot *desc,
  40. dma_addr_t addr, u32 byte_count,
  41. enum dma_ctrl_flags flags)
  42. {
  43. struct mv_xor_desc *hw_desc = desc->hw_desc;
  44. hw_desc->status = XOR_DESC_DMA_OWNED;
  45. hw_desc->phy_next_desc = 0;
  46. /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
  47. hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
  48. XOR_DESC_EOD_INT_EN : 0;
  49. hw_desc->phy_dest_addr = addr;
  50. hw_desc->byte_count = byte_count;
  51. }
  52. static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
  53. {
  54. struct mv_xor_desc *hw_desc = desc->hw_desc;
  55. switch (desc->type) {
  56. case DMA_XOR:
  57. case DMA_INTERRUPT:
  58. hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
  59. break;
  60. case DMA_MEMCPY:
  61. hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
  62. break;
  63. default:
  64. BUG();
  65. return;
  66. }
  67. }
  68. static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
  69. u32 next_desc_addr)
  70. {
  71. struct mv_xor_desc *hw_desc = desc->hw_desc;
  72. BUG_ON(hw_desc->phy_next_desc);
  73. hw_desc->phy_next_desc = next_desc_addr;
  74. }
  75. static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
  76. int index, dma_addr_t addr)
  77. {
  78. struct mv_xor_desc *hw_desc = desc->hw_desc;
  79. hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
  80. if (desc->type == DMA_XOR)
  81. hw_desc->desc_command |= (1 << index);
  82. }
  83. static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
  84. {
  85. return readl_relaxed(XOR_CURR_DESC(chan));
  86. }
  87. static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
  88. u32 next_desc_addr)
  89. {
  90. writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
  91. }
  92. static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
  93. {
  94. u32 val = readl_relaxed(XOR_INTR_MASK(chan));
  95. val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
  96. writel_relaxed(val, XOR_INTR_MASK(chan));
  97. }
  98. static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
  99. {
  100. u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
  101. intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
  102. return intr_cause;
  103. }
  104. static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
  105. {
  106. u32 val;
  107. val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
  108. val = ~(val << (chan->idx * 16));
  109. dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
  110. writel_relaxed(val, XOR_INTR_CAUSE(chan));
  111. }
  112. static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
  113. {
  114. u32 val = 0xFFFF0000 >> (chan->idx * 16);
  115. writel_relaxed(val, XOR_INTR_CAUSE(chan));
  116. }
  117. static void mv_chan_set_mode(struct mv_xor_chan *chan,
  118. u32 op_mode)
  119. {
  120. u32 config = readl_relaxed(XOR_CONFIG(chan));
  121. config &= ~0x7;
  122. config |= op_mode;
  123. #if defined(__BIG_ENDIAN)
  124. config |= XOR_DESCRIPTOR_SWAP;
  125. #else
  126. config &= ~XOR_DESCRIPTOR_SWAP;
  127. #endif
  128. writel_relaxed(config, XOR_CONFIG(chan));
  129. }
  130. static void mv_chan_activate(struct mv_xor_chan *chan)
  131. {
  132. dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
  133. /* writel ensures all descriptors are flushed before activation */
  134. writel(BIT(0), XOR_ACTIVATION(chan));
  135. }
  136. static char mv_chan_is_busy(struct mv_xor_chan *chan)
  137. {
  138. u32 state = readl_relaxed(XOR_ACTIVATION(chan));
  139. state = (state >> 4) & 0x3;
  140. return (state == 1) ? 1 : 0;
  141. }
  142. /*
  143. * mv_chan_start_new_chain - program the engine to operate on new
  144. * chain headed by sw_desc
  145. * Caller must hold &mv_chan->lock while calling this function
  146. */
  147. static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
  148. struct mv_xor_desc_slot *sw_desc)
  149. {
  150. dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
  151. __func__, __LINE__, sw_desc);
  152. /* set the hardware chain */
  153. mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
  154. mv_chan->pending++;
  155. mv_xor_issue_pending(&mv_chan->dmachan);
  156. }
  157. static dma_cookie_t
  158. mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
  159. struct mv_xor_chan *mv_chan,
  160. dma_cookie_t cookie)
  161. {
  162. BUG_ON(desc->async_tx.cookie < 0);
  163. if (desc->async_tx.cookie > 0) {
  164. cookie = desc->async_tx.cookie;
  165. dma_descriptor_unmap(&desc->async_tx);
  166. /* call the callback (must not sleep or submit new
  167. * operations to this channel)
  168. */
  169. dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL);
  170. }
  171. /* run dependent operations */
  172. dma_run_dependencies(&desc->async_tx);
  173. return cookie;
  174. }
  175. static int
  176. mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
  177. {
  178. struct mv_xor_desc_slot *iter, *_iter;
  179. dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
  180. list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
  181. node) {
  182. if (async_tx_test_ack(&iter->async_tx)) {
  183. list_move_tail(&iter->node, &mv_chan->free_slots);
  184. if (!list_empty(&iter->sg_tx_list)) {
  185. list_splice_tail_init(&iter->sg_tx_list,
  186. &mv_chan->free_slots);
  187. }
  188. }
  189. }
  190. return 0;
  191. }
  192. static int
  193. mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
  194. struct mv_xor_chan *mv_chan)
  195. {
  196. dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
  197. __func__, __LINE__, desc, desc->async_tx.flags);
  198. /* the client is allowed to attach dependent operations
  199. * until 'ack' is set
  200. */
  201. if (!async_tx_test_ack(&desc->async_tx)) {
  202. /* move this slot to the completed_slots */
  203. list_move_tail(&desc->node, &mv_chan->completed_slots);
  204. if (!list_empty(&desc->sg_tx_list)) {
  205. list_splice_tail_init(&desc->sg_tx_list,
  206. &mv_chan->completed_slots);
  207. }
  208. } else {
  209. list_move_tail(&desc->node, &mv_chan->free_slots);
  210. if (!list_empty(&desc->sg_tx_list)) {
  211. list_splice_tail_init(&desc->sg_tx_list,
  212. &mv_chan->free_slots);
  213. }
  214. }
  215. return 0;
  216. }
  217. /* This function must be called with the mv_xor_chan spinlock held */
  218. static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
  219. {
  220. struct mv_xor_desc_slot *iter, *_iter;
  221. dma_cookie_t cookie = 0;
  222. int busy = mv_chan_is_busy(mv_chan);
  223. u32 current_desc = mv_chan_get_current_desc(mv_chan);
  224. int current_cleaned = 0;
  225. struct mv_xor_desc *hw_desc;
  226. dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
  227. dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
  228. mv_chan_clean_completed_slots(mv_chan);
  229. /* free completed slots from the chain starting with
  230. * the oldest descriptor
  231. */
  232. list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
  233. node) {
  234. /* clean finished descriptors */
  235. hw_desc = iter->hw_desc;
  236. if (hw_desc->status & XOR_DESC_SUCCESS) {
  237. cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
  238. cookie);
  239. /* done processing desc, clean slot */
  240. mv_desc_clean_slot(iter, mv_chan);
  241. /* break if we did cleaned the current */
  242. if (iter->async_tx.phys == current_desc) {
  243. current_cleaned = 1;
  244. break;
  245. }
  246. } else {
  247. if (iter->async_tx.phys == current_desc) {
  248. current_cleaned = 0;
  249. break;
  250. }
  251. }
  252. }
  253. if ((busy == 0) && !list_empty(&mv_chan->chain)) {
  254. if (current_cleaned) {
  255. /*
  256. * current descriptor cleaned and removed, run
  257. * from list head
  258. */
  259. iter = list_entry(mv_chan->chain.next,
  260. struct mv_xor_desc_slot,
  261. node);
  262. mv_chan_start_new_chain(mv_chan, iter);
  263. } else {
  264. if (!list_is_last(&iter->node, &mv_chan->chain)) {
  265. /*
  266. * descriptors are still waiting after
  267. * current, trigger them
  268. */
  269. iter = list_entry(iter->node.next,
  270. struct mv_xor_desc_slot,
  271. node);
  272. mv_chan_start_new_chain(mv_chan, iter);
  273. } else {
  274. /*
  275. * some descriptors are still waiting
  276. * to be cleaned
  277. */
  278. tasklet_schedule(&mv_chan->irq_tasklet);
  279. }
  280. }
  281. }
  282. if (cookie > 0)
  283. mv_chan->dmachan.completed_cookie = cookie;
  284. }
  285. static void mv_xor_tasklet(struct tasklet_struct *t)
  286. {
  287. struct mv_xor_chan *chan = from_tasklet(chan, t, irq_tasklet);
  288. spin_lock(&chan->lock);
  289. mv_chan_slot_cleanup(chan);
  290. spin_unlock(&chan->lock);
  291. }
  292. static struct mv_xor_desc_slot *
  293. mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
  294. {
  295. struct mv_xor_desc_slot *iter;
  296. spin_lock_bh(&mv_chan->lock);
  297. if (!list_empty(&mv_chan->free_slots)) {
  298. iter = list_first_entry(&mv_chan->free_slots,
  299. struct mv_xor_desc_slot,
  300. node);
  301. list_move_tail(&iter->node, &mv_chan->allocated_slots);
  302. spin_unlock_bh(&mv_chan->lock);
  303. /* pre-ack descriptor */
  304. async_tx_ack(&iter->async_tx);
  305. iter->async_tx.cookie = -EBUSY;
  306. return iter;
  307. }
  308. spin_unlock_bh(&mv_chan->lock);
  309. /* try to free some slots if the allocation fails */
  310. tasklet_schedule(&mv_chan->irq_tasklet);
  311. return NULL;
  312. }
  313. /************************ DMA engine API functions ****************************/
  314. static dma_cookie_t
  315. mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
  316. {
  317. struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
  318. struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
  319. struct mv_xor_desc_slot *old_chain_tail;
  320. dma_cookie_t cookie;
  321. int new_hw_chain = 1;
  322. dev_dbg(mv_chan_to_devp(mv_chan),
  323. "%s sw_desc %p: async_tx %p\n",
  324. __func__, sw_desc, &sw_desc->async_tx);
  325. spin_lock_bh(&mv_chan->lock);
  326. cookie = dma_cookie_assign(tx);
  327. if (list_empty(&mv_chan->chain))
  328. list_move_tail(&sw_desc->node, &mv_chan->chain);
  329. else {
  330. new_hw_chain = 0;
  331. old_chain_tail = list_entry(mv_chan->chain.prev,
  332. struct mv_xor_desc_slot,
  333. node);
  334. list_move_tail(&sw_desc->node, &mv_chan->chain);
  335. dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
  336. &old_chain_tail->async_tx.phys);
  337. /* fix up the hardware chain */
  338. mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
  339. /* if the channel is not busy */
  340. if (!mv_chan_is_busy(mv_chan)) {
  341. u32 current_desc = mv_chan_get_current_desc(mv_chan);
  342. /*
  343. * and the curren desc is the end of the chain before
  344. * the append, then we need to start the channel
  345. */
  346. if (current_desc == old_chain_tail->async_tx.phys)
  347. new_hw_chain = 1;
  348. }
  349. }
  350. if (new_hw_chain)
  351. mv_chan_start_new_chain(mv_chan, sw_desc);
  352. spin_unlock_bh(&mv_chan->lock);
  353. return cookie;
  354. }
  355. /* returns the number of allocated descriptors */
  356. static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
  357. {
  358. void *virt_desc;
  359. dma_addr_t dma_desc;
  360. int idx;
  361. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  362. struct mv_xor_desc_slot *slot = NULL;
  363. int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
  364. /* Allocate descriptor slots */
  365. idx = mv_chan->slots_allocated;
  366. while (idx < num_descs_in_pool) {
  367. slot = kzalloc(sizeof(*slot), GFP_KERNEL);
  368. if (!slot) {
  369. dev_info(mv_chan_to_devp(mv_chan),
  370. "channel only initialized %d descriptor slots",
  371. idx);
  372. break;
  373. }
  374. virt_desc = mv_chan->dma_desc_pool_virt;
  375. slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
  376. dma_async_tx_descriptor_init(&slot->async_tx, chan);
  377. slot->async_tx.tx_submit = mv_xor_tx_submit;
  378. INIT_LIST_HEAD(&slot->node);
  379. INIT_LIST_HEAD(&slot->sg_tx_list);
  380. dma_desc = mv_chan->dma_desc_pool;
  381. slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
  382. slot->idx = idx++;
  383. spin_lock_bh(&mv_chan->lock);
  384. mv_chan->slots_allocated = idx;
  385. list_add_tail(&slot->node, &mv_chan->free_slots);
  386. spin_unlock_bh(&mv_chan->lock);
  387. }
  388. dev_dbg(mv_chan_to_devp(mv_chan),
  389. "allocated %d descriptor slots\n",
  390. mv_chan->slots_allocated);
  391. return mv_chan->slots_allocated ? : -ENOMEM;
  392. }
  393. /*
  394. * Check if source or destination is an PCIe/IO address (non-SDRAM) and add
  395. * a new MBus window if necessary. Use a cache for these check so that
  396. * the MMIO mapped registers don't have to be accessed for this check
  397. * to speed up this process.
  398. */
  399. static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr)
  400. {
  401. struct mv_xor_device *xordev = mv_chan->xordev;
  402. void __iomem *base = mv_chan->mmr_high_base;
  403. u32 win_enable;
  404. u32 size;
  405. u8 target, attr;
  406. int ret;
  407. int i;
  408. /* Nothing needs to get done for the Armada 3700 */
  409. if (xordev->xor_type == XOR_ARMADA_37XX)
  410. return 0;
  411. /*
  412. * Loop over the cached windows to check, if the requested area
  413. * is already mapped. If this the case, nothing needs to be done
  414. * and we can return.
  415. */
  416. for (i = 0; i < WINDOW_COUNT; i++) {
  417. if (addr >= xordev->win_start[i] &&
  418. addr <= xordev->win_end[i]) {
  419. /* Window is already mapped */
  420. return 0;
  421. }
  422. }
  423. /*
  424. * The window is not mapped, so we need to create the new mapping
  425. */
  426. /* If no IO window is found that addr has to be located in SDRAM */
  427. ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr);
  428. if (ret < 0)
  429. return 0;
  430. /*
  431. * Mask the base addr 'addr' according to 'size' read back from the
  432. * MBus window. Otherwise we might end up with an address located
  433. * somewhere in the middle of this area here.
  434. */
  435. size -= 1;
  436. addr &= ~size;
  437. /*
  438. * Reading one of both enabled register is enough, as they are always
  439. * programmed to the identical values
  440. */
  441. win_enable = readl(base + WINDOW_BAR_ENABLE(0));
  442. /* Set 'i' to the first free window to write the new values to */
  443. i = ffs(~win_enable) - 1;
  444. if (i >= WINDOW_COUNT)
  445. return -ENOMEM;
  446. writel((addr & 0xffff0000) | (attr << 8) | target,
  447. base + WINDOW_BASE(i));
  448. writel(size & 0xffff0000, base + WINDOW_SIZE(i));
  449. /* Fill the caching variables for later use */
  450. xordev->win_start[i] = addr;
  451. xordev->win_end[i] = addr + size;
  452. win_enable |= (1 << i);
  453. win_enable |= 3 << (16 + (2 * i));
  454. writel(win_enable, base + WINDOW_BAR_ENABLE(0));
  455. writel(win_enable, base + WINDOW_BAR_ENABLE(1));
  456. return 0;
  457. }
  458. static struct dma_async_tx_descriptor *
  459. mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
  460. unsigned int src_cnt, size_t len, unsigned long flags)
  461. {
  462. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  463. struct mv_xor_desc_slot *sw_desc;
  464. int ret;
  465. if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
  466. return NULL;
  467. BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
  468. dev_dbg(mv_chan_to_devp(mv_chan),
  469. "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
  470. __func__, src_cnt, len, &dest, flags);
  471. /* Check if a new window needs to get added for 'dest' */
  472. ret = mv_xor_add_io_win(mv_chan, dest);
  473. if (ret)
  474. return NULL;
  475. sw_desc = mv_chan_alloc_slot(mv_chan);
  476. if (sw_desc) {
  477. sw_desc->type = DMA_XOR;
  478. sw_desc->async_tx.flags = flags;
  479. mv_desc_init(sw_desc, dest, len, flags);
  480. if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
  481. mv_desc_set_mode(sw_desc);
  482. while (src_cnt--) {
  483. /* Check if a new window needs to get added for 'src' */
  484. ret = mv_xor_add_io_win(mv_chan, src[src_cnt]);
  485. if (ret)
  486. return NULL;
  487. mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
  488. }
  489. }
  490. dev_dbg(mv_chan_to_devp(mv_chan),
  491. "%s sw_desc %p async_tx %p \n",
  492. __func__, sw_desc, &sw_desc->async_tx);
  493. return sw_desc ? &sw_desc->async_tx : NULL;
  494. }
  495. static struct dma_async_tx_descriptor *
  496. mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  497. size_t len, unsigned long flags)
  498. {
  499. /*
  500. * A MEMCPY operation is identical to an XOR operation with only
  501. * a single source address.
  502. */
  503. return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
  504. }
  505. static struct dma_async_tx_descriptor *
  506. mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
  507. {
  508. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  509. dma_addr_t src, dest;
  510. size_t len;
  511. src = mv_chan->dummy_src_addr;
  512. dest = mv_chan->dummy_dst_addr;
  513. len = MV_XOR_MIN_BYTE_COUNT;
  514. /*
  515. * We implement the DMA_INTERRUPT operation as a minimum sized
  516. * XOR operation with a single dummy source address.
  517. */
  518. return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
  519. }
  520. static void mv_xor_free_chan_resources(struct dma_chan *chan)
  521. {
  522. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  523. struct mv_xor_desc_slot *iter, *_iter;
  524. int in_use_descs = 0;
  525. spin_lock_bh(&mv_chan->lock);
  526. mv_chan_slot_cleanup(mv_chan);
  527. list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
  528. node) {
  529. in_use_descs++;
  530. list_move_tail(&iter->node, &mv_chan->free_slots);
  531. }
  532. list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
  533. node) {
  534. in_use_descs++;
  535. list_move_tail(&iter->node, &mv_chan->free_slots);
  536. }
  537. list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
  538. node) {
  539. in_use_descs++;
  540. list_move_tail(&iter->node, &mv_chan->free_slots);
  541. }
  542. list_for_each_entry_safe_reverse(
  543. iter, _iter, &mv_chan->free_slots, node) {
  544. list_del(&iter->node);
  545. kfree(iter);
  546. mv_chan->slots_allocated--;
  547. }
  548. dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
  549. __func__, mv_chan->slots_allocated);
  550. spin_unlock_bh(&mv_chan->lock);
  551. if (in_use_descs)
  552. dev_err(mv_chan_to_devp(mv_chan),
  553. "freeing %d in use descriptors!\n", in_use_descs);
  554. }
  555. /**
  556. * mv_xor_status - poll the status of an XOR transaction
  557. * @chan: XOR channel handle
  558. * @cookie: XOR transaction identifier
  559. * @txstate: XOR transactions state holder (or NULL)
  560. */
  561. static enum dma_status mv_xor_status(struct dma_chan *chan,
  562. dma_cookie_t cookie,
  563. struct dma_tx_state *txstate)
  564. {
  565. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  566. enum dma_status ret;
  567. ret = dma_cookie_status(chan, cookie, txstate);
  568. if (ret == DMA_COMPLETE)
  569. return ret;
  570. spin_lock_bh(&mv_chan->lock);
  571. mv_chan_slot_cleanup(mv_chan);
  572. spin_unlock_bh(&mv_chan->lock);
  573. return dma_cookie_status(chan, cookie, txstate);
  574. }
  575. static void mv_chan_dump_regs(struct mv_xor_chan *chan)
  576. {
  577. u32 val;
  578. val = readl_relaxed(XOR_CONFIG(chan));
  579. dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
  580. val = readl_relaxed(XOR_ACTIVATION(chan));
  581. dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
  582. val = readl_relaxed(XOR_INTR_CAUSE(chan));
  583. dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
  584. val = readl_relaxed(XOR_INTR_MASK(chan));
  585. dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
  586. val = readl_relaxed(XOR_ERROR_CAUSE(chan));
  587. dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
  588. val = readl_relaxed(XOR_ERROR_ADDR(chan));
  589. dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
  590. }
  591. static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
  592. u32 intr_cause)
  593. {
  594. if (intr_cause & XOR_INT_ERR_DECODE) {
  595. dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
  596. return;
  597. }
  598. dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
  599. chan->idx, intr_cause);
  600. mv_chan_dump_regs(chan);
  601. WARN_ON(1);
  602. }
  603. static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
  604. {
  605. struct mv_xor_chan *chan = data;
  606. u32 intr_cause = mv_chan_get_intr_cause(chan);
  607. dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
  608. if (intr_cause & XOR_INTR_ERRORS)
  609. mv_chan_err_interrupt_handler(chan, intr_cause);
  610. tasklet_schedule(&chan->irq_tasklet);
  611. mv_chan_clear_eoc_cause(chan);
  612. return IRQ_HANDLED;
  613. }
  614. static void mv_xor_issue_pending(struct dma_chan *chan)
  615. {
  616. struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
  617. if (mv_chan->pending >= MV_XOR_THRESHOLD) {
  618. mv_chan->pending = 0;
  619. mv_chan_activate(mv_chan);
  620. }
  621. }
  622. /*
  623. * Perform a transaction to verify the HW works.
  624. */
  625. static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
  626. {
  627. int i, ret;
  628. void *src, *dest;
  629. dma_addr_t src_dma, dest_dma;
  630. struct dma_chan *dma_chan;
  631. dma_cookie_t cookie;
  632. struct dma_async_tx_descriptor *tx;
  633. struct dmaengine_unmap_data *unmap;
  634. int err = 0;
  635. src = kmalloc(PAGE_SIZE, GFP_KERNEL);
  636. if (!src)
  637. return -ENOMEM;
  638. dest = kzalloc(PAGE_SIZE, GFP_KERNEL);
  639. if (!dest) {
  640. kfree(src);
  641. return -ENOMEM;
  642. }
  643. /* Fill in src buffer */
  644. for (i = 0; i < PAGE_SIZE; i++)
  645. ((u8 *) src)[i] = (u8)i;
  646. dma_chan = &mv_chan->dmachan;
  647. if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
  648. err = -ENODEV;
  649. goto out;
  650. }
  651. unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
  652. if (!unmap) {
  653. err = -ENOMEM;
  654. goto free_resources;
  655. }
  656. src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src),
  657. offset_in_page(src), PAGE_SIZE,
  658. DMA_TO_DEVICE);
  659. unmap->addr[0] = src_dma;
  660. ret = dma_mapping_error(dma_chan->device->dev, src_dma);
  661. if (ret) {
  662. err = -ENOMEM;
  663. goto free_resources;
  664. }
  665. unmap->to_cnt = 1;
  666. dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest),
  667. offset_in_page(dest), PAGE_SIZE,
  668. DMA_FROM_DEVICE);
  669. unmap->addr[1] = dest_dma;
  670. ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
  671. if (ret) {
  672. err = -ENOMEM;
  673. goto free_resources;
  674. }
  675. unmap->from_cnt = 1;
  676. unmap->len = PAGE_SIZE;
  677. tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
  678. PAGE_SIZE, 0);
  679. if (!tx) {
  680. dev_err(dma_chan->device->dev,
  681. "Self-test cannot prepare operation, disabling\n");
  682. err = -ENODEV;
  683. goto free_resources;
  684. }
  685. cookie = mv_xor_tx_submit(tx);
  686. if (dma_submit_error(cookie)) {
  687. dev_err(dma_chan->device->dev,
  688. "Self-test submit error, disabling\n");
  689. err = -ENODEV;
  690. goto free_resources;
  691. }
  692. mv_xor_issue_pending(dma_chan);
  693. async_tx_ack(tx);
  694. msleep(1);
  695. if (mv_xor_status(dma_chan, cookie, NULL) !=
  696. DMA_COMPLETE) {
  697. dev_err(dma_chan->device->dev,
  698. "Self-test copy timed out, disabling\n");
  699. err = -ENODEV;
  700. goto free_resources;
  701. }
  702. dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
  703. PAGE_SIZE, DMA_FROM_DEVICE);
  704. if (memcmp(src, dest, PAGE_SIZE)) {
  705. dev_err(dma_chan->device->dev,
  706. "Self-test copy failed compare, disabling\n");
  707. err = -ENODEV;
  708. goto free_resources;
  709. }
  710. free_resources:
  711. dmaengine_unmap_put(unmap);
  712. mv_xor_free_chan_resources(dma_chan);
  713. out:
  714. kfree(src);
  715. kfree(dest);
  716. return err;
  717. }
  718. #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
  719. static int
  720. mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
  721. {
  722. int i, src_idx, ret;
  723. struct page *dest;
  724. struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
  725. dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
  726. dma_addr_t dest_dma;
  727. struct dma_async_tx_descriptor *tx;
  728. struct dmaengine_unmap_data *unmap;
  729. struct dma_chan *dma_chan;
  730. dma_cookie_t cookie;
  731. u8 cmp_byte = 0;
  732. u32 cmp_word;
  733. int err = 0;
  734. int src_count = MV_XOR_NUM_SRC_TEST;
  735. for (src_idx = 0; src_idx < src_count; src_idx++) {
  736. xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
  737. if (!xor_srcs[src_idx]) {
  738. while (src_idx--)
  739. __free_page(xor_srcs[src_idx]);
  740. return -ENOMEM;
  741. }
  742. }
  743. dest = alloc_page(GFP_KERNEL);
  744. if (!dest) {
  745. while (src_idx--)
  746. __free_page(xor_srcs[src_idx]);
  747. return -ENOMEM;
  748. }
  749. /* Fill in src buffers */
  750. for (src_idx = 0; src_idx < src_count; src_idx++) {
  751. u8 *ptr = page_address(xor_srcs[src_idx]);
  752. for (i = 0; i < PAGE_SIZE; i++)
  753. ptr[i] = (1 << src_idx);
  754. }
  755. for (src_idx = 0; src_idx < src_count; src_idx++)
  756. cmp_byte ^= (u8) (1 << src_idx);
  757. cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
  758. (cmp_byte << 8) | cmp_byte;
  759. memset(page_address(dest), 0, PAGE_SIZE);
  760. dma_chan = &mv_chan->dmachan;
  761. if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
  762. err = -ENODEV;
  763. goto out;
  764. }
  765. unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
  766. GFP_KERNEL);
  767. if (!unmap) {
  768. err = -ENOMEM;
  769. goto free_resources;
  770. }
  771. /* test xor */
  772. for (i = 0; i < src_count; i++) {
  773. unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
  774. 0, PAGE_SIZE, DMA_TO_DEVICE);
  775. dma_srcs[i] = unmap->addr[i];
  776. ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
  777. if (ret) {
  778. err = -ENOMEM;
  779. goto free_resources;
  780. }
  781. unmap->to_cnt++;
  782. }
  783. unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
  784. DMA_FROM_DEVICE);
  785. dest_dma = unmap->addr[src_count];
  786. ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
  787. if (ret) {
  788. err = -ENOMEM;
  789. goto free_resources;
  790. }
  791. unmap->from_cnt = 1;
  792. unmap->len = PAGE_SIZE;
  793. tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
  794. src_count, PAGE_SIZE, 0);
  795. if (!tx) {
  796. dev_err(dma_chan->device->dev,
  797. "Self-test cannot prepare operation, disabling\n");
  798. err = -ENODEV;
  799. goto free_resources;
  800. }
  801. cookie = mv_xor_tx_submit(tx);
  802. if (dma_submit_error(cookie)) {
  803. dev_err(dma_chan->device->dev,
  804. "Self-test submit error, disabling\n");
  805. err = -ENODEV;
  806. goto free_resources;
  807. }
  808. mv_xor_issue_pending(dma_chan);
  809. async_tx_ack(tx);
  810. msleep(8);
  811. if (mv_xor_status(dma_chan, cookie, NULL) !=
  812. DMA_COMPLETE) {
  813. dev_err(dma_chan->device->dev,
  814. "Self-test xor timed out, disabling\n");
  815. err = -ENODEV;
  816. goto free_resources;
  817. }
  818. dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
  819. PAGE_SIZE, DMA_FROM_DEVICE);
  820. for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
  821. u32 *ptr = page_address(dest);
  822. if (ptr[i] != cmp_word) {
  823. dev_err(dma_chan->device->dev,
  824. "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
  825. i, ptr[i], cmp_word);
  826. err = -ENODEV;
  827. goto free_resources;
  828. }
  829. }
  830. free_resources:
  831. dmaengine_unmap_put(unmap);
  832. mv_xor_free_chan_resources(dma_chan);
  833. out:
  834. src_idx = src_count;
  835. while (src_idx--)
  836. __free_page(xor_srcs[src_idx]);
  837. __free_page(dest);
  838. return err;
  839. }
  840. static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
  841. {
  842. struct dma_chan *chan, *_chan;
  843. struct device *dev = mv_chan->dmadev.dev;
  844. dma_async_device_unregister(&mv_chan->dmadev);
  845. dma_free_coherent(dev, MV_XOR_POOL_SIZE,
  846. mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
  847. dma_unmap_single(dev, mv_chan->dummy_src_addr,
  848. MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
  849. dma_unmap_single(dev, mv_chan->dummy_dst_addr,
  850. MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
  851. list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
  852. device_node) {
  853. list_del(&chan->device_node);
  854. }
  855. free_irq(mv_chan->irq, mv_chan);
  856. return 0;
  857. }
  858. static struct mv_xor_chan *
  859. mv_xor_channel_add(struct mv_xor_device *xordev,
  860. struct platform_device *pdev,
  861. int idx, dma_cap_mask_t cap_mask, int irq)
  862. {
  863. int ret = 0;
  864. struct mv_xor_chan *mv_chan;
  865. struct dma_device *dma_dev;
  866. mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
  867. if (!mv_chan)
  868. return ERR_PTR(-ENOMEM);
  869. mv_chan->idx = idx;
  870. mv_chan->irq = irq;
  871. if (xordev->xor_type == XOR_ORION)
  872. mv_chan->op_in_desc = XOR_MODE_IN_REG;
  873. else
  874. mv_chan->op_in_desc = XOR_MODE_IN_DESC;
  875. dma_dev = &mv_chan->dmadev;
  876. dma_dev->dev = &pdev->dev;
  877. mv_chan->xordev = xordev;
  878. /*
  879. * These source and destination dummy buffers are used to implement
  880. * a DMA_INTERRUPT operation as a minimum-sized XOR operation.
  881. * Hence, we only need to map the buffers at initialization-time.
  882. */
  883. mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
  884. mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
  885. mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
  886. mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
  887. /* allocate coherent memory for hardware descriptors
  888. * note: writecombine gives slightly better performance, but
  889. * requires that we explicitly flush the writes
  890. */
  891. mv_chan->dma_desc_pool_virt =
  892. dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
  893. GFP_KERNEL);
  894. if (!mv_chan->dma_desc_pool_virt)
  895. return ERR_PTR(-ENOMEM);
  896. /* discover transaction capabilites from the platform data */
  897. dma_dev->cap_mask = cap_mask;
  898. INIT_LIST_HEAD(&dma_dev->channels);
  899. /* set base routines */
  900. dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
  901. dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
  902. dma_dev->device_tx_status = mv_xor_status;
  903. dma_dev->device_issue_pending = mv_xor_issue_pending;
  904. /* set prep routines based on capability */
  905. if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
  906. dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
  907. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
  908. dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
  909. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  910. dma_dev->max_xor = 8;
  911. dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
  912. }
  913. mv_chan->mmr_base = xordev->xor_base;
  914. mv_chan->mmr_high_base = xordev->xor_high_base;
  915. tasklet_setup(&mv_chan->irq_tasklet, mv_xor_tasklet);
  916. /* clear errors before enabling interrupts */
  917. mv_chan_clear_err_status(mv_chan);
  918. ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
  919. 0, dev_name(&pdev->dev), mv_chan);
  920. if (ret)
  921. goto err_free_dma;
  922. mv_chan_unmask_interrupts(mv_chan);
  923. if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
  924. mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
  925. else
  926. mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
  927. spin_lock_init(&mv_chan->lock);
  928. INIT_LIST_HEAD(&mv_chan->chain);
  929. INIT_LIST_HEAD(&mv_chan->completed_slots);
  930. INIT_LIST_HEAD(&mv_chan->free_slots);
  931. INIT_LIST_HEAD(&mv_chan->allocated_slots);
  932. mv_chan->dmachan.device = dma_dev;
  933. dma_cookie_init(&mv_chan->dmachan);
  934. list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
  935. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  936. ret = mv_chan_memcpy_self_test(mv_chan);
  937. dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
  938. if (ret)
  939. goto err_free_irq;
  940. }
  941. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  942. ret = mv_chan_xor_self_test(mv_chan);
  943. dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
  944. if (ret)
  945. goto err_free_irq;
  946. }
  947. dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
  948. mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
  949. dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
  950. dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
  951. dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
  952. ret = dma_async_device_register(dma_dev);
  953. if (ret)
  954. goto err_free_irq;
  955. return mv_chan;
  956. err_free_irq:
  957. free_irq(mv_chan->irq, mv_chan);
  958. err_free_dma:
  959. dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
  960. mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
  961. return ERR_PTR(ret);
  962. }
  963. static void
  964. mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
  965. const struct mbus_dram_target_info *dram)
  966. {
  967. void __iomem *base = xordev->xor_high_base;
  968. u32 win_enable = 0;
  969. int i;
  970. for (i = 0; i < 8; i++) {
  971. writel(0, base + WINDOW_BASE(i));
  972. writel(0, base + WINDOW_SIZE(i));
  973. if (i < 4)
  974. writel(0, base + WINDOW_REMAP_HIGH(i));
  975. }
  976. for (i = 0; i < dram->num_cs; i++) {
  977. const struct mbus_dram_window *cs = dram->cs + i;
  978. writel((cs->base & 0xffff0000) |
  979. (cs->mbus_attr << 8) |
  980. dram->mbus_dram_target_id, base + WINDOW_BASE(i));
  981. writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
  982. /* Fill the caching variables for later use */
  983. xordev->win_start[i] = cs->base;
  984. xordev->win_end[i] = cs->base + cs->size - 1;
  985. win_enable |= (1 << i);
  986. win_enable |= 3 << (16 + (2 * i));
  987. }
  988. writel(win_enable, base + WINDOW_BAR_ENABLE(0));
  989. writel(win_enable, base + WINDOW_BAR_ENABLE(1));
  990. writel(0, base + WINDOW_OVERRIDE_CTRL(0));
  991. writel(0, base + WINDOW_OVERRIDE_CTRL(1));
  992. }
  993. static void
  994. mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
  995. {
  996. void __iomem *base = xordev->xor_high_base;
  997. u32 win_enable = 0;
  998. int i;
  999. for (i = 0; i < 8; i++) {
  1000. writel(0, base + WINDOW_BASE(i));
  1001. writel(0, base + WINDOW_SIZE(i));
  1002. if (i < 4)
  1003. writel(0, base + WINDOW_REMAP_HIGH(i));
  1004. }
  1005. /*
  1006. * For Armada3700 open default 4GB Mbus window. The dram
  1007. * related configuration are done at AXIS level.
  1008. */
  1009. writel(0xffff0000, base + WINDOW_SIZE(0));
  1010. win_enable |= 1;
  1011. win_enable |= 3 << 16;
  1012. writel(win_enable, base + WINDOW_BAR_ENABLE(0));
  1013. writel(win_enable, base + WINDOW_BAR_ENABLE(1));
  1014. writel(0, base + WINDOW_OVERRIDE_CTRL(0));
  1015. writel(0, base + WINDOW_OVERRIDE_CTRL(1));
  1016. }
  1017. /*
  1018. * Since this XOR driver is basically used only for RAID5, we don't
  1019. * need to care about synchronizing ->suspend with DMA activity,
  1020. * because the DMA engine will naturally be quiet due to the block
  1021. * devices being suspended.
  1022. */
  1023. static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
  1024. {
  1025. struct mv_xor_device *xordev = platform_get_drvdata(pdev);
  1026. int i;
  1027. for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
  1028. struct mv_xor_chan *mv_chan = xordev->channels[i];
  1029. if (!mv_chan)
  1030. continue;
  1031. mv_chan->saved_config_reg =
  1032. readl_relaxed(XOR_CONFIG(mv_chan));
  1033. mv_chan->saved_int_mask_reg =
  1034. readl_relaxed(XOR_INTR_MASK(mv_chan));
  1035. }
  1036. return 0;
  1037. }
  1038. static int mv_xor_resume(struct platform_device *dev)
  1039. {
  1040. struct mv_xor_device *xordev = platform_get_drvdata(dev);
  1041. const struct mbus_dram_target_info *dram;
  1042. int i;
  1043. for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
  1044. struct mv_xor_chan *mv_chan = xordev->channels[i];
  1045. if (!mv_chan)
  1046. continue;
  1047. writel_relaxed(mv_chan->saved_config_reg,
  1048. XOR_CONFIG(mv_chan));
  1049. writel_relaxed(mv_chan->saved_int_mask_reg,
  1050. XOR_INTR_MASK(mv_chan));
  1051. }
  1052. if (xordev->xor_type == XOR_ARMADA_37XX) {
  1053. mv_xor_conf_mbus_windows_a3700(xordev);
  1054. return 0;
  1055. }
  1056. dram = mv_mbus_dram_info();
  1057. if (dram)
  1058. mv_xor_conf_mbus_windows(xordev, dram);
  1059. return 0;
  1060. }
  1061. static const struct of_device_id mv_xor_dt_ids[] = {
  1062. { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
  1063. { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
  1064. { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
  1065. {},
  1066. };
  1067. static unsigned int mv_xor_engine_count;
  1068. static int mv_xor_probe(struct platform_device *pdev)
  1069. {
  1070. const struct mbus_dram_target_info *dram;
  1071. struct mv_xor_device *xordev;
  1072. struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1073. struct resource *res;
  1074. unsigned int max_engines, max_channels;
  1075. int i, ret;
  1076. dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
  1077. xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
  1078. if (!xordev)
  1079. return -ENOMEM;
  1080. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1081. if (!res)
  1082. return -ENODEV;
  1083. xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
  1084. resource_size(res));
  1085. if (!xordev->xor_base)
  1086. return -EBUSY;
  1087. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1088. if (!res)
  1089. return -ENODEV;
  1090. xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
  1091. resource_size(res));
  1092. if (!xordev->xor_high_base)
  1093. return -EBUSY;
  1094. platform_set_drvdata(pdev, xordev);
  1095. /*
  1096. * We need to know which type of XOR device we use before
  1097. * setting up. In non-dt case it can only be the legacy one.
  1098. */
  1099. xordev->xor_type = XOR_ORION;
  1100. if (pdev->dev.of_node) {
  1101. const struct of_device_id *of_id =
  1102. of_match_device(mv_xor_dt_ids,
  1103. &pdev->dev);
  1104. xordev->xor_type = (uintptr_t)of_id->data;
  1105. }
  1106. /*
  1107. * (Re-)program MBUS remapping windows if we are asked to.
  1108. */
  1109. if (xordev->xor_type == XOR_ARMADA_37XX) {
  1110. mv_xor_conf_mbus_windows_a3700(xordev);
  1111. } else {
  1112. dram = mv_mbus_dram_info();
  1113. if (dram)
  1114. mv_xor_conf_mbus_windows(xordev, dram);
  1115. }
  1116. /* Not all platforms can gate the clock, so it is not
  1117. * an error if the clock does not exists.
  1118. */
  1119. xordev->clk = clk_get(&pdev->dev, NULL);
  1120. if (!IS_ERR(xordev->clk))
  1121. clk_prepare_enable(xordev->clk);
  1122. /*
  1123. * We don't want to have more than one channel per CPU in
  1124. * order for async_tx to perform well. So we limit the number
  1125. * of engines and channels so that we take into account this
  1126. * constraint. Note that we also want to use channels from
  1127. * separate engines when possible. For dual-CPU Armada 3700
  1128. * SoC with single XOR engine allow using its both channels.
  1129. */
  1130. max_engines = num_present_cpus();
  1131. if (xordev->xor_type == XOR_ARMADA_37XX)
  1132. max_channels = num_present_cpus();
  1133. else
  1134. max_channels = min_t(unsigned int,
  1135. MV_XOR_MAX_CHANNELS,
  1136. DIV_ROUND_UP(num_present_cpus(), 2));
  1137. if (mv_xor_engine_count >= max_engines)
  1138. return 0;
  1139. if (pdev->dev.of_node) {
  1140. struct device_node *np;
  1141. int i = 0;
  1142. for_each_child_of_node(pdev->dev.of_node, np) {
  1143. struct mv_xor_chan *chan;
  1144. dma_cap_mask_t cap_mask;
  1145. int irq;
  1146. if (i >= max_channels)
  1147. continue;
  1148. dma_cap_zero(cap_mask);
  1149. dma_cap_set(DMA_MEMCPY, cap_mask);
  1150. dma_cap_set(DMA_XOR, cap_mask);
  1151. dma_cap_set(DMA_INTERRUPT, cap_mask);
  1152. irq = irq_of_parse_and_map(np, 0);
  1153. if (!irq) {
  1154. ret = -ENODEV;
  1155. goto err_channel_add;
  1156. }
  1157. chan = mv_xor_channel_add(xordev, pdev, i,
  1158. cap_mask, irq);
  1159. if (IS_ERR(chan)) {
  1160. ret = PTR_ERR(chan);
  1161. irq_dispose_mapping(irq);
  1162. goto err_channel_add;
  1163. }
  1164. xordev->channels[i] = chan;
  1165. i++;
  1166. }
  1167. } else if (pdata && pdata->channels) {
  1168. for (i = 0; i < max_channels; i++) {
  1169. struct mv_xor_channel_data *cd;
  1170. struct mv_xor_chan *chan;
  1171. int irq;
  1172. cd = &pdata->channels[i];
  1173. irq = platform_get_irq(pdev, i);
  1174. if (irq < 0) {
  1175. ret = irq;
  1176. goto err_channel_add;
  1177. }
  1178. chan = mv_xor_channel_add(xordev, pdev, i,
  1179. cd->cap_mask, irq);
  1180. if (IS_ERR(chan)) {
  1181. ret = PTR_ERR(chan);
  1182. goto err_channel_add;
  1183. }
  1184. xordev->channels[i] = chan;
  1185. }
  1186. }
  1187. return 0;
  1188. err_channel_add:
  1189. for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
  1190. if (xordev->channels[i]) {
  1191. mv_xor_channel_remove(xordev->channels[i]);
  1192. if (pdev->dev.of_node)
  1193. irq_dispose_mapping(xordev->channels[i]->irq);
  1194. }
  1195. if (!IS_ERR(xordev->clk)) {
  1196. clk_disable_unprepare(xordev->clk);
  1197. clk_put(xordev->clk);
  1198. }
  1199. return ret;
  1200. }
  1201. static struct platform_driver mv_xor_driver = {
  1202. .probe = mv_xor_probe,
  1203. .suspend = mv_xor_suspend,
  1204. .resume = mv_xor_resume,
  1205. .driver = {
  1206. .name = MV_XOR_NAME,
  1207. .of_match_table = of_match_ptr(mv_xor_dt_ids),
  1208. },
  1209. };
  1210. builtin_platform_driver(mv_xor_driver);
  1211. /*
  1212. MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
  1213. MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
  1214. MODULE_LICENSE("GPL");
  1215. */