moxart-dma.c 16 KB

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  1. /*
  2. * MOXA ART SoCs DMA Engine support.
  3. *
  4. * Copyright (C) 2013 Jonas Jensen
  5. *
  6. * Jonas Jensen <jonas.jensen@gmail.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/dmaengine.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/list.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/slab.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/of_dma.h>
  25. #include <linux/bitops.h>
  26. #include <asm/cacheflush.h>
  27. #include "dmaengine.h"
  28. #include "virt-dma.h"
  29. #define APB_DMA_MAX_CHANNEL 4
  30. #define REG_OFF_ADDRESS_SOURCE 0
  31. #define REG_OFF_ADDRESS_DEST 4
  32. #define REG_OFF_CYCLES 8
  33. #define REG_OFF_CTRL 12
  34. #define REG_OFF_CHAN_SIZE 16
  35. #define APB_DMA_ENABLE BIT(0)
  36. #define APB_DMA_FIN_INT_STS BIT(1)
  37. #define APB_DMA_FIN_INT_EN BIT(2)
  38. #define APB_DMA_BURST_MODE BIT(3)
  39. #define APB_DMA_ERR_INT_STS BIT(4)
  40. #define APB_DMA_ERR_INT_EN BIT(5)
  41. /*
  42. * Unset: APB
  43. * Set: AHB
  44. */
  45. #define APB_DMA_SOURCE_SELECT 0x40
  46. #define APB_DMA_DEST_SELECT 0x80
  47. #define APB_DMA_SOURCE 0x100
  48. #define APB_DMA_DEST 0x1000
  49. #define APB_DMA_SOURCE_MASK 0x700
  50. #define APB_DMA_DEST_MASK 0x7000
  51. /*
  52. * 000: No increment
  53. * 001: +1 (Burst=0), +4 (Burst=1)
  54. * 010: +2 (Burst=0), +8 (Burst=1)
  55. * 011: +4 (Burst=0), +16 (Burst=1)
  56. * 101: -1 (Burst=0), -4 (Burst=1)
  57. * 110: -2 (Burst=0), -8 (Burst=1)
  58. * 111: -4 (Burst=0), -16 (Burst=1)
  59. */
  60. #define APB_DMA_SOURCE_INC_0 0
  61. #define APB_DMA_SOURCE_INC_1_4 0x100
  62. #define APB_DMA_SOURCE_INC_2_8 0x200
  63. #define APB_DMA_SOURCE_INC_4_16 0x300
  64. #define APB_DMA_SOURCE_DEC_1_4 0x500
  65. #define APB_DMA_SOURCE_DEC_2_8 0x600
  66. #define APB_DMA_SOURCE_DEC_4_16 0x700
  67. #define APB_DMA_DEST_INC_0 0
  68. #define APB_DMA_DEST_INC_1_4 0x1000
  69. #define APB_DMA_DEST_INC_2_8 0x2000
  70. #define APB_DMA_DEST_INC_4_16 0x3000
  71. #define APB_DMA_DEST_DEC_1_4 0x5000
  72. #define APB_DMA_DEST_DEC_2_8 0x6000
  73. #define APB_DMA_DEST_DEC_4_16 0x7000
  74. /*
  75. * Request signal select source/destination address for DMA hardware handshake.
  76. *
  77. * The request line number is a property of the DMA controller itself,
  78. * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
  79. *
  80. * 0: No request / Grant signal
  81. * 1-15: Request / Grant signal
  82. */
  83. #define APB_DMA_SOURCE_REQ_NO 0x1000000
  84. #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000
  85. #define APB_DMA_DEST_REQ_NO 0x10000
  86. #define APB_DMA_DEST_REQ_NO_MASK 0xf0000
  87. #define APB_DMA_DATA_WIDTH 0x100000
  88. #define APB_DMA_DATA_WIDTH_MASK 0x300000
  89. /*
  90. * Data width of transfer:
  91. *
  92. * 00: Word
  93. * 01: Half
  94. * 10: Byte
  95. */
  96. #define APB_DMA_DATA_WIDTH_4 0
  97. #define APB_DMA_DATA_WIDTH_2 0x100000
  98. #define APB_DMA_DATA_WIDTH_1 0x200000
  99. #define APB_DMA_CYCLES_MASK 0x00ffffff
  100. #define MOXART_DMA_DATA_TYPE_S8 0x00
  101. #define MOXART_DMA_DATA_TYPE_S16 0x01
  102. #define MOXART_DMA_DATA_TYPE_S32 0x02
  103. struct moxart_sg {
  104. dma_addr_t addr;
  105. uint32_t len;
  106. };
  107. struct moxart_desc {
  108. enum dma_transfer_direction dma_dir;
  109. dma_addr_t dev_addr;
  110. unsigned int sglen;
  111. unsigned int dma_cycles;
  112. struct virt_dma_desc vd;
  113. uint8_t es;
  114. struct moxart_sg sg[];
  115. };
  116. struct moxart_chan {
  117. struct virt_dma_chan vc;
  118. void __iomem *base;
  119. struct moxart_desc *desc;
  120. struct dma_slave_config cfg;
  121. bool allocated;
  122. bool error;
  123. int ch_num;
  124. unsigned int line_reqno;
  125. unsigned int sgidx;
  126. };
  127. struct moxart_dmadev {
  128. struct dma_device dma_slave;
  129. struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL];
  130. unsigned int irq;
  131. };
  132. struct moxart_filter_data {
  133. struct moxart_dmadev *mdc;
  134. struct of_phandle_args *dma_spec;
  135. };
  136. static const unsigned int es_bytes[] = {
  137. [MOXART_DMA_DATA_TYPE_S8] = 1,
  138. [MOXART_DMA_DATA_TYPE_S16] = 2,
  139. [MOXART_DMA_DATA_TYPE_S32] = 4,
  140. };
  141. static struct device *chan2dev(struct dma_chan *chan)
  142. {
  143. return &chan->dev->device;
  144. }
  145. static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
  146. {
  147. return container_of(c, struct moxart_chan, vc.chan);
  148. }
  149. static inline struct moxart_desc *to_moxart_dma_desc(
  150. struct dma_async_tx_descriptor *t)
  151. {
  152. return container_of(t, struct moxart_desc, vd.tx);
  153. }
  154. static void moxart_dma_desc_free(struct virt_dma_desc *vd)
  155. {
  156. kfree(container_of(vd, struct moxart_desc, vd));
  157. }
  158. static int moxart_terminate_all(struct dma_chan *chan)
  159. {
  160. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  161. unsigned long flags;
  162. LIST_HEAD(head);
  163. u32 ctrl;
  164. dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
  165. spin_lock_irqsave(&ch->vc.lock, flags);
  166. if (ch->desc) {
  167. moxart_dma_desc_free(&ch->desc->vd);
  168. ch->desc = NULL;
  169. }
  170. ctrl = readl(ch->base + REG_OFF_CTRL);
  171. ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
  172. writel(ctrl, ch->base + REG_OFF_CTRL);
  173. vchan_get_all_descriptors(&ch->vc, &head);
  174. spin_unlock_irqrestore(&ch->vc.lock, flags);
  175. vchan_dma_desc_free_list(&ch->vc, &head);
  176. return 0;
  177. }
  178. static int moxart_slave_config(struct dma_chan *chan,
  179. struct dma_slave_config *cfg)
  180. {
  181. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  182. u32 ctrl;
  183. ch->cfg = *cfg;
  184. ctrl = readl(ch->base + REG_OFF_CTRL);
  185. ctrl |= APB_DMA_BURST_MODE;
  186. ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
  187. ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
  188. switch (ch->cfg.src_addr_width) {
  189. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  190. ctrl |= APB_DMA_DATA_WIDTH_1;
  191. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  192. ctrl |= APB_DMA_DEST_INC_1_4;
  193. else
  194. ctrl |= APB_DMA_SOURCE_INC_1_4;
  195. break;
  196. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  197. ctrl |= APB_DMA_DATA_WIDTH_2;
  198. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  199. ctrl |= APB_DMA_DEST_INC_2_8;
  200. else
  201. ctrl |= APB_DMA_SOURCE_INC_2_8;
  202. break;
  203. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  204. ctrl &= ~APB_DMA_DATA_WIDTH;
  205. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  206. ctrl |= APB_DMA_DEST_INC_4_16;
  207. else
  208. ctrl |= APB_DMA_SOURCE_INC_4_16;
  209. break;
  210. default:
  211. return -EINVAL;
  212. }
  213. if (ch->cfg.direction == DMA_MEM_TO_DEV) {
  214. ctrl &= ~APB_DMA_DEST_SELECT;
  215. ctrl |= APB_DMA_SOURCE_SELECT;
  216. ctrl |= (ch->line_reqno << 16 &
  217. APB_DMA_DEST_REQ_NO_MASK);
  218. } else {
  219. ctrl |= APB_DMA_DEST_SELECT;
  220. ctrl &= ~APB_DMA_SOURCE_SELECT;
  221. ctrl |= (ch->line_reqno << 24 &
  222. APB_DMA_SOURCE_REQ_NO_MASK);
  223. }
  224. writel(ctrl, ch->base + REG_OFF_CTRL);
  225. return 0;
  226. }
  227. static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
  228. struct dma_chan *chan, struct scatterlist *sgl,
  229. unsigned int sg_len, enum dma_transfer_direction dir,
  230. unsigned long tx_flags, void *context)
  231. {
  232. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  233. struct moxart_desc *d;
  234. enum dma_slave_buswidth dev_width;
  235. dma_addr_t dev_addr;
  236. struct scatterlist *sgent;
  237. unsigned int es;
  238. unsigned int i;
  239. if (!is_slave_direction(dir)) {
  240. dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
  241. __func__);
  242. return NULL;
  243. }
  244. if (dir == DMA_DEV_TO_MEM) {
  245. dev_addr = ch->cfg.src_addr;
  246. dev_width = ch->cfg.src_addr_width;
  247. } else {
  248. dev_addr = ch->cfg.dst_addr;
  249. dev_width = ch->cfg.dst_addr_width;
  250. }
  251. switch (dev_width) {
  252. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  253. es = MOXART_DMA_DATA_TYPE_S8;
  254. break;
  255. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  256. es = MOXART_DMA_DATA_TYPE_S16;
  257. break;
  258. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  259. es = MOXART_DMA_DATA_TYPE_S32;
  260. break;
  261. default:
  262. dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
  263. __func__, dev_width);
  264. return NULL;
  265. }
  266. d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC);
  267. if (!d)
  268. return NULL;
  269. d->dma_dir = dir;
  270. d->dev_addr = dev_addr;
  271. d->es = es;
  272. for_each_sg(sgl, sgent, sg_len, i) {
  273. d->sg[i].addr = sg_dma_address(sgent);
  274. d->sg[i].len = sg_dma_len(sgent);
  275. }
  276. d->sglen = sg_len;
  277. ch->error = 0;
  278. return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
  279. }
  280. static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
  281. struct of_dma *ofdma)
  282. {
  283. struct moxart_dmadev *mdc = ofdma->of_dma_data;
  284. struct dma_chan *chan;
  285. struct moxart_chan *ch;
  286. chan = dma_get_any_slave_channel(&mdc->dma_slave);
  287. if (!chan)
  288. return NULL;
  289. ch = to_moxart_dma_chan(chan);
  290. ch->line_reqno = dma_spec->args[0];
  291. return chan;
  292. }
  293. static int moxart_alloc_chan_resources(struct dma_chan *chan)
  294. {
  295. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  296. dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
  297. __func__, ch->ch_num);
  298. ch->allocated = 1;
  299. return 0;
  300. }
  301. static void moxart_free_chan_resources(struct dma_chan *chan)
  302. {
  303. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  304. vchan_free_chan_resources(&ch->vc);
  305. dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
  306. __func__, ch->ch_num);
  307. ch->allocated = 0;
  308. }
  309. static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
  310. dma_addr_t dst_addr)
  311. {
  312. writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
  313. writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
  314. }
  315. static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
  316. {
  317. struct moxart_desc *d = ch->desc;
  318. unsigned int sglen_div = es_bytes[d->es];
  319. d->dma_cycles = len >> sglen_div;
  320. /*
  321. * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
  322. * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
  323. */
  324. writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
  325. dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
  326. __func__, d->dma_cycles, len);
  327. }
  328. static void moxart_start_dma(struct moxart_chan *ch)
  329. {
  330. u32 ctrl;
  331. ctrl = readl(ch->base + REG_OFF_CTRL);
  332. ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
  333. writel(ctrl, ch->base + REG_OFF_CTRL);
  334. }
  335. static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
  336. {
  337. struct moxart_desc *d = ch->desc;
  338. struct moxart_sg *sg = ch->desc->sg + idx;
  339. if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
  340. moxart_dma_set_params(ch, sg->addr, d->dev_addr);
  341. else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
  342. moxart_dma_set_params(ch, d->dev_addr, sg->addr);
  343. moxart_set_transfer_params(ch, sg->len);
  344. moxart_start_dma(ch);
  345. }
  346. static void moxart_dma_start_desc(struct dma_chan *chan)
  347. {
  348. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  349. struct virt_dma_desc *vd;
  350. vd = vchan_next_desc(&ch->vc);
  351. if (!vd) {
  352. ch->desc = NULL;
  353. return;
  354. }
  355. list_del(&vd->node);
  356. ch->desc = to_moxart_dma_desc(&vd->tx);
  357. ch->sgidx = 0;
  358. moxart_dma_start_sg(ch, 0);
  359. }
  360. static void moxart_issue_pending(struct dma_chan *chan)
  361. {
  362. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  363. unsigned long flags;
  364. spin_lock_irqsave(&ch->vc.lock, flags);
  365. if (vchan_issue_pending(&ch->vc) && !ch->desc)
  366. moxart_dma_start_desc(chan);
  367. spin_unlock_irqrestore(&ch->vc.lock, flags);
  368. }
  369. static size_t moxart_dma_desc_size(struct moxart_desc *d,
  370. unsigned int completed_sgs)
  371. {
  372. unsigned int i;
  373. size_t size;
  374. for (size = i = completed_sgs; i < d->sglen; i++)
  375. size += d->sg[i].len;
  376. return size;
  377. }
  378. static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
  379. {
  380. size_t size;
  381. unsigned int completed_cycles, cycles;
  382. size = moxart_dma_desc_size(ch->desc, ch->sgidx);
  383. cycles = readl(ch->base + REG_OFF_CYCLES);
  384. completed_cycles = (ch->desc->dma_cycles - cycles);
  385. size -= completed_cycles << es_bytes[ch->desc->es];
  386. dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
  387. return size;
  388. }
  389. static enum dma_status moxart_tx_status(struct dma_chan *chan,
  390. dma_cookie_t cookie,
  391. struct dma_tx_state *txstate)
  392. {
  393. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  394. struct virt_dma_desc *vd;
  395. struct moxart_desc *d;
  396. enum dma_status ret;
  397. unsigned long flags;
  398. /*
  399. * dma_cookie_status() assigns initial residue value.
  400. */
  401. ret = dma_cookie_status(chan, cookie, txstate);
  402. spin_lock_irqsave(&ch->vc.lock, flags);
  403. vd = vchan_find_desc(&ch->vc, cookie);
  404. if (vd) {
  405. d = to_moxart_dma_desc(&vd->tx);
  406. txstate->residue = moxart_dma_desc_size(d, 0);
  407. } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
  408. txstate->residue = moxart_dma_desc_size_in_flight(ch);
  409. }
  410. spin_unlock_irqrestore(&ch->vc.lock, flags);
  411. if (ch->error)
  412. return DMA_ERROR;
  413. return ret;
  414. }
  415. static void moxart_dma_init(struct dma_device *dma, struct device *dev)
  416. {
  417. dma->device_prep_slave_sg = moxart_prep_slave_sg;
  418. dma->device_alloc_chan_resources = moxart_alloc_chan_resources;
  419. dma->device_free_chan_resources = moxart_free_chan_resources;
  420. dma->device_issue_pending = moxart_issue_pending;
  421. dma->device_tx_status = moxart_tx_status;
  422. dma->device_config = moxart_slave_config;
  423. dma->device_terminate_all = moxart_terminate_all;
  424. dma->dev = dev;
  425. INIT_LIST_HEAD(&dma->channels);
  426. }
  427. static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
  428. {
  429. struct moxart_dmadev *mc = devid;
  430. struct moxart_chan *ch = &mc->slave_chans[0];
  431. unsigned int i;
  432. unsigned long flags;
  433. u32 ctrl;
  434. dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
  435. for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
  436. if (!ch->allocated)
  437. continue;
  438. ctrl = readl(ch->base + REG_OFF_CTRL);
  439. dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
  440. __func__, ch, ch->base, ctrl);
  441. if (ctrl & APB_DMA_FIN_INT_STS) {
  442. ctrl &= ~APB_DMA_FIN_INT_STS;
  443. if (ch->desc) {
  444. spin_lock_irqsave(&ch->vc.lock, flags);
  445. if (++ch->sgidx < ch->desc->sglen) {
  446. moxart_dma_start_sg(ch, ch->sgidx);
  447. } else {
  448. vchan_cookie_complete(&ch->desc->vd);
  449. moxart_dma_start_desc(&ch->vc.chan);
  450. }
  451. spin_unlock_irqrestore(&ch->vc.lock, flags);
  452. }
  453. }
  454. if (ctrl & APB_DMA_ERR_INT_STS) {
  455. ctrl &= ~APB_DMA_ERR_INT_STS;
  456. ch->error = 1;
  457. }
  458. writel(ctrl, ch->base + REG_OFF_CTRL);
  459. }
  460. return IRQ_HANDLED;
  461. }
  462. static int moxart_probe(struct platform_device *pdev)
  463. {
  464. struct device *dev = &pdev->dev;
  465. struct device_node *node = dev->of_node;
  466. struct resource *res;
  467. void __iomem *dma_base_addr;
  468. int ret, i;
  469. unsigned int irq;
  470. struct moxart_chan *ch;
  471. struct moxart_dmadev *mdc;
  472. mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
  473. if (!mdc)
  474. return -ENOMEM;
  475. irq = irq_of_parse_and_map(node, 0);
  476. if (!irq) {
  477. dev_err(dev, "no IRQ resource\n");
  478. return -EINVAL;
  479. }
  480. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  481. dma_base_addr = devm_ioremap_resource(dev, res);
  482. if (IS_ERR(dma_base_addr))
  483. return PTR_ERR(dma_base_addr);
  484. dma_cap_zero(mdc->dma_slave.cap_mask);
  485. dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
  486. dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
  487. moxart_dma_init(&mdc->dma_slave, dev);
  488. ch = &mdc->slave_chans[0];
  489. for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
  490. ch->ch_num = i;
  491. ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
  492. ch->allocated = 0;
  493. ch->vc.desc_free = moxart_dma_desc_free;
  494. vchan_init(&ch->vc, &mdc->dma_slave);
  495. dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
  496. __func__, i, ch->ch_num, ch->base);
  497. }
  498. platform_set_drvdata(pdev, mdc);
  499. ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
  500. "moxart-dma-engine", mdc);
  501. if (ret) {
  502. dev_err(dev, "devm_request_irq failed\n");
  503. return ret;
  504. }
  505. mdc->irq = irq;
  506. ret = dma_async_device_register(&mdc->dma_slave);
  507. if (ret) {
  508. dev_err(dev, "dma_async_device_register failed\n");
  509. return ret;
  510. }
  511. ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
  512. if (ret) {
  513. dev_err(dev, "of_dma_controller_register failed\n");
  514. dma_async_device_unregister(&mdc->dma_slave);
  515. return ret;
  516. }
  517. dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
  518. return 0;
  519. }
  520. static int moxart_remove(struct platform_device *pdev)
  521. {
  522. struct moxart_dmadev *m = platform_get_drvdata(pdev);
  523. devm_free_irq(&pdev->dev, m->irq, m);
  524. dma_async_device_unregister(&m->dma_slave);
  525. if (pdev->dev.of_node)
  526. of_dma_controller_free(pdev->dev.of_node);
  527. return 0;
  528. }
  529. static const struct of_device_id moxart_dma_match[] = {
  530. { .compatible = "moxa,moxart-dma" },
  531. { }
  532. };
  533. MODULE_DEVICE_TABLE(of, moxart_dma_match);
  534. static struct platform_driver moxart_driver = {
  535. .probe = moxart_probe,
  536. .remove = moxart_remove,
  537. .driver = {
  538. .name = "moxart-dma-engine",
  539. .of_match_table = moxart_dma_match,
  540. },
  541. };
  542. static int moxart_init(void)
  543. {
  544. return platform_driver_register(&moxart_driver);
  545. }
  546. subsys_initcall(moxart_init);
  547. static void __exit moxart_exit(void)
  548. {
  549. platform_driver_unregister(&moxart_driver);
  550. }
  551. module_exit(moxart_exit);
  552. MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
  553. MODULE_DESCRIPTION("MOXART DMA engine driver");
  554. MODULE_LICENSE("GPL v2");