mmp_tdma.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver For Marvell Two-channel DMA Engine
  4. *
  5. * Copyright: Marvell International Ltd.
  6. */
  7. #include <linux/err.h>
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/types.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/slab.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/device.h>
  17. #include <linux/platform_data/dma-mmp_tdma.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of_dma.h>
  20. #include "dmaengine.h"
  21. /*
  22. * Two-Channel DMA registers
  23. */
  24. #define TDBCR 0x00 /* Byte Count */
  25. #define TDSAR 0x10 /* Src Addr */
  26. #define TDDAR 0x20 /* Dst Addr */
  27. #define TDNDPR 0x30 /* Next Desc */
  28. #define TDCR 0x40 /* Control */
  29. #define TDCP 0x60 /* Priority*/
  30. #define TDCDPR 0x70 /* Current Desc */
  31. #define TDIMR 0x80 /* Int Mask */
  32. #define TDISR 0xa0 /* Int Status */
  33. /* Two-Channel DMA Control Register */
  34. #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
  35. #define TDCR_SSZ_12_BITS (0x1 << 22)
  36. #define TDCR_SSZ_16_BITS (0x2 << 22)
  37. #define TDCR_SSZ_20_BITS (0x3 << 22)
  38. #define TDCR_SSZ_24_BITS (0x4 << 22)
  39. #define TDCR_SSZ_32_BITS (0x5 << 22)
  40. #define TDCR_SSZ_SHIFT (0x1 << 22)
  41. #define TDCR_SSZ_MASK (0x7 << 22)
  42. #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
  43. #define TDCR_ABR (0x1 << 20) /* Channel Abort */
  44. #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
  45. #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
  46. #define TDCR_CHANACT (0x1 << 14) /* Channel Active */
  47. #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
  48. #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
  49. #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
  50. #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
  51. #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
  52. #define TDCR_BURSTSZ_4B (0x0 << 6)
  53. #define TDCR_BURSTSZ_8B (0x1 << 6)
  54. #define TDCR_BURSTSZ_16B (0x3 << 6)
  55. #define TDCR_BURSTSZ_32B (0x6 << 6)
  56. #define TDCR_BURSTSZ_64B (0x7 << 6)
  57. #define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
  58. #define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
  59. #define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
  60. #define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
  61. #define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
  62. #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
  63. #define TDCR_BURSTSZ_128B (0x5 << 6)
  64. #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
  65. #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
  66. #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
  67. #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
  68. #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
  69. #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
  70. #define TDCR_DSTDESCCONT (0x1 << 1)
  71. #define TDCR_SRCDESTCONT (0x1 << 0)
  72. /* Two-Channel DMA Int Mask Register */
  73. #define TDIMR_COMP (0x1 << 0)
  74. /* Two-Channel DMA Int Status Register */
  75. #define TDISR_COMP (0x1 << 0)
  76. /*
  77. * Two-Channel DMA Descriptor Struct
  78. * NOTE: desc's buf must be aligned to 16 bytes.
  79. */
  80. struct mmp_tdma_desc {
  81. u32 byte_cnt;
  82. u32 src_addr;
  83. u32 dst_addr;
  84. u32 nxt_desc;
  85. };
  86. enum mmp_tdma_type {
  87. MMP_AUD_TDMA = 0,
  88. PXA910_SQU,
  89. };
  90. #define TDMA_MAX_XFER_BYTES SZ_64K
  91. struct mmp_tdma_chan {
  92. struct device *dev;
  93. struct dma_chan chan;
  94. struct dma_async_tx_descriptor desc;
  95. struct tasklet_struct tasklet;
  96. struct mmp_tdma_desc *desc_arr;
  97. dma_addr_t desc_arr_phys;
  98. int desc_num;
  99. enum dma_transfer_direction dir;
  100. dma_addr_t dev_addr;
  101. u32 burst_sz;
  102. enum dma_slave_buswidth buswidth;
  103. enum dma_status status;
  104. struct dma_slave_config slave_config;
  105. int idx;
  106. enum mmp_tdma_type type;
  107. int irq;
  108. void __iomem *reg_base;
  109. size_t buf_len;
  110. size_t period_len;
  111. size_t pos;
  112. struct gen_pool *pool;
  113. };
  114. #define TDMA_CHANNEL_NUM 2
  115. struct mmp_tdma_device {
  116. struct device *dev;
  117. void __iomem *base;
  118. struct dma_device device;
  119. struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
  120. };
  121. #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
  122. static int mmp_tdma_config_write(struct dma_chan *chan,
  123. enum dma_transfer_direction dir,
  124. struct dma_slave_config *dmaengine_cfg);
  125. static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
  126. {
  127. writel(phys, tdmac->reg_base + TDNDPR);
  128. writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
  129. tdmac->reg_base + TDCR);
  130. }
  131. static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
  132. {
  133. if (enable)
  134. writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
  135. else
  136. writel(0, tdmac->reg_base + TDIMR);
  137. }
  138. static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
  139. {
  140. /* enable dma chan */
  141. writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
  142. tdmac->reg_base + TDCR);
  143. tdmac->status = DMA_IN_PROGRESS;
  144. }
  145. static int mmp_tdma_disable_chan(struct dma_chan *chan)
  146. {
  147. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  148. u32 tdcr;
  149. tdcr = readl(tdmac->reg_base + TDCR);
  150. tdcr |= TDCR_ABR;
  151. tdcr &= ~TDCR_CHANEN;
  152. writel(tdcr, tdmac->reg_base + TDCR);
  153. tdmac->status = DMA_COMPLETE;
  154. return 0;
  155. }
  156. static int mmp_tdma_resume_chan(struct dma_chan *chan)
  157. {
  158. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  159. writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
  160. tdmac->reg_base + TDCR);
  161. tdmac->status = DMA_IN_PROGRESS;
  162. return 0;
  163. }
  164. static int mmp_tdma_pause_chan(struct dma_chan *chan)
  165. {
  166. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  167. writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
  168. tdmac->reg_base + TDCR);
  169. tdmac->status = DMA_PAUSED;
  170. return 0;
  171. }
  172. static int mmp_tdma_config_chan(struct dma_chan *chan)
  173. {
  174. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  175. unsigned int tdcr = 0;
  176. mmp_tdma_disable_chan(chan);
  177. if (tdmac->dir == DMA_MEM_TO_DEV)
  178. tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
  179. else if (tdmac->dir == DMA_DEV_TO_MEM)
  180. tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
  181. if (tdmac->type == MMP_AUD_TDMA) {
  182. tdcr |= TDCR_PACKMOD;
  183. switch (tdmac->burst_sz) {
  184. case 4:
  185. tdcr |= TDCR_BURSTSZ_4B;
  186. break;
  187. case 8:
  188. tdcr |= TDCR_BURSTSZ_8B;
  189. break;
  190. case 16:
  191. tdcr |= TDCR_BURSTSZ_16B;
  192. break;
  193. case 32:
  194. tdcr |= TDCR_BURSTSZ_32B;
  195. break;
  196. case 64:
  197. tdcr |= TDCR_BURSTSZ_64B;
  198. break;
  199. case 128:
  200. tdcr |= TDCR_BURSTSZ_128B;
  201. break;
  202. default:
  203. dev_err(tdmac->dev, "unknown burst size.\n");
  204. return -EINVAL;
  205. }
  206. switch (tdmac->buswidth) {
  207. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  208. tdcr |= TDCR_SSZ_8_BITS;
  209. break;
  210. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  211. tdcr |= TDCR_SSZ_16_BITS;
  212. break;
  213. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  214. tdcr |= TDCR_SSZ_32_BITS;
  215. break;
  216. default:
  217. dev_err(tdmac->dev, "unknown bus size.\n");
  218. return -EINVAL;
  219. }
  220. } else if (tdmac->type == PXA910_SQU) {
  221. tdcr |= TDCR_SSPMOD;
  222. switch (tdmac->burst_sz) {
  223. case 1:
  224. tdcr |= TDCR_BURSTSZ_SQU_1B;
  225. break;
  226. case 2:
  227. tdcr |= TDCR_BURSTSZ_SQU_2B;
  228. break;
  229. case 4:
  230. tdcr |= TDCR_BURSTSZ_SQU_4B;
  231. break;
  232. case 8:
  233. tdcr |= TDCR_BURSTSZ_SQU_8B;
  234. break;
  235. case 16:
  236. tdcr |= TDCR_BURSTSZ_SQU_16B;
  237. break;
  238. case 32:
  239. tdcr |= TDCR_BURSTSZ_SQU_32B;
  240. break;
  241. default:
  242. dev_err(tdmac->dev, "unknown burst size.\n");
  243. return -EINVAL;
  244. }
  245. }
  246. writel(tdcr, tdmac->reg_base + TDCR);
  247. return 0;
  248. }
  249. static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
  250. {
  251. u32 reg = readl(tdmac->reg_base + TDISR);
  252. if (reg & TDISR_COMP) {
  253. /* clear irq */
  254. reg &= ~TDISR_COMP;
  255. writel(reg, tdmac->reg_base + TDISR);
  256. return 0;
  257. }
  258. return -EAGAIN;
  259. }
  260. static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac)
  261. {
  262. size_t reg;
  263. if (tdmac->idx == 0) {
  264. reg = __raw_readl(tdmac->reg_base + TDSAR);
  265. reg -= tdmac->desc_arr[0].src_addr;
  266. } else if (tdmac->idx == 1) {
  267. reg = __raw_readl(tdmac->reg_base + TDDAR);
  268. reg -= tdmac->desc_arr[0].dst_addr;
  269. } else
  270. return -EINVAL;
  271. return reg;
  272. }
  273. static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
  274. {
  275. struct mmp_tdma_chan *tdmac = dev_id;
  276. if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
  277. tasklet_schedule(&tdmac->tasklet);
  278. return IRQ_HANDLED;
  279. } else
  280. return IRQ_NONE;
  281. }
  282. static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
  283. {
  284. struct mmp_tdma_device *tdev = dev_id;
  285. int i, ret;
  286. int irq_num = 0;
  287. for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
  288. struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
  289. ret = mmp_tdma_chan_handler(irq, tdmac);
  290. if (ret == IRQ_HANDLED)
  291. irq_num++;
  292. }
  293. if (irq_num)
  294. return IRQ_HANDLED;
  295. else
  296. return IRQ_NONE;
  297. }
  298. static void dma_do_tasklet(struct tasklet_struct *t)
  299. {
  300. struct mmp_tdma_chan *tdmac = from_tasklet(tdmac, t, tasklet);
  301. dmaengine_desc_get_callback_invoke(&tdmac->desc, NULL);
  302. }
  303. static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
  304. {
  305. struct gen_pool *gpool;
  306. int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
  307. gpool = tdmac->pool;
  308. if (gpool && tdmac->desc_arr)
  309. gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
  310. size);
  311. tdmac->desc_arr = NULL;
  312. if (tdmac->status == DMA_ERROR)
  313. tdmac->status = DMA_COMPLETE;
  314. return;
  315. }
  316. static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
  317. {
  318. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
  319. mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
  320. return 0;
  321. }
  322. static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
  323. {
  324. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  325. int ret;
  326. dma_async_tx_descriptor_init(&tdmac->desc, chan);
  327. tdmac->desc.tx_submit = mmp_tdma_tx_submit;
  328. if (tdmac->irq) {
  329. ret = devm_request_irq(tdmac->dev, tdmac->irq,
  330. mmp_tdma_chan_handler, 0, "tdma", tdmac);
  331. if (ret)
  332. return ret;
  333. }
  334. return 1;
  335. }
  336. static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
  337. {
  338. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  339. if (tdmac->irq)
  340. devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
  341. mmp_tdma_free_descriptor(tdmac);
  342. return;
  343. }
  344. static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
  345. {
  346. struct gen_pool *gpool;
  347. int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
  348. gpool = tdmac->pool;
  349. if (!gpool)
  350. return NULL;
  351. tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
  352. return tdmac->desc_arr;
  353. }
  354. static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
  355. struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
  356. size_t period_len, enum dma_transfer_direction direction,
  357. unsigned long flags)
  358. {
  359. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  360. struct mmp_tdma_desc *desc;
  361. int num_periods = buf_len / period_len;
  362. int i = 0, buf = 0;
  363. if (!is_slave_direction(direction)) {
  364. dev_err(tdmac->dev, "unsupported transfer direction\n");
  365. return NULL;
  366. }
  367. if (tdmac->status != DMA_COMPLETE) {
  368. dev_err(tdmac->dev, "controller busy");
  369. return NULL;
  370. }
  371. if (period_len > TDMA_MAX_XFER_BYTES) {
  372. dev_err(tdmac->dev,
  373. "maximum period size exceeded: %zu > %d\n",
  374. period_len, TDMA_MAX_XFER_BYTES);
  375. goto err_out;
  376. }
  377. tdmac->status = DMA_IN_PROGRESS;
  378. tdmac->desc_num = num_periods;
  379. desc = mmp_tdma_alloc_descriptor(tdmac);
  380. if (!desc)
  381. goto err_out;
  382. if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
  383. goto err_out;
  384. while (buf < buf_len) {
  385. desc = &tdmac->desc_arr[i];
  386. if (i + 1 == num_periods)
  387. desc->nxt_desc = tdmac->desc_arr_phys;
  388. else
  389. desc->nxt_desc = tdmac->desc_arr_phys +
  390. sizeof(*desc) * (i + 1);
  391. if (direction == DMA_MEM_TO_DEV) {
  392. desc->src_addr = dma_addr;
  393. desc->dst_addr = tdmac->dev_addr;
  394. } else {
  395. desc->src_addr = tdmac->dev_addr;
  396. desc->dst_addr = dma_addr;
  397. }
  398. desc->byte_cnt = period_len;
  399. dma_addr += period_len;
  400. buf += period_len;
  401. i++;
  402. }
  403. /* enable interrupt */
  404. if (flags & DMA_PREP_INTERRUPT)
  405. mmp_tdma_enable_irq(tdmac, true);
  406. tdmac->buf_len = buf_len;
  407. tdmac->period_len = period_len;
  408. tdmac->pos = 0;
  409. return &tdmac->desc;
  410. err_out:
  411. tdmac->status = DMA_ERROR;
  412. return NULL;
  413. }
  414. static int mmp_tdma_terminate_all(struct dma_chan *chan)
  415. {
  416. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  417. mmp_tdma_disable_chan(chan);
  418. /* disable interrupt */
  419. mmp_tdma_enable_irq(tdmac, false);
  420. return 0;
  421. }
  422. static int mmp_tdma_config(struct dma_chan *chan,
  423. struct dma_slave_config *dmaengine_cfg)
  424. {
  425. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  426. memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
  427. return 0;
  428. }
  429. static int mmp_tdma_config_write(struct dma_chan *chan,
  430. enum dma_transfer_direction dir,
  431. struct dma_slave_config *dmaengine_cfg)
  432. {
  433. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  434. if (dir == DMA_DEV_TO_MEM) {
  435. tdmac->dev_addr = dmaengine_cfg->src_addr;
  436. tdmac->burst_sz = dmaengine_cfg->src_maxburst;
  437. tdmac->buswidth = dmaengine_cfg->src_addr_width;
  438. } else {
  439. tdmac->dev_addr = dmaengine_cfg->dst_addr;
  440. tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
  441. tdmac->buswidth = dmaengine_cfg->dst_addr_width;
  442. }
  443. tdmac->dir = dir;
  444. return mmp_tdma_config_chan(chan);
  445. }
  446. static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
  447. dma_cookie_t cookie, struct dma_tx_state *txstate)
  448. {
  449. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  450. tdmac->pos = mmp_tdma_get_pos(tdmac);
  451. dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
  452. tdmac->buf_len - tdmac->pos);
  453. return tdmac->status;
  454. }
  455. static void mmp_tdma_issue_pending(struct dma_chan *chan)
  456. {
  457. struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
  458. mmp_tdma_enable_chan(tdmac);
  459. }
  460. static int mmp_tdma_remove(struct platform_device *pdev)
  461. {
  462. if (pdev->dev.of_node)
  463. of_dma_controller_free(pdev->dev.of_node);
  464. return 0;
  465. }
  466. static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
  467. int idx, int irq,
  468. int type, struct gen_pool *pool)
  469. {
  470. struct mmp_tdma_chan *tdmac;
  471. if (idx >= TDMA_CHANNEL_NUM) {
  472. dev_err(tdev->dev, "too many channels for device!\n");
  473. return -EINVAL;
  474. }
  475. /* alloc channel */
  476. tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
  477. if (!tdmac)
  478. return -ENOMEM;
  479. if (irq)
  480. tdmac->irq = irq;
  481. tdmac->dev = tdev->dev;
  482. tdmac->chan.device = &tdev->device;
  483. tdmac->idx = idx;
  484. tdmac->type = type;
  485. tdmac->reg_base = tdev->base + idx * 4;
  486. tdmac->pool = pool;
  487. tdmac->status = DMA_COMPLETE;
  488. tdev->tdmac[tdmac->idx] = tdmac;
  489. tasklet_setup(&tdmac->tasklet, dma_do_tasklet);
  490. /* add the channel to tdma_chan list */
  491. list_add_tail(&tdmac->chan.device_node,
  492. &tdev->device.channels);
  493. return 0;
  494. }
  495. struct mmp_tdma_filter_param {
  496. unsigned int chan_id;
  497. };
  498. static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
  499. {
  500. struct mmp_tdma_filter_param *param = fn_param;
  501. if (chan->chan_id != param->chan_id)
  502. return false;
  503. return true;
  504. }
  505. static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
  506. struct of_dma *ofdma)
  507. {
  508. struct mmp_tdma_device *tdev = ofdma->of_dma_data;
  509. dma_cap_mask_t mask = tdev->device.cap_mask;
  510. struct mmp_tdma_filter_param param;
  511. if (dma_spec->args_count != 1)
  512. return NULL;
  513. param.chan_id = dma_spec->args[0];
  514. if (param.chan_id >= TDMA_CHANNEL_NUM)
  515. return NULL;
  516. return __dma_request_channel(&mask, mmp_tdma_filter_fn, &param,
  517. ofdma->of_node);
  518. }
  519. static const struct of_device_id mmp_tdma_dt_ids[] = {
  520. { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
  521. { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
  522. {}
  523. };
  524. MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
  525. static int mmp_tdma_probe(struct platform_device *pdev)
  526. {
  527. enum mmp_tdma_type type;
  528. const struct of_device_id *of_id;
  529. struct mmp_tdma_device *tdev;
  530. struct resource *iores;
  531. int i, ret;
  532. int irq = 0, irq_num = 0;
  533. int chan_num = TDMA_CHANNEL_NUM;
  534. struct gen_pool *pool = NULL;
  535. of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
  536. if (of_id)
  537. type = (enum mmp_tdma_type) of_id->data;
  538. else
  539. type = platform_get_device_id(pdev)->driver_data;
  540. /* always have couple channels */
  541. tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
  542. if (!tdev)
  543. return -ENOMEM;
  544. tdev->dev = &pdev->dev;
  545. for (i = 0; i < chan_num; i++) {
  546. if (platform_get_irq(pdev, i) > 0)
  547. irq_num++;
  548. }
  549. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  550. tdev->base = devm_ioremap_resource(&pdev->dev, iores);
  551. if (IS_ERR(tdev->base))
  552. return PTR_ERR(tdev->base);
  553. INIT_LIST_HEAD(&tdev->device.channels);
  554. if (pdev->dev.of_node)
  555. pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0);
  556. else
  557. pool = sram_get_gpool("asram");
  558. if (!pool) {
  559. dev_err(&pdev->dev, "asram pool not available\n");
  560. return -ENOMEM;
  561. }
  562. if (irq_num != chan_num) {
  563. irq = platform_get_irq(pdev, 0);
  564. ret = devm_request_irq(&pdev->dev, irq,
  565. mmp_tdma_int_handler, IRQF_SHARED, "tdma", tdev);
  566. if (ret)
  567. return ret;
  568. }
  569. /* initialize channel parameters */
  570. for (i = 0; i < chan_num; i++) {
  571. irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
  572. ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
  573. if (ret)
  574. return ret;
  575. }
  576. dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
  577. dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
  578. tdev->device.dev = &pdev->dev;
  579. tdev->device.device_alloc_chan_resources =
  580. mmp_tdma_alloc_chan_resources;
  581. tdev->device.device_free_chan_resources =
  582. mmp_tdma_free_chan_resources;
  583. tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
  584. tdev->device.device_tx_status = mmp_tdma_tx_status;
  585. tdev->device.device_issue_pending = mmp_tdma_issue_pending;
  586. tdev->device.device_config = mmp_tdma_config;
  587. tdev->device.device_pause = mmp_tdma_pause_chan;
  588. tdev->device.device_resume = mmp_tdma_resume_chan;
  589. tdev->device.device_terminate_all = mmp_tdma_terminate_all;
  590. tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
  591. tdev->device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  592. if (type == MMP_AUD_TDMA) {
  593. tdev->device.max_burst = SZ_128;
  594. tdev->device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  595. tdev->device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  596. } else if (type == PXA910_SQU) {
  597. tdev->device.max_burst = SZ_32;
  598. }
  599. tdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  600. tdev->device.descriptor_reuse = true;
  601. dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
  602. platform_set_drvdata(pdev, tdev);
  603. ret = dmaenginem_async_device_register(&tdev->device);
  604. if (ret) {
  605. dev_err(tdev->device.dev, "unable to register\n");
  606. return ret;
  607. }
  608. if (pdev->dev.of_node) {
  609. ret = of_dma_controller_register(pdev->dev.of_node,
  610. mmp_tdma_xlate, tdev);
  611. if (ret) {
  612. dev_err(tdev->device.dev,
  613. "failed to register controller\n");
  614. return ret;
  615. }
  616. }
  617. dev_info(tdev->device.dev, "initialized\n");
  618. return 0;
  619. }
  620. static const struct platform_device_id mmp_tdma_id_table[] = {
  621. { "mmp-adma", MMP_AUD_TDMA },
  622. { "pxa910-squ", PXA910_SQU },
  623. { },
  624. };
  625. static struct platform_driver mmp_tdma_driver = {
  626. .driver = {
  627. .name = "mmp-tdma",
  628. .of_match_table = mmp_tdma_dt_ids,
  629. },
  630. .id_table = mmp_tdma_id_table,
  631. .probe = mmp_tdma_probe,
  632. .remove = mmp_tdma_remove,
  633. };
  634. module_platform_driver(mmp_tdma_driver);
  635. MODULE_LICENSE("GPL");
  636. MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
  637. MODULE_ALIAS("platform:mmp-tdma");
  638. MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
  639. MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");