milbeaut-xdmac.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2019 Linaro Ltd.
  4. // Copyright (C) 2019 Socionext Inc.
  5. #include <linux/bits.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/dmaengine.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_dma.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/bitfield.h>
  17. #include "virt-dma.h"
  18. /* global register */
  19. #define M10V_XDACS 0x00
  20. /* channel local register */
  21. #define M10V_XDTBC 0x10
  22. #define M10V_XDSSA 0x14
  23. #define M10V_XDDSA 0x18
  24. #define M10V_XDSAC 0x1C
  25. #define M10V_XDDAC 0x20
  26. #define M10V_XDDCC 0x24
  27. #define M10V_XDDES 0x28
  28. #define M10V_XDDPC 0x2C
  29. #define M10V_XDDSD 0x30
  30. #define M10V_XDACS_XE BIT(28)
  31. #define M10V_DEFBS 0x3
  32. #define M10V_DEFBL 0xf
  33. #define M10V_XDSAC_SBS GENMASK(17, 16)
  34. #define M10V_XDSAC_SBL GENMASK(11, 8)
  35. #define M10V_XDDAC_DBS GENMASK(17, 16)
  36. #define M10V_XDDAC_DBL GENMASK(11, 8)
  37. #define M10V_XDDES_CE BIT(28)
  38. #define M10V_XDDES_SE BIT(24)
  39. #define M10V_XDDES_SA BIT(15)
  40. #define M10V_XDDES_TF GENMASK(23, 20)
  41. #define M10V_XDDES_EI BIT(1)
  42. #define M10V_XDDES_TI BIT(0)
  43. #define M10V_XDDSD_IS_MASK GENMASK(3, 0)
  44. #define M10V_XDDSD_IS_NORMAL 0x8
  45. #define MLB_XDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  46. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  47. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  48. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  49. struct milbeaut_xdmac_desc {
  50. struct virt_dma_desc vd;
  51. size_t len;
  52. dma_addr_t src;
  53. dma_addr_t dst;
  54. };
  55. struct milbeaut_xdmac_chan {
  56. struct virt_dma_chan vc;
  57. struct milbeaut_xdmac_desc *md;
  58. void __iomem *reg_ch_base;
  59. };
  60. struct milbeaut_xdmac_device {
  61. struct dma_device ddev;
  62. void __iomem *reg_base;
  63. struct milbeaut_xdmac_chan channels[];
  64. };
  65. static struct milbeaut_xdmac_chan *
  66. to_milbeaut_xdmac_chan(struct virt_dma_chan *vc)
  67. {
  68. return container_of(vc, struct milbeaut_xdmac_chan, vc);
  69. }
  70. static struct milbeaut_xdmac_desc *
  71. to_milbeaut_xdmac_desc(struct virt_dma_desc *vd)
  72. {
  73. return container_of(vd, struct milbeaut_xdmac_desc, vd);
  74. }
  75. /* mc->vc.lock must be held by caller */
  76. static struct milbeaut_xdmac_desc *
  77. milbeaut_xdmac_next_desc(struct milbeaut_xdmac_chan *mc)
  78. {
  79. struct virt_dma_desc *vd;
  80. vd = vchan_next_desc(&mc->vc);
  81. if (!vd) {
  82. mc->md = NULL;
  83. return NULL;
  84. }
  85. list_del(&vd->node);
  86. mc->md = to_milbeaut_xdmac_desc(vd);
  87. return mc->md;
  88. }
  89. /* mc->vc.lock must be held by caller */
  90. static void milbeaut_chan_start(struct milbeaut_xdmac_chan *mc,
  91. struct milbeaut_xdmac_desc *md)
  92. {
  93. u32 val;
  94. /* Setup the channel */
  95. val = md->len - 1;
  96. writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC);
  97. val = md->src;
  98. writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA);
  99. val = md->dst;
  100. writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA);
  101. val = readl_relaxed(mc->reg_ch_base + M10V_XDSAC);
  102. val &= ~(M10V_XDSAC_SBS | M10V_XDSAC_SBL);
  103. val |= FIELD_PREP(M10V_XDSAC_SBS, M10V_DEFBS) |
  104. FIELD_PREP(M10V_XDSAC_SBL, M10V_DEFBL);
  105. writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC);
  106. val = readl_relaxed(mc->reg_ch_base + M10V_XDDAC);
  107. val &= ~(M10V_XDDAC_DBS | M10V_XDDAC_DBL);
  108. val |= FIELD_PREP(M10V_XDDAC_DBS, M10V_DEFBS) |
  109. FIELD_PREP(M10V_XDDAC_DBL, M10V_DEFBL);
  110. writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC);
  111. /* Start the channel */
  112. val = readl_relaxed(mc->reg_ch_base + M10V_XDDES);
  113. val &= ~(M10V_XDDES_CE | M10V_XDDES_SE | M10V_XDDES_TF |
  114. M10V_XDDES_EI | M10V_XDDES_TI);
  115. val |= FIELD_PREP(M10V_XDDES_CE, 1) | FIELD_PREP(M10V_XDDES_SE, 1) |
  116. FIELD_PREP(M10V_XDDES_TF, 1) | FIELD_PREP(M10V_XDDES_EI, 1) |
  117. FIELD_PREP(M10V_XDDES_TI, 1);
  118. writel_relaxed(val, mc->reg_ch_base + M10V_XDDES);
  119. }
  120. /* mc->vc.lock must be held by caller */
  121. static void milbeaut_xdmac_start(struct milbeaut_xdmac_chan *mc)
  122. {
  123. struct milbeaut_xdmac_desc *md;
  124. md = milbeaut_xdmac_next_desc(mc);
  125. if (md)
  126. milbeaut_chan_start(mc, md);
  127. }
  128. static irqreturn_t milbeaut_xdmac_interrupt(int irq, void *dev_id)
  129. {
  130. struct milbeaut_xdmac_chan *mc = dev_id;
  131. struct milbeaut_xdmac_desc *md;
  132. unsigned long flags;
  133. u32 val;
  134. spin_lock_irqsave(&mc->vc.lock, flags);
  135. /* Ack and Stop */
  136. val = FIELD_PREP(M10V_XDDSD_IS_MASK, 0x0);
  137. writel_relaxed(val, mc->reg_ch_base + M10V_XDDSD);
  138. md = mc->md;
  139. if (!md)
  140. goto out;
  141. vchan_cookie_complete(&md->vd);
  142. milbeaut_xdmac_start(mc);
  143. out:
  144. spin_unlock_irqrestore(&mc->vc.lock, flags);
  145. return IRQ_HANDLED;
  146. }
  147. static void milbeaut_xdmac_free_chan_resources(struct dma_chan *chan)
  148. {
  149. vchan_free_chan_resources(to_virt_chan(chan));
  150. }
  151. static struct dma_async_tx_descriptor *
  152. milbeaut_xdmac_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
  153. dma_addr_t src, size_t len, unsigned long flags)
  154. {
  155. struct virt_dma_chan *vc = to_virt_chan(chan);
  156. struct milbeaut_xdmac_desc *md;
  157. md = kzalloc(sizeof(*md), GFP_NOWAIT);
  158. if (!md)
  159. return NULL;
  160. md->len = len;
  161. md->src = src;
  162. md->dst = dst;
  163. return vchan_tx_prep(vc, &md->vd, flags);
  164. }
  165. static int milbeaut_xdmac_terminate_all(struct dma_chan *chan)
  166. {
  167. struct virt_dma_chan *vc = to_virt_chan(chan);
  168. struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
  169. unsigned long flags;
  170. u32 val;
  171. LIST_HEAD(head);
  172. spin_lock_irqsave(&vc->lock, flags);
  173. /* Halt the channel */
  174. val = readl(mc->reg_ch_base + M10V_XDDES);
  175. val &= ~M10V_XDDES_CE;
  176. val |= FIELD_PREP(M10V_XDDES_CE, 0);
  177. writel(val, mc->reg_ch_base + M10V_XDDES);
  178. if (mc->md) {
  179. vchan_terminate_vdesc(&mc->md->vd);
  180. mc->md = NULL;
  181. }
  182. vchan_get_all_descriptors(vc, &head);
  183. spin_unlock_irqrestore(&vc->lock, flags);
  184. vchan_dma_desc_free_list(vc, &head);
  185. return 0;
  186. }
  187. static void milbeaut_xdmac_synchronize(struct dma_chan *chan)
  188. {
  189. vchan_synchronize(to_virt_chan(chan));
  190. }
  191. static void milbeaut_xdmac_issue_pending(struct dma_chan *chan)
  192. {
  193. struct virt_dma_chan *vc = to_virt_chan(chan);
  194. struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
  195. unsigned long flags;
  196. spin_lock_irqsave(&vc->lock, flags);
  197. if (vchan_issue_pending(vc) && !mc->md)
  198. milbeaut_xdmac_start(mc);
  199. spin_unlock_irqrestore(&vc->lock, flags);
  200. }
  201. static void milbeaut_xdmac_desc_free(struct virt_dma_desc *vd)
  202. {
  203. kfree(to_milbeaut_xdmac_desc(vd));
  204. }
  205. static int milbeaut_xdmac_chan_init(struct platform_device *pdev,
  206. struct milbeaut_xdmac_device *mdev,
  207. int chan_id)
  208. {
  209. struct device *dev = &pdev->dev;
  210. struct milbeaut_xdmac_chan *mc = &mdev->channels[chan_id];
  211. char *irq_name;
  212. int irq, ret;
  213. irq = platform_get_irq(pdev, chan_id);
  214. if (irq < 0)
  215. return irq;
  216. irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-xdmac-%d",
  217. chan_id);
  218. if (!irq_name)
  219. return -ENOMEM;
  220. ret = devm_request_irq(dev, irq, milbeaut_xdmac_interrupt,
  221. IRQF_SHARED, irq_name, mc);
  222. if (ret)
  223. return ret;
  224. mc->reg_ch_base = mdev->reg_base + chan_id * 0x30;
  225. mc->vc.desc_free = milbeaut_xdmac_desc_free;
  226. vchan_init(&mc->vc, &mdev->ddev);
  227. return 0;
  228. }
  229. static void enable_xdmac(struct milbeaut_xdmac_device *mdev)
  230. {
  231. unsigned int val;
  232. val = readl(mdev->reg_base + M10V_XDACS);
  233. val |= M10V_XDACS_XE;
  234. writel(val, mdev->reg_base + M10V_XDACS);
  235. }
  236. static void disable_xdmac(struct milbeaut_xdmac_device *mdev)
  237. {
  238. unsigned int val;
  239. val = readl(mdev->reg_base + M10V_XDACS);
  240. val &= ~M10V_XDACS_XE;
  241. writel(val, mdev->reg_base + M10V_XDACS);
  242. }
  243. static int milbeaut_xdmac_probe(struct platform_device *pdev)
  244. {
  245. struct device *dev = &pdev->dev;
  246. struct milbeaut_xdmac_device *mdev;
  247. struct dma_device *ddev;
  248. int nr_chans, ret, i;
  249. nr_chans = platform_irq_count(pdev);
  250. if (nr_chans < 0)
  251. return nr_chans;
  252. mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
  253. GFP_KERNEL);
  254. if (!mdev)
  255. return -ENOMEM;
  256. mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
  257. if (IS_ERR(mdev->reg_base))
  258. return PTR_ERR(mdev->reg_base);
  259. ddev = &mdev->ddev;
  260. ddev->dev = dev;
  261. dma_cap_set(DMA_MEMCPY, ddev->cap_mask);
  262. ddev->src_addr_widths = MLB_XDMAC_BUSWIDTHS;
  263. ddev->dst_addr_widths = MLB_XDMAC_BUSWIDTHS;
  264. ddev->device_free_chan_resources = milbeaut_xdmac_free_chan_resources;
  265. ddev->device_prep_dma_memcpy = milbeaut_xdmac_prep_memcpy;
  266. ddev->device_terminate_all = milbeaut_xdmac_terminate_all;
  267. ddev->device_synchronize = milbeaut_xdmac_synchronize;
  268. ddev->device_tx_status = dma_cookie_status;
  269. ddev->device_issue_pending = milbeaut_xdmac_issue_pending;
  270. INIT_LIST_HEAD(&ddev->channels);
  271. for (i = 0; i < nr_chans; i++) {
  272. ret = milbeaut_xdmac_chan_init(pdev, mdev, i);
  273. if (ret)
  274. return ret;
  275. }
  276. enable_xdmac(mdev);
  277. ret = dma_async_device_register(ddev);
  278. if (ret)
  279. goto disable_xdmac;
  280. ret = of_dma_controller_register(dev->of_node,
  281. of_dma_simple_xlate, mdev);
  282. if (ret)
  283. goto unregister_dmac;
  284. platform_set_drvdata(pdev, mdev);
  285. return 0;
  286. unregister_dmac:
  287. dma_async_device_unregister(ddev);
  288. disable_xdmac:
  289. disable_xdmac(mdev);
  290. return ret;
  291. }
  292. static int milbeaut_xdmac_remove(struct platform_device *pdev)
  293. {
  294. struct milbeaut_xdmac_device *mdev = platform_get_drvdata(pdev);
  295. struct dma_chan *chan;
  296. int ret;
  297. /*
  298. * Before reaching here, almost all descriptors have been freed by the
  299. * ->device_free_chan_resources() hook. However, each channel might
  300. * be still holding one descriptor that was on-flight at that moment.
  301. * Terminate it to make sure this hardware is no longer running. Then,
  302. * free the channel resources once again to avoid memory leak.
  303. */
  304. list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
  305. ret = dmaengine_terminate_sync(chan);
  306. if (ret)
  307. return ret;
  308. milbeaut_xdmac_free_chan_resources(chan);
  309. }
  310. of_dma_controller_free(pdev->dev.of_node);
  311. dma_async_device_unregister(&mdev->ddev);
  312. disable_xdmac(mdev);
  313. return 0;
  314. }
  315. static const struct of_device_id milbeaut_xdmac_match[] = {
  316. { .compatible = "socionext,milbeaut-m10v-xdmac" },
  317. { /* sentinel */ }
  318. };
  319. MODULE_DEVICE_TABLE(of, milbeaut_xdmac_match);
  320. static struct platform_driver milbeaut_xdmac_driver = {
  321. .probe = milbeaut_xdmac_probe,
  322. .remove = milbeaut_xdmac_remove,
  323. .driver = {
  324. .name = "milbeaut-m10v-xdmac",
  325. .of_match_table = milbeaut_xdmac_match,
  326. },
  327. };
  328. module_platform_driver(milbeaut_xdmac_driver);
  329. MODULE_DESCRIPTION("Milbeaut XDMAC DmaEngine driver");
  330. MODULE_LICENSE("GPL v2");