milbeaut-hdmac.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2019 Linaro Ltd.
  4. // Copyright (C) 2019 Socionext Inc.
  5. #include <linux/bits.h>
  6. #include <linux/clk.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_dma.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/bitfield.h>
  17. #include "virt-dma.h"
  18. #define MLB_HDMAC_DMACR 0x0 /* global */
  19. #define MLB_HDMAC_DE BIT(31)
  20. #define MLB_HDMAC_DS BIT(30)
  21. #define MLB_HDMAC_PR BIT(28)
  22. #define MLB_HDMAC_DH GENMASK(27, 24)
  23. #define MLB_HDMAC_CH_STRIDE 0x10
  24. #define MLB_HDMAC_DMACA 0x0 /* channel */
  25. #define MLB_HDMAC_EB BIT(31)
  26. #define MLB_HDMAC_PB BIT(30)
  27. #define MLB_HDMAC_ST BIT(29)
  28. #define MLB_HDMAC_IS GENMASK(28, 24)
  29. #define MLB_HDMAC_BT GENMASK(23, 20)
  30. #define MLB_HDMAC_BC GENMASK(19, 16)
  31. #define MLB_HDMAC_TC GENMASK(15, 0)
  32. #define MLB_HDMAC_DMACB 0x4
  33. #define MLB_HDMAC_TT GENMASK(31, 30)
  34. #define MLB_HDMAC_MS GENMASK(29, 28)
  35. #define MLB_HDMAC_TW GENMASK(27, 26)
  36. #define MLB_HDMAC_FS BIT(25)
  37. #define MLB_HDMAC_FD BIT(24)
  38. #define MLB_HDMAC_RC BIT(23)
  39. #define MLB_HDMAC_RS BIT(22)
  40. #define MLB_HDMAC_RD BIT(21)
  41. #define MLB_HDMAC_EI BIT(20)
  42. #define MLB_HDMAC_CI BIT(19)
  43. #define HDMAC_PAUSE 0x7
  44. #define MLB_HDMAC_SS GENMASK(18, 16)
  45. #define MLB_HDMAC_SP GENMASK(15, 12)
  46. #define MLB_HDMAC_DP GENMASK(11, 8)
  47. #define MLB_HDMAC_DMACSA 0x8
  48. #define MLB_HDMAC_DMACDA 0xc
  49. #define MLB_HDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  50. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  51. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
  52. struct milbeaut_hdmac_desc {
  53. struct virt_dma_desc vd;
  54. struct scatterlist *sgl;
  55. unsigned int sg_len;
  56. unsigned int sg_cur;
  57. enum dma_transfer_direction dir;
  58. };
  59. struct milbeaut_hdmac_chan {
  60. struct virt_dma_chan vc;
  61. struct milbeaut_hdmac_device *mdev;
  62. struct milbeaut_hdmac_desc *md;
  63. void __iomem *reg_ch_base;
  64. unsigned int slave_id;
  65. struct dma_slave_config cfg;
  66. };
  67. struct milbeaut_hdmac_device {
  68. struct dma_device ddev;
  69. struct clk *clk;
  70. void __iomem *reg_base;
  71. struct milbeaut_hdmac_chan channels[];
  72. };
  73. static struct milbeaut_hdmac_chan *
  74. to_milbeaut_hdmac_chan(struct virt_dma_chan *vc)
  75. {
  76. return container_of(vc, struct milbeaut_hdmac_chan, vc);
  77. }
  78. static struct milbeaut_hdmac_desc *
  79. to_milbeaut_hdmac_desc(struct virt_dma_desc *vd)
  80. {
  81. return container_of(vd, struct milbeaut_hdmac_desc, vd);
  82. }
  83. /* mc->vc.lock must be held by caller */
  84. static struct milbeaut_hdmac_desc *
  85. milbeaut_hdmac_next_desc(struct milbeaut_hdmac_chan *mc)
  86. {
  87. struct virt_dma_desc *vd;
  88. vd = vchan_next_desc(&mc->vc);
  89. if (!vd) {
  90. mc->md = NULL;
  91. return NULL;
  92. }
  93. list_del(&vd->node);
  94. mc->md = to_milbeaut_hdmac_desc(vd);
  95. return mc->md;
  96. }
  97. /* mc->vc.lock must be held by caller */
  98. static void milbeaut_chan_start(struct milbeaut_hdmac_chan *mc,
  99. struct milbeaut_hdmac_desc *md)
  100. {
  101. struct scatterlist *sg;
  102. u32 cb, ca, src_addr, dest_addr, len;
  103. u32 width, burst;
  104. sg = &md->sgl[md->sg_cur];
  105. len = sg_dma_len(sg);
  106. cb = MLB_HDMAC_CI | MLB_HDMAC_EI;
  107. if (md->dir == DMA_MEM_TO_DEV) {
  108. cb |= MLB_HDMAC_FD;
  109. width = mc->cfg.dst_addr_width;
  110. burst = mc->cfg.dst_maxburst;
  111. src_addr = sg_dma_address(sg);
  112. dest_addr = mc->cfg.dst_addr;
  113. } else {
  114. cb |= MLB_HDMAC_FS;
  115. width = mc->cfg.src_addr_width;
  116. burst = mc->cfg.src_maxburst;
  117. src_addr = mc->cfg.src_addr;
  118. dest_addr = sg_dma_address(sg);
  119. }
  120. cb |= FIELD_PREP(MLB_HDMAC_TW, (width >> 1));
  121. cb |= FIELD_PREP(MLB_HDMAC_MS, 2);
  122. writel_relaxed(MLB_HDMAC_DE, mc->mdev->reg_base + MLB_HDMAC_DMACR);
  123. writel_relaxed(src_addr, mc->reg_ch_base + MLB_HDMAC_DMACSA);
  124. writel_relaxed(dest_addr, mc->reg_ch_base + MLB_HDMAC_DMACDA);
  125. writel_relaxed(cb, mc->reg_ch_base + MLB_HDMAC_DMACB);
  126. ca = FIELD_PREP(MLB_HDMAC_IS, mc->slave_id);
  127. if (burst == 16)
  128. ca |= FIELD_PREP(MLB_HDMAC_BT, 0xf);
  129. else if (burst == 8)
  130. ca |= FIELD_PREP(MLB_HDMAC_BT, 0xd);
  131. else if (burst == 4)
  132. ca |= FIELD_PREP(MLB_HDMAC_BT, 0xb);
  133. burst *= width;
  134. ca |= FIELD_PREP(MLB_HDMAC_TC, (len / burst - 1));
  135. writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
  136. ca |= MLB_HDMAC_EB;
  137. writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
  138. }
  139. /* mc->vc.lock must be held by caller */
  140. static void milbeaut_hdmac_start(struct milbeaut_hdmac_chan *mc)
  141. {
  142. struct milbeaut_hdmac_desc *md;
  143. md = milbeaut_hdmac_next_desc(mc);
  144. if (md)
  145. milbeaut_chan_start(mc, md);
  146. }
  147. static irqreturn_t milbeaut_hdmac_interrupt(int irq, void *dev_id)
  148. {
  149. struct milbeaut_hdmac_chan *mc = dev_id;
  150. struct milbeaut_hdmac_desc *md;
  151. u32 val;
  152. spin_lock(&mc->vc.lock);
  153. /* Ack and Disable irqs */
  154. val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACB);
  155. val &= ~(FIELD_PREP(MLB_HDMAC_SS, HDMAC_PAUSE));
  156. writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
  157. val &= ~MLB_HDMAC_EI;
  158. val &= ~MLB_HDMAC_CI;
  159. writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
  160. md = mc->md;
  161. if (!md)
  162. goto out;
  163. md->sg_cur++;
  164. if (md->sg_cur >= md->sg_len) {
  165. vchan_cookie_complete(&md->vd);
  166. md = milbeaut_hdmac_next_desc(mc);
  167. if (!md)
  168. goto out;
  169. }
  170. milbeaut_chan_start(mc, md);
  171. out:
  172. spin_unlock(&mc->vc.lock);
  173. return IRQ_HANDLED;
  174. }
  175. static void milbeaut_hdmac_free_chan_resources(struct dma_chan *chan)
  176. {
  177. vchan_free_chan_resources(to_virt_chan(chan));
  178. }
  179. static int
  180. milbeaut_hdmac_chan_config(struct dma_chan *chan, struct dma_slave_config *cfg)
  181. {
  182. struct virt_dma_chan *vc = to_virt_chan(chan);
  183. struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
  184. spin_lock(&mc->vc.lock);
  185. mc->cfg = *cfg;
  186. spin_unlock(&mc->vc.lock);
  187. return 0;
  188. }
  189. static int milbeaut_hdmac_chan_pause(struct dma_chan *chan)
  190. {
  191. struct virt_dma_chan *vc = to_virt_chan(chan);
  192. struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
  193. u32 val;
  194. spin_lock(&mc->vc.lock);
  195. val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
  196. val |= MLB_HDMAC_PB;
  197. writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
  198. spin_unlock(&mc->vc.lock);
  199. return 0;
  200. }
  201. static int milbeaut_hdmac_chan_resume(struct dma_chan *chan)
  202. {
  203. struct virt_dma_chan *vc = to_virt_chan(chan);
  204. struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
  205. u32 val;
  206. spin_lock(&mc->vc.lock);
  207. val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
  208. val &= ~MLB_HDMAC_PB;
  209. writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
  210. spin_unlock(&mc->vc.lock);
  211. return 0;
  212. }
  213. static struct dma_async_tx_descriptor *
  214. milbeaut_hdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  215. unsigned int sg_len,
  216. enum dma_transfer_direction direction,
  217. unsigned long flags, void *context)
  218. {
  219. struct virt_dma_chan *vc = to_virt_chan(chan);
  220. struct milbeaut_hdmac_desc *md;
  221. int i;
  222. if (!is_slave_direction(direction))
  223. return NULL;
  224. md = kzalloc(sizeof(*md), GFP_NOWAIT);
  225. if (!md)
  226. return NULL;
  227. md->sgl = kzalloc(sizeof(*sgl) * sg_len, GFP_NOWAIT);
  228. if (!md->sgl) {
  229. kfree(md);
  230. return NULL;
  231. }
  232. for (i = 0; i < sg_len; i++)
  233. md->sgl[i] = sgl[i];
  234. md->sg_len = sg_len;
  235. md->dir = direction;
  236. return vchan_tx_prep(vc, &md->vd, flags);
  237. }
  238. static int milbeaut_hdmac_terminate_all(struct dma_chan *chan)
  239. {
  240. struct virt_dma_chan *vc = to_virt_chan(chan);
  241. struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
  242. unsigned long flags;
  243. u32 val;
  244. LIST_HEAD(head);
  245. spin_lock_irqsave(&vc->lock, flags);
  246. val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
  247. val &= ~MLB_HDMAC_EB; /* disable the channel */
  248. writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
  249. if (mc->md) {
  250. vchan_terminate_vdesc(&mc->md->vd);
  251. mc->md = NULL;
  252. }
  253. vchan_get_all_descriptors(vc, &head);
  254. spin_unlock_irqrestore(&vc->lock, flags);
  255. vchan_dma_desc_free_list(vc, &head);
  256. return 0;
  257. }
  258. static void milbeaut_hdmac_synchronize(struct dma_chan *chan)
  259. {
  260. vchan_synchronize(to_virt_chan(chan));
  261. }
  262. static enum dma_status milbeaut_hdmac_tx_status(struct dma_chan *chan,
  263. dma_cookie_t cookie,
  264. struct dma_tx_state *txstate)
  265. {
  266. struct virt_dma_chan *vc;
  267. struct virt_dma_desc *vd;
  268. struct milbeaut_hdmac_chan *mc;
  269. struct milbeaut_hdmac_desc *md = NULL;
  270. enum dma_status stat;
  271. unsigned long flags;
  272. int i;
  273. stat = dma_cookie_status(chan, cookie, txstate);
  274. /* Return immediately if we do not need to compute the residue. */
  275. if (stat == DMA_COMPLETE || !txstate)
  276. return stat;
  277. vc = to_virt_chan(chan);
  278. spin_lock_irqsave(&vc->lock, flags);
  279. mc = to_milbeaut_hdmac_chan(vc);
  280. /* residue from the on-flight chunk */
  281. if (mc->md && mc->md->vd.tx.cookie == cookie) {
  282. struct scatterlist *sg;
  283. u32 done;
  284. md = mc->md;
  285. sg = &md->sgl[md->sg_cur];
  286. if (md->dir == DMA_DEV_TO_MEM)
  287. done = readl_relaxed(mc->reg_ch_base
  288. + MLB_HDMAC_DMACDA);
  289. else
  290. done = readl_relaxed(mc->reg_ch_base
  291. + MLB_HDMAC_DMACSA);
  292. done -= sg_dma_address(sg);
  293. txstate->residue = -done;
  294. }
  295. if (!md) {
  296. vd = vchan_find_desc(vc, cookie);
  297. if (vd)
  298. md = to_milbeaut_hdmac_desc(vd);
  299. }
  300. if (md) {
  301. /* residue from the queued chunks */
  302. for (i = md->sg_cur; i < md->sg_len; i++)
  303. txstate->residue += sg_dma_len(&md->sgl[i]);
  304. }
  305. spin_unlock_irqrestore(&vc->lock, flags);
  306. return stat;
  307. }
  308. static void milbeaut_hdmac_issue_pending(struct dma_chan *chan)
  309. {
  310. struct virt_dma_chan *vc = to_virt_chan(chan);
  311. struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
  312. unsigned long flags;
  313. spin_lock_irqsave(&vc->lock, flags);
  314. if (vchan_issue_pending(vc) && !mc->md)
  315. milbeaut_hdmac_start(mc);
  316. spin_unlock_irqrestore(&vc->lock, flags);
  317. }
  318. static void milbeaut_hdmac_desc_free(struct virt_dma_desc *vd)
  319. {
  320. struct milbeaut_hdmac_desc *md = to_milbeaut_hdmac_desc(vd);
  321. kfree(md->sgl);
  322. kfree(md);
  323. }
  324. static struct dma_chan *
  325. milbeaut_hdmac_xlate(struct of_phandle_args *dma_spec, struct of_dma *of_dma)
  326. {
  327. struct milbeaut_hdmac_device *mdev = of_dma->of_dma_data;
  328. struct milbeaut_hdmac_chan *mc;
  329. struct virt_dma_chan *vc;
  330. struct dma_chan *chan;
  331. if (dma_spec->args_count != 1)
  332. return NULL;
  333. chan = dma_get_any_slave_channel(&mdev->ddev);
  334. if (!chan)
  335. return NULL;
  336. vc = to_virt_chan(chan);
  337. mc = to_milbeaut_hdmac_chan(vc);
  338. mc->slave_id = dma_spec->args[0];
  339. return chan;
  340. }
  341. static int milbeaut_hdmac_chan_init(struct platform_device *pdev,
  342. struct milbeaut_hdmac_device *mdev,
  343. int chan_id)
  344. {
  345. struct device *dev = &pdev->dev;
  346. struct milbeaut_hdmac_chan *mc = &mdev->channels[chan_id];
  347. char *irq_name;
  348. int irq, ret;
  349. irq = platform_get_irq(pdev, chan_id);
  350. if (irq < 0)
  351. return irq;
  352. irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-hdmac-%d",
  353. chan_id);
  354. if (!irq_name)
  355. return -ENOMEM;
  356. ret = devm_request_irq(dev, irq, milbeaut_hdmac_interrupt,
  357. IRQF_SHARED, irq_name, mc);
  358. if (ret)
  359. return ret;
  360. mc->mdev = mdev;
  361. mc->reg_ch_base = mdev->reg_base + MLB_HDMAC_CH_STRIDE * (chan_id + 1);
  362. mc->vc.desc_free = milbeaut_hdmac_desc_free;
  363. vchan_init(&mc->vc, &mdev->ddev);
  364. return 0;
  365. }
  366. static int milbeaut_hdmac_probe(struct platform_device *pdev)
  367. {
  368. struct device *dev = &pdev->dev;
  369. struct milbeaut_hdmac_device *mdev;
  370. struct dma_device *ddev;
  371. int nr_chans, ret, i;
  372. nr_chans = platform_irq_count(pdev);
  373. if (nr_chans < 0)
  374. return nr_chans;
  375. ret = dma_set_mask(dev, DMA_BIT_MASK(32));
  376. if (ret)
  377. return ret;
  378. mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
  379. GFP_KERNEL);
  380. if (!mdev)
  381. return -ENOMEM;
  382. mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
  383. if (IS_ERR(mdev->reg_base))
  384. return PTR_ERR(mdev->reg_base);
  385. mdev->clk = devm_clk_get(dev, NULL);
  386. if (IS_ERR(mdev->clk)) {
  387. dev_err(dev, "failed to get clock\n");
  388. return PTR_ERR(mdev->clk);
  389. }
  390. ret = clk_prepare_enable(mdev->clk);
  391. if (ret)
  392. return ret;
  393. ddev = &mdev->ddev;
  394. ddev->dev = dev;
  395. dma_cap_set(DMA_SLAVE, ddev->cap_mask);
  396. dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
  397. ddev->src_addr_widths = MLB_HDMAC_BUSWIDTHS;
  398. ddev->dst_addr_widths = MLB_HDMAC_BUSWIDTHS;
  399. ddev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
  400. ddev->device_free_chan_resources = milbeaut_hdmac_free_chan_resources;
  401. ddev->device_config = milbeaut_hdmac_chan_config;
  402. ddev->device_pause = milbeaut_hdmac_chan_pause;
  403. ddev->device_resume = milbeaut_hdmac_chan_resume;
  404. ddev->device_prep_slave_sg = milbeaut_hdmac_prep_slave_sg;
  405. ddev->device_terminate_all = milbeaut_hdmac_terminate_all;
  406. ddev->device_synchronize = milbeaut_hdmac_synchronize;
  407. ddev->device_tx_status = milbeaut_hdmac_tx_status;
  408. ddev->device_issue_pending = milbeaut_hdmac_issue_pending;
  409. INIT_LIST_HEAD(&ddev->channels);
  410. for (i = 0; i < nr_chans; i++) {
  411. ret = milbeaut_hdmac_chan_init(pdev, mdev, i);
  412. if (ret)
  413. goto disable_clk;
  414. }
  415. ret = dma_async_device_register(ddev);
  416. if (ret)
  417. goto disable_clk;
  418. ret = of_dma_controller_register(dev->of_node,
  419. milbeaut_hdmac_xlate, mdev);
  420. if (ret)
  421. goto unregister_dmac;
  422. platform_set_drvdata(pdev, mdev);
  423. return 0;
  424. unregister_dmac:
  425. dma_async_device_unregister(ddev);
  426. disable_clk:
  427. clk_disable_unprepare(mdev->clk);
  428. return ret;
  429. }
  430. static int milbeaut_hdmac_remove(struct platform_device *pdev)
  431. {
  432. struct milbeaut_hdmac_device *mdev = platform_get_drvdata(pdev);
  433. struct dma_chan *chan;
  434. int ret;
  435. /*
  436. * Before reaching here, almost all descriptors have been freed by the
  437. * ->device_free_chan_resources() hook. However, each channel might
  438. * be still holding one descriptor that was on-flight at that moment.
  439. * Terminate it to make sure this hardware is no longer running. Then,
  440. * free the channel resources once again to avoid memory leak.
  441. */
  442. list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
  443. ret = dmaengine_terminate_sync(chan);
  444. if (ret)
  445. return ret;
  446. milbeaut_hdmac_free_chan_resources(chan);
  447. }
  448. of_dma_controller_free(pdev->dev.of_node);
  449. dma_async_device_unregister(&mdev->ddev);
  450. clk_disable_unprepare(mdev->clk);
  451. return 0;
  452. }
  453. static const struct of_device_id milbeaut_hdmac_match[] = {
  454. { .compatible = "socionext,milbeaut-m10v-hdmac" },
  455. { /* sentinel */ }
  456. };
  457. MODULE_DEVICE_TABLE(of, milbeaut_hdmac_match);
  458. static struct platform_driver milbeaut_hdmac_driver = {
  459. .probe = milbeaut_hdmac_probe,
  460. .remove = milbeaut_hdmac_remove,
  461. .driver = {
  462. .name = "milbeaut-m10v-hdmac",
  463. .of_match_table = milbeaut_hdmac_match,
  464. },
  465. };
  466. module_platform_driver(milbeaut_hdmac_driver);
  467. MODULE_DESCRIPTION("Milbeaut HDMAC DmaEngine driver");
  468. MODULE_LICENSE("GPL v2");