k3dma.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 - 2015 Linaro Ltd.
  4. * Copyright (c) 2013 Hisilicon Limited.
  5. */
  6. #include <linux/sched.h>
  7. #include <linux/device.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dmapool.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of.h>
  20. #include <linux/clk.h>
  21. #include <linux/of_dma.h>
  22. #include "virt-dma.h"
  23. #define DRIVER_NAME "k3-dma"
  24. #define DMA_MAX_SIZE 0x1ffc
  25. #define DMA_CYCLIC_MAX_PERIOD 0x1000
  26. #define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
  27. #define INT_STAT 0x00
  28. #define INT_TC1 0x04
  29. #define INT_TC2 0x08
  30. #define INT_ERR1 0x0c
  31. #define INT_ERR2 0x10
  32. #define INT_TC1_MASK 0x18
  33. #define INT_TC2_MASK 0x1c
  34. #define INT_ERR1_MASK 0x20
  35. #define INT_ERR2_MASK 0x24
  36. #define INT_TC1_RAW 0x600
  37. #define INT_TC2_RAW 0x608
  38. #define INT_ERR1_RAW 0x610
  39. #define INT_ERR2_RAW 0x618
  40. #define CH_PRI 0x688
  41. #define CH_STAT 0x690
  42. #define CX_CUR_CNT 0x704
  43. #define CX_LLI 0x800
  44. #define CX_CNT1 0x80c
  45. #define CX_CNT0 0x810
  46. #define CX_SRC 0x814
  47. #define CX_DST 0x818
  48. #define CX_CFG 0x81c
  49. #define CX_LLI_CHAIN_EN 0x2
  50. #define CX_CFG_EN 0x1
  51. #define CX_CFG_NODEIRQ BIT(1)
  52. #define CX_CFG_MEM2PER (0x1 << 2)
  53. #define CX_CFG_PER2MEM (0x2 << 2)
  54. #define CX_CFG_SRCINCR (0x1 << 31)
  55. #define CX_CFG_DSTINCR (0x1 << 30)
  56. struct k3_desc_hw {
  57. u32 lli;
  58. u32 reserved[3];
  59. u32 count;
  60. u32 saddr;
  61. u32 daddr;
  62. u32 config;
  63. } __aligned(32);
  64. struct k3_dma_desc_sw {
  65. struct virt_dma_desc vd;
  66. dma_addr_t desc_hw_lli;
  67. size_t desc_num;
  68. size_t size;
  69. struct k3_desc_hw *desc_hw;
  70. };
  71. struct k3_dma_phy;
  72. struct k3_dma_chan {
  73. u32 ccfg;
  74. struct virt_dma_chan vc;
  75. struct k3_dma_phy *phy;
  76. struct list_head node;
  77. dma_addr_t dev_addr;
  78. enum dma_status status;
  79. bool cyclic;
  80. struct dma_slave_config slave_config;
  81. };
  82. struct k3_dma_phy {
  83. u32 idx;
  84. void __iomem *base;
  85. struct k3_dma_chan *vchan;
  86. struct k3_dma_desc_sw *ds_run;
  87. struct k3_dma_desc_sw *ds_done;
  88. };
  89. struct k3_dma_dev {
  90. struct dma_device slave;
  91. void __iomem *base;
  92. struct tasklet_struct task;
  93. spinlock_t lock;
  94. struct list_head chan_pending;
  95. struct k3_dma_phy *phy;
  96. struct k3_dma_chan *chans;
  97. struct clk *clk;
  98. struct dma_pool *pool;
  99. u32 dma_channels;
  100. u32 dma_requests;
  101. u32 dma_channel_mask;
  102. unsigned int irq;
  103. };
  104. #define K3_FLAG_NOCLK BIT(1)
  105. struct k3dma_soc_data {
  106. unsigned long flags;
  107. };
  108. #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
  109. static int k3_dma_config_write(struct dma_chan *chan,
  110. enum dma_transfer_direction dir,
  111. struct dma_slave_config *cfg);
  112. static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
  113. {
  114. return container_of(chan, struct k3_dma_chan, vc.chan);
  115. }
  116. static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
  117. {
  118. u32 val = 0;
  119. if (on) {
  120. val = readl_relaxed(phy->base + CX_CFG);
  121. val |= CX_CFG_EN;
  122. writel_relaxed(val, phy->base + CX_CFG);
  123. } else {
  124. val = readl_relaxed(phy->base + CX_CFG);
  125. val &= ~CX_CFG_EN;
  126. writel_relaxed(val, phy->base + CX_CFG);
  127. }
  128. }
  129. static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
  130. {
  131. u32 val = 0;
  132. k3_dma_pause_dma(phy, false);
  133. val = 0x1 << phy->idx;
  134. writel_relaxed(val, d->base + INT_TC1_RAW);
  135. writel_relaxed(val, d->base + INT_TC2_RAW);
  136. writel_relaxed(val, d->base + INT_ERR1_RAW);
  137. writel_relaxed(val, d->base + INT_ERR2_RAW);
  138. }
  139. static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
  140. {
  141. writel_relaxed(hw->lli, phy->base + CX_LLI);
  142. writel_relaxed(hw->count, phy->base + CX_CNT0);
  143. writel_relaxed(hw->saddr, phy->base + CX_SRC);
  144. writel_relaxed(hw->daddr, phy->base + CX_DST);
  145. writel_relaxed(hw->config, phy->base + CX_CFG);
  146. }
  147. static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
  148. {
  149. u32 cnt = 0;
  150. cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
  151. cnt &= 0xffff;
  152. return cnt;
  153. }
  154. static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
  155. {
  156. return readl_relaxed(phy->base + CX_LLI);
  157. }
  158. static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
  159. {
  160. return readl_relaxed(d->base + CH_STAT);
  161. }
  162. static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
  163. {
  164. if (on) {
  165. /* set same priority */
  166. writel_relaxed(0x0, d->base + CH_PRI);
  167. /* unmask irq */
  168. writel_relaxed(0xffff, d->base + INT_TC1_MASK);
  169. writel_relaxed(0xffff, d->base + INT_TC2_MASK);
  170. writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
  171. writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
  172. } else {
  173. /* mask irq */
  174. writel_relaxed(0x0, d->base + INT_TC1_MASK);
  175. writel_relaxed(0x0, d->base + INT_TC2_MASK);
  176. writel_relaxed(0x0, d->base + INT_ERR1_MASK);
  177. writel_relaxed(0x0, d->base + INT_ERR2_MASK);
  178. }
  179. }
  180. static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
  181. {
  182. struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
  183. struct k3_dma_phy *p;
  184. struct k3_dma_chan *c;
  185. u32 stat = readl_relaxed(d->base + INT_STAT);
  186. u32 tc1 = readl_relaxed(d->base + INT_TC1);
  187. u32 tc2 = readl_relaxed(d->base + INT_TC2);
  188. u32 err1 = readl_relaxed(d->base + INT_ERR1);
  189. u32 err2 = readl_relaxed(d->base + INT_ERR2);
  190. u32 i, irq_chan = 0;
  191. while (stat) {
  192. i = __ffs(stat);
  193. stat &= ~BIT(i);
  194. if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
  195. unsigned long flags;
  196. p = &d->phy[i];
  197. c = p->vchan;
  198. if (c && (tc1 & BIT(i))) {
  199. spin_lock_irqsave(&c->vc.lock, flags);
  200. if (p->ds_run != NULL) {
  201. vchan_cookie_complete(&p->ds_run->vd);
  202. p->ds_done = p->ds_run;
  203. p->ds_run = NULL;
  204. }
  205. spin_unlock_irqrestore(&c->vc.lock, flags);
  206. }
  207. if (c && (tc2 & BIT(i))) {
  208. spin_lock_irqsave(&c->vc.lock, flags);
  209. if (p->ds_run != NULL)
  210. vchan_cyclic_callback(&p->ds_run->vd);
  211. spin_unlock_irqrestore(&c->vc.lock, flags);
  212. }
  213. irq_chan |= BIT(i);
  214. }
  215. if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
  216. dev_warn(d->slave.dev, "DMA ERR\n");
  217. }
  218. writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
  219. writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
  220. writel_relaxed(err1, d->base + INT_ERR1_RAW);
  221. writel_relaxed(err2, d->base + INT_ERR2_RAW);
  222. if (irq_chan)
  223. tasklet_schedule(&d->task);
  224. if (irq_chan || err1 || err2)
  225. return IRQ_HANDLED;
  226. return IRQ_NONE;
  227. }
  228. static int k3_dma_start_txd(struct k3_dma_chan *c)
  229. {
  230. struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
  231. struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
  232. if (!c->phy)
  233. return -EAGAIN;
  234. if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
  235. return -EAGAIN;
  236. /* Avoid losing track of ds_run if a transaction is in flight */
  237. if (c->phy->ds_run)
  238. return -EAGAIN;
  239. if (vd) {
  240. struct k3_dma_desc_sw *ds =
  241. container_of(vd, struct k3_dma_desc_sw, vd);
  242. /*
  243. * fetch and remove request from vc->desc_issued
  244. * so vc->desc_issued only contains desc pending
  245. */
  246. list_del(&ds->vd.node);
  247. c->phy->ds_run = ds;
  248. c->phy->ds_done = NULL;
  249. /* start dma */
  250. k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
  251. return 0;
  252. }
  253. c->phy->ds_run = NULL;
  254. c->phy->ds_done = NULL;
  255. return -EAGAIN;
  256. }
  257. static void k3_dma_tasklet(struct tasklet_struct *t)
  258. {
  259. struct k3_dma_dev *d = from_tasklet(d, t, task);
  260. struct k3_dma_phy *p;
  261. struct k3_dma_chan *c, *cn;
  262. unsigned pch, pch_alloc = 0;
  263. /* check new dma request of running channel in vc->desc_issued */
  264. list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
  265. spin_lock_irq(&c->vc.lock);
  266. p = c->phy;
  267. if (p && p->ds_done) {
  268. if (k3_dma_start_txd(c)) {
  269. /* No current txd associated with this channel */
  270. dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
  271. /* Mark this channel free */
  272. c->phy = NULL;
  273. p->vchan = NULL;
  274. }
  275. }
  276. spin_unlock_irq(&c->vc.lock);
  277. }
  278. /* check new channel request in d->chan_pending */
  279. spin_lock_irq(&d->lock);
  280. for (pch = 0; pch < d->dma_channels; pch++) {
  281. if (!(d->dma_channel_mask & (1 << pch)))
  282. continue;
  283. p = &d->phy[pch];
  284. if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
  285. c = list_first_entry(&d->chan_pending,
  286. struct k3_dma_chan, node);
  287. /* remove from d->chan_pending */
  288. list_del_init(&c->node);
  289. pch_alloc |= 1 << pch;
  290. /* Mark this channel allocated */
  291. p->vchan = c;
  292. c->phy = p;
  293. dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
  294. }
  295. }
  296. spin_unlock_irq(&d->lock);
  297. for (pch = 0; pch < d->dma_channels; pch++) {
  298. if (!(d->dma_channel_mask & (1 << pch)))
  299. continue;
  300. if (pch_alloc & (1 << pch)) {
  301. p = &d->phy[pch];
  302. c = p->vchan;
  303. if (c) {
  304. spin_lock_irq(&c->vc.lock);
  305. k3_dma_start_txd(c);
  306. spin_unlock_irq(&c->vc.lock);
  307. }
  308. }
  309. }
  310. }
  311. static void k3_dma_free_chan_resources(struct dma_chan *chan)
  312. {
  313. struct k3_dma_chan *c = to_k3_chan(chan);
  314. struct k3_dma_dev *d = to_k3_dma(chan->device);
  315. unsigned long flags;
  316. spin_lock_irqsave(&d->lock, flags);
  317. list_del_init(&c->node);
  318. spin_unlock_irqrestore(&d->lock, flags);
  319. vchan_free_chan_resources(&c->vc);
  320. c->ccfg = 0;
  321. }
  322. static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
  323. dma_cookie_t cookie, struct dma_tx_state *state)
  324. {
  325. struct k3_dma_chan *c = to_k3_chan(chan);
  326. struct k3_dma_dev *d = to_k3_dma(chan->device);
  327. struct k3_dma_phy *p;
  328. struct virt_dma_desc *vd;
  329. unsigned long flags;
  330. enum dma_status ret;
  331. size_t bytes = 0;
  332. ret = dma_cookie_status(&c->vc.chan, cookie, state);
  333. if (ret == DMA_COMPLETE)
  334. return ret;
  335. spin_lock_irqsave(&c->vc.lock, flags);
  336. p = c->phy;
  337. ret = c->status;
  338. /*
  339. * If the cookie is on our issue queue, then the residue is
  340. * its total size.
  341. */
  342. vd = vchan_find_desc(&c->vc, cookie);
  343. if (vd && !c->cyclic) {
  344. bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
  345. } else if ((!p) || (!p->ds_run)) {
  346. bytes = 0;
  347. } else {
  348. struct k3_dma_desc_sw *ds = p->ds_run;
  349. u32 clli = 0, index = 0;
  350. bytes = k3_dma_get_curr_cnt(d, p);
  351. clli = k3_dma_get_curr_lli(p);
  352. index = ((clli - ds->desc_hw_lli) /
  353. sizeof(struct k3_desc_hw)) + 1;
  354. for (; index < ds->desc_num; index++) {
  355. bytes += ds->desc_hw[index].count;
  356. /* end of lli */
  357. if (!ds->desc_hw[index].lli)
  358. break;
  359. }
  360. }
  361. spin_unlock_irqrestore(&c->vc.lock, flags);
  362. dma_set_residue(state, bytes);
  363. return ret;
  364. }
  365. static void k3_dma_issue_pending(struct dma_chan *chan)
  366. {
  367. struct k3_dma_chan *c = to_k3_chan(chan);
  368. struct k3_dma_dev *d = to_k3_dma(chan->device);
  369. unsigned long flags;
  370. spin_lock_irqsave(&c->vc.lock, flags);
  371. /* add request to vc->desc_issued */
  372. if (vchan_issue_pending(&c->vc)) {
  373. spin_lock(&d->lock);
  374. if (!c->phy) {
  375. if (list_empty(&c->node)) {
  376. /* if new channel, add chan_pending */
  377. list_add_tail(&c->node, &d->chan_pending);
  378. /* check in tasklet */
  379. tasklet_schedule(&d->task);
  380. dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
  381. }
  382. }
  383. spin_unlock(&d->lock);
  384. } else
  385. dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
  386. spin_unlock_irqrestore(&c->vc.lock, flags);
  387. }
  388. static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
  389. dma_addr_t src, size_t len, u32 num, u32 ccfg)
  390. {
  391. if (num != ds->desc_num - 1)
  392. ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
  393. sizeof(struct k3_desc_hw);
  394. ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
  395. ds->desc_hw[num].count = len;
  396. ds->desc_hw[num].saddr = src;
  397. ds->desc_hw[num].daddr = dst;
  398. ds->desc_hw[num].config = ccfg;
  399. }
  400. static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
  401. struct dma_chan *chan)
  402. {
  403. struct k3_dma_chan *c = to_k3_chan(chan);
  404. struct k3_dma_desc_sw *ds;
  405. struct k3_dma_dev *d = to_k3_dma(chan->device);
  406. int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
  407. if (num > lli_limit) {
  408. dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
  409. &c->vc, num, lli_limit);
  410. return NULL;
  411. }
  412. ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
  413. if (!ds)
  414. return NULL;
  415. ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
  416. if (!ds->desc_hw) {
  417. dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
  418. kfree(ds);
  419. return NULL;
  420. }
  421. ds->desc_num = num;
  422. return ds;
  423. }
  424. static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
  425. struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
  426. size_t len, unsigned long flags)
  427. {
  428. struct k3_dma_chan *c = to_k3_chan(chan);
  429. struct k3_dma_desc_sw *ds;
  430. size_t copy = 0;
  431. int num = 0;
  432. if (!len)
  433. return NULL;
  434. num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
  435. ds = k3_dma_alloc_desc_resource(num, chan);
  436. if (!ds)
  437. return NULL;
  438. c->cyclic = 0;
  439. ds->size = len;
  440. num = 0;
  441. if (!c->ccfg) {
  442. /* default is memtomem, without calling device_config */
  443. c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
  444. c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
  445. c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
  446. }
  447. do {
  448. copy = min_t(size_t, len, DMA_MAX_SIZE);
  449. k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
  450. src += copy;
  451. dst += copy;
  452. len -= copy;
  453. } while (len);
  454. ds->desc_hw[num-1].lli = 0; /* end of link */
  455. return vchan_tx_prep(&c->vc, &ds->vd, flags);
  456. }
  457. static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
  458. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
  459. enum dma_transfer_direction dir, unsigned long flags, void *context)
  460. {
  461. struct k3_dma_chan *c = to_k3_chan(chan);
  462. struct k3_dma_desc_sw *ds;
  463. size_t len, avail, total = 0;
  464. struct scatterlist *sg;
  465. dma_addr_t addr, src = 0, dst = 0;
  466. int num = sglen, i;
  467. if (sgl == NULL)
  468. return NULL;
  469. c->cyclic = 0;
  470. for_each_sg(sgl, sg, sglen, i) {
  471. avail = sg_dma_len(sg);
  472. if (avail > DMA_MAX_SIZE)
  473. num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
  474. }
  475. ds = k3_dma_alloc_desc_resource(num, chan);
  476. if (!ds)
  477. return NULL;
  478. num = 0;
  479. k3_dma_config_write(chan, dir, &c->slave_config);
  480. for_each_sg(sgl, sg, sglen, i) {
  481. addr = sg_dma_address(sg);
  482. avail = sg_dma_len(sg);
  483. total += avail;
  484. do {
  485. len = min_t(size_t, avail, DMA_MAX_SIZE);
  486. if (dir == DMA_MEM_TO_DEV) {
  487. src = addr;
  488. dst = c->dev_addr;
  489. } else if (dir == DMA_DEV_TO_MEM) {
  490. src = c->dev_addr;
  491. dst = addr;
  492. }
  493. k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
  494. addr += len;
  495. avail -= len;
  496. } while (avail);
  497. }
  498. ds->desc_hw[num-1].lli = 0; /* end of link */
  499. ds->size = total;
  500. return vchan_tx_prep(&c->vc, &ds->vd, flags);
  501. }
  502. static struct dma_async_tx_descriptor *
  503. k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
  504. size_t buf_len, size_t period_len,
  505. enum dma_transfer_direction dir,
  506. unsigned long flags)
  507. {
  508. struct k3_dma_chan *c = to_k3_chan(chan);
  509. struct k3_dma_desc_sw *ds;
  510. size_t len, avail, total = 0;
  511. dma_addr_t addr, src = 0, dst = 0;
  512. int num = 1, since = 0;
  513. size_t modulo = DMA_CYCLIC_MAX_PERIOD;
  514. u32 en_tc2 = 0;
  515. dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
  516. __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
  517. buf_len, period_len, (int)dir);
  518. avail = buf_len;
  519. if (avail > modulo)
  520. num += DIV_ROUND_UP(avail, modulo) - 1;
  521. ds = k3_dma_alloc_desc_resource(num, chan);
  522. if (!ds)
  523. return NULL;
  524. c->cyclic = 1;
  525. addr = buf_addr;
  526. avail = buf_len;
  527. total = avail;
  528. num = 0;
  529. k3_dma_config_write(chan, dir, &c->slave_config);
  530. if (period_len < modulo)
  531. modulo = period_len;
  532. do {
  533. len = min_t(size_t, avail, modulo);
  534. if (dir == DMA_MEM_TO_DEV) {
  535. src = addr;
  536. dst = c->dev_addr;
  537. } else if (dir == DMA_DEV_TO_MEM) {
  538. src = c->dev_addr;
  539. dst = addr;
  540. }
  541. since += len;
  542. if (since >= period_len) {
  543. /* descriptor asks for TC2 interrupt on completion */
  544. en_tc2 = CX_CFG_NODEIRQ;
  545. since -= period_len;
  546. } else
  547. en_tc2 = 0;
  548. k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
  549. addr += len;
  550. avail -= len;
  551. } while (avail);
  552. /* "Cyclic" == end of link points back to start of link */
  553. ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
  554. ds->size = total;
  555. return vchan_tx_prep(&c->vc, &ds->vd, flags);
  556. }
  557. static int k3_dma_config(struct dma_chan *chan,
  558. struct dma_slave_config *cfg)
  559. {
  560. struct k3_dma_chan *c = to_k3_chan(chan);
  561. memcpy(&c->slave_config, cfg, sizeof(*cfg));
  562. return 0;
  563. }
  564. static int k3_dma_config_write(struct dma_chan *chan,
  565. enum dma_transfer_direction dir,
  566. struct dma_slave_config *cfg)
  567. {
  568. struct k3_dma_chan *c = to_k3_chan(chan);
  569. u32 maxburst = 0, val = 0;
  570. enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  571. if (dir == DMA_DEV_TO_MEM) {
  572. c->ccfg = CX_CFG_DSTINCR;
  573. c->dev_addr = cfg->src_addr;
  574. maxburst = cfg->src_maxburst;
  575. width = cfg->src_addr_width;
  576. } else if (dir == DMA_MEM_TO_DEV) {
  577. c->ccfg = CX_CFG_SRCINCR;
  578. c->dev_addr = cfg->dst_addr;
  579. maxburst = cfg->dst_maxburst;
  580. width = cfg->dst_addr_width;
  581. }
  582. switch (width) {
  583. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  584. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  585. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  586. case DMA_SLAVE_BUSWIDTH_8_BYTES:
  587. val = __ffs(width);
  588. break;
  589. default:
  590. val = 3;
  591. break;
  592. }
  593. c->ccfg |= (val << 12) | (val << 16);
  594. if ((maxburst == 0) || (maxburst > 16))
  595. val = 15;
  596. else
  597. val = maxburst - 1;
  598. c->ccfg |= (val << 20) | (val << 24);
  599. c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
  600. /* specific request line */
  601. c->ccfg |= c->vc.chan.chan_id << 4;
  602. return 0;
  603. }
  604. static void k3_dma_free_desc(struct virt_dma_desc *vd)
  605. {
  606. struct k3_dma_desc_sw *ds =
  607. container_of(vd, struct k3_dma_desc_sw, vd);
  608. struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
  609. dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
  610. kfree(ds);
  611. }
  612. static int k3_dma_terminate_all(struct dma_chan *chan)
  613. {
  614. struct k3_dma_chan *c = to_k3_chan(chan);
  615. struct k3_dma_dev *d = to_k3_dma(chan->device);
  616. struct k3_dma_phy *p = c->phy;
  617. unsigned long flags;
  618. LIST_HEAD(head);
  619. dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
  620. /* Prevent this channel being scheduled */
  621. spin_lock(&d->lock);
  622. list_del_init(&c->node);
  623. spin_unlock(&d->lock);
  624. /* Clear the tx descriptor lists */
  625. spin_lock_irqsave(&c->vc.lock, flags);
  626. vchan_get_all_descriptors(&c->vc, &head);
  627. if (p) {
  628. /* vchan is assigned to a pchan - stop the channel */
  629. k3_dma_terminate_chan(p, d);
  630. c->phy = NULL;
  631. p->vchan = NULL;
  632. if (p->ds_run) {
  633. vchan_terminate_vdesc(&p->ds_run->vd);
  634. p->ds_run = NULL;
  635. }
  636. p->ds_done = NULL;
  637. }
  638. spin_unlock_irqrestore(&c->vc.lock, flags);
  639. vchan_dma_desc_free_list(&c->vc, &head);
  640. return 0;
  641. }
  642. static void k3_dma_synchronize(struct dma_chan *chan)
  643. {
  644. struct k3_dma_chan *c = to_k3_chan(chan);
  645. vchan_synchronize(&c->vc);
  646. }
  647. static int k3_dma_transfer_pause(struct dma_chan *chan)
  648. {
  649. struct k3_dma_chan *c = to_k3_chan(chan);
  650. struct k3_dma_dev *d = to_k3_dma(chan->device);
  651. struct k3_dma_phy *p = c->phy;
  652. dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
  653. if (c->status == DMA_IN_PROGRESS) {
  654. c->status = DMA_PAUSED;
  655. if (p) {
  656. k3_dma_pause_dma(p, false);
  657. } else {
  658. spin_lock(&d->lock);
  659. list_del_init(&c->node);
  660. spin_unlock(&d->lock);
  661. }
  662. }
  663. return 0;
  664. }
  665. static int k3_dma_transfer_resume(struct dma_chan *chan)
  666. {
  667. struct k3_dma_chan *c = to_k3_chan(chan);
  668. struct k3_dma_dev *d = to_k3_dma(chan->device);
  669. struct k3_dma_phy *p = c->phy;
  670. unsigned long flags;
  671. dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
  672. spin_lock_irqsave(&c->vc.lock, flags);
  673. if (c->status == DMA_PAUSED) {
  674. c->status = DMA_IN_PROGRESS;
  675. if (p) {
  676. k3_dma_pause_dma(p, true);
  677. } else if (!list_empty(&c->vc.desc_issued)) {
  678. spin_lock(&d->lock);
  679. list_add_tail(&c->node, &d->chan_pending);
  680. spin_unlock(&d->lock);
  681. }
  682. }
  683. spin_unlock_irqrestore(&c->vc.lock, flags);
  684. return 0;
  685. }
  686. static const struct k3dma_soc_data k3_v1_dma_data = {
  687. .flags = 0,
  688. };
  689. static const struct k3dma_soc_data asp_v1_dma_data = {
  690. .flags = K3_FLAG_NOCLK,
  691. };
  692. static const struct of_device_id k3_pdma_dt_ids[] = {
  693. { .compatible = "hisilicon,k3-dma-1.0",
  694. .data = &k3_v1_dma_data
  695. },
  696. { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0",
  697. .data = &asp_v1_dma_data
  698. },
  699. {}
  700. };
  701. MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
  702. static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
  703. struct of_dma *ofdma)
  704. {
  705. struct k3_dma_dev *d = ofdma->of_dma_data;
  706. unsigned int request = dma_spec->args[0];
  707. if (request >= d->dma_requests)
  708. return NULL;
  709. return dma_get_slave_channel(&(d->chans[request].vc.chan));
  710. }
  711. static int k3_dma_probe(struct platform_device *op)
  712. {
  713. const struct k3dma_soc_data *soc_data;
  714. struct k3_dma_dev *d;
  715. const struct of_device_id *of_id;
  716. int i, ret, irq = 0;
  717. d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
  718. if (!d)
  719. return -ENOMEM;
  720. soc_data = device_get_match_data(&op->dev);
  721. if (!soc_data)
  722. return -EINVAL;
  723. d->base = devm_platform_ioremap_resource(op, 0);
  724. if (IS_ERR(d->base))
  725. return PTR_ERR(d->base);
  726. of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
  727. if (of_id) {
  728. of_property_read_u32((&op->dev)->of_node,
  729. "dma-channels", &d->dma_channels);
  730. of_property_read_u32((&op->dev)->of_node,
  731. "dma-requests", &d->dma_requests);
  732. ret = of_property_read_u32((&op->dev)->of_node,
  733. "dma-channel-mask", &d->dma_channel_mask);
  734. if (ret) {
  735. dev_warn(&op->dev,
  736. "dma-channel-mask doesn't exist, considering all as available.\n");
  737. d->dma_channel_mask = (u32)~0UL;
  738. }
  739. }
  740. if (!(soc_data->flags & K3_FLAG_NOCLK)) {
  741. d->clk = devm_clk_get(&op->dev, NULL);
  742. if (IS_ERR(d->clk)) {
  743. dev_err(&op->dev, "no dma clk\n");
  744. return PTR_ERR(d->clk);
  745. }
  746. }
  747. irq = platform_get_irq(op, 0);
  748. ret = devm_request_irq(&op->dev, irq,
  749. k3_dma_int_handler, 0, DRIVER_NAME, d);
  750. if (ret)
  751. return ret;
  752. d->irq = irq;
  753. /* A DMA memory pool for LLIs, align on 32-byte boundary */
  754. d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
  755. LLI_BLOCK_SIZE, 32, 0);
  756. if (!d->pool)
  757. return -ENOMEM;
  758. /* init phy channel */
  759. d->phy = devm_kcalloc(&op->dev,
  760. d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL);
  761. if (d->phy == NULL)
  762. return -ENOMEM;
  763. for (i = 0; i < d->dma_channels; i++) {
  764. struct k3_dma_phy *p;
  765. if (!(d->dma_channel_mask & BIT(i)))
  766. continue;
  767. p = &d->phy[i];
  768. p->idx = i;
  769. p->base = d->base + i * 0x40;
  770. }
  771. INIT_LIST_HEAD(&d->slave.channels);
  772. dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
  773. dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
  774. dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
  775. d->slave.dev = &op->dev;
  776. d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
  777. d->slave.device_tx_status = k3_dma_tx_status;
  778. d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
  779. d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
  780. d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
  781. d->slave.device_issue_pending = k3_dma_issue_pending;
  782. d->slave.device_config = k3_dma_config;
  783. d->slave.device_pause = k3_dma_transfer_pause;
  784. d->slave.device_resume = k3_dma_transfer_resume;
  785. d->slave.device_terminate_all = k3_dma_terminate_all;
  786. d->slave.device_synchronize = k3_dma_synchronize;
  787. d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
  788. /* init virtual channel */
  789. d->chans = devm_kcalloc(&op->dev,
  790. d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL);
  791. if (d->chans == NULL)
  792. return -ENOMEM;
  793. for (i = 0; i < d->dma_requests; i++) {
  794. struct k3_dma_chan *c = &d->chans[i];
  795. c->status = DMA_IN_PROGRESS;
  796. INIT_LIST_HEAD(&c->node);
  797. c->vc.desc_free = k3_dma_free_desc;
  798. vchan_init(&c->vc, &d->slave);
  799. }
  800. /* Enable clock before accessing registers */
  801. ret = clk_prepare_enable(d->clk);
  802. if (ret < 0) {
  803. dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
  804. return ret;
  805. }
  806. k3_dma_enable_dma(d, true);
  807. ret = dma_async_device_register(&d->slave);
  808. if (ret)
  809. goto dma_async_register_fail;
  810. ret = of_dma_controller_register((&op->dev)->of_node,
  811. k3_of_dma_simple_xlate, d);
  812. if (ret)
  813. goto of_dma_register_fail;
  814. spin_lock_init(&d->lock);
  815. INIT_LIST_HEAD(&d->chan_pending);
  816. tasklet_setup(&d->task, k3_dma_tasklet);
  817. platform_set_drvdata(op, d);
  818. dev_info(&op->dev, "initialized\n");
  819. return 0;
  820. of_dma_register_fail:
  821. dma_async_device_unregister(&d->slave);
  822. dma_async_register_fail:
  823. clk_disable_unprepare(d->clk);
  824. return ret;
  825. }
  826. static int k3_dma_remove(struct platform_device *op)
  827. {
  828. struct k3_dma_chan *c, *cn;
  829. struct k3_dma_dev *d = platform_get_drvdata(op);
  830. dma_async_device_unregister(&d->slave);
  831. of_dma_controller_free((&op->dev)->of_node);
  832. devm_free_irq(&op->dev, d->irq, d);
  833. list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
  834. list_del(&c->vc.chan.device_node);
  835. tasklet_kill(&c->vc.task);
  836. }
  837. tasklet_kill(&d->task);
  838. clk_disable_unprepare(d->clk);
  839. return 0;
  840. }
  841. #ifdef CONFIG_PM_SLEEP
  842. static int k3_dma_suspend_dev(struct device *dev)
  843. {
  844. struct k3_dma_dev *d = dev_get_drvdata(dev);
  845. u32 stat = 0;
  846. stat = k3_dma_get_chan_stat(d);
  847. if (stat) {
  848. dev_warn(d->slave.dev,
  849. "chan %d is running fail to suspend\n", stat);
  850. return -1;
  851. }
  852. k3_dma_enable_dma(d, false);
  853. clk_disable_unprepare(d->clk);
  854. return 0;
  855. }
  856. static int k3_dma_resume_dev(struct device *dev)
  857. {
  858. struct k3_dma_dev *d = dev_get_drvdata(dev);
  859. int ret = 0;
  860. ret = clk_prepare_enable(d->clk);
  861. if (ret < 0) {
  862. dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
  863. return ret;
  864. }
  865. k3_dma_enable_dma(d, true);
  866. return 0;
  867. }
  868. #endif
  869. static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
  870. static struct platform_driver k3_pdma_driver = {
  871. .driver = {
  872. .name = DRIVER_NAME,
  873. .pm = &k3_dma_pmops,
  874. .of_match_table = k3_pdma_dt_ids,
  875. },
  876. .probe = k3_dma_probe,
  877. .remove = k3_dma_remove,
  878. };
  879. module_platform_driver(k3_pdma_driver);
  880. MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
  881. MODULE_ALIAS("platform:k3dma");
  882. MODULE_LICENSE("GPL v2");