ipu_irq.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2008
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. */
  6. #include <linux/init.h>
  7. #include <linux/err.h>
  8. #include <linux/spinlock.h>
  9. #include <linux/delay.h>
  10. #include <linux/clk.h>
  11. #include <linux/irq.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/dma/ipu-dma.h>
  15. #include "ipu_intern.h"
  16. /*
  17. * Register read / write - shall be inlined by the compiler
  18. */
  19. static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
  20. {
  21. return __raw_readl(ipu->reg_ipu + reg);
  22. }
  23. static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
  24. {
  25. __raw_writel(value, ipu->reg_ipu + reg);
  26. }
  27. /*
  28. * IPU IRQ chip driver
  29. */
  30. #define IPU_IRQ_NR_FN_BANKS 3
  31. #define IPU_IRQ_NR_ERR_BANKS 2
  32. #define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
  33. struct ipu_irq_bank {
  34. unsigned int control;
  35. unsigned int status;
  36. struct ipu *ipu;
  37. };
  38. static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
  39. /* 3 groups of functional interrupts */
  40. {
  41. .control = IPU_INT_CTRL_1,
  42. .status = IPU_INT_STAT_1,
  43. }, {
  44. .control = IPU_INT_CTRL_2,
  45. .status = IPU_INT_STAT_2,
  46. }, {
  47. .control = IPU_INT_CTRL_3,
  48. .status = IPU_INT_STAT_3,
  49. },
  50. /* 2 groups of error interrupts */
  51. {
  52. .control = IPU_INT_CTRL_4,
  53. .status = IPU_INT_STAT_4,
  54. }, {
  55. .control = IPU_INT_CTRL_5,
  56. .status = IPU_INT_STAT_5,
  57. },
  58. };
  59. struct ipu_irq_map {
  60. unsigned int irq;
  61. int source;
  62. struct ipu_irq_bank *bank;
  63. struct ipu *ipu;
  64. };
  65. static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
  66. /* Protects allocations from the above array of maps */
  67. static DEFINE_MUTEX(map_lock);
  68. /* Protects register accesses and individual mappings */
  69. static DEFINE_RAW_SPINLOCK(bank_lock);
  70. static struct ipu_irq_map *src2map(unsigned int src)
  71. {
  72. int i;
  73. for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
  74. if (irq_map[i].source == src)
  75. return irq_map + i;
  76. return NULL;
  77. }
  78. static void ipu_irq_unmask(struct irq_data *d)
  79. {
  80. struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
  81. struct ipu_irq_bank *bank;
  82. uint32_t reg;
  83. unsigned long lock_flags;
  84. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  85. bank = map->bank;
  86. if (!bank) {
  87. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  88. pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
  89. return;
  90. }
  91. reg = ipu_read_reg(bank->ipu, bank->control);
  92. reg |= (1UL << (map->source & 31));
  93. ipu_write_reg(bank->ipu, reg, bank->control);
  94. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  95. }
  96. static void ipu_irq_mask(struct irq_data *d)
  97. {
  98. struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
  99. struct ipu_irq_bank *bank;
  100. uint32_t reg;
  101. unsigned long lock_flags;
  102. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  103. bank = map->bank;
  104. if (!bank) {
  105. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  106. pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
  107. return;
  108. }
  109. reg = ipu_read_reg(bank->ipu, bank->control);
  110. reg &= ~(1UL << (map->source & 31));
  111. ipu_write_reg(bank->ipu, reg, bank->control);
  112. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  113. }
  114. static void ipu_irq_ack(struct irq_data *d)
  115. {
  116. struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
  117. struct ipu_irq_bank *bank;
  118. unsigned long lock_flags;
  119. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  120. bank = map->bank;
  121. if (!bank) {
  122. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  123. pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
  124. return;
  125. }
  126. ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
  127. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  128. }
  129. /**
  130. * ipu_irq_status() - returns the current interrupt status of the specified IRQ.
  131. * @irq: interrupt line to get status for.
  132. * @return: true if the interrupt is pending/asserted or false if the
  133. * interrupt is not pending.
  134. */
  135. bool ipu_irq_status(unsigned int irq)
  136. {
  137. struct ipu_irq_map *map = irq_get_chip_data(irq);
  138. struct ipu_irq_bank *bank;
  139. unsigned long lock_flags;
  140. bool ret;
  141. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  142. bank = map->bank;
  143. ret = bank && ipu_read_reg(bank->ipu, bank->status) &
  144. (1UL << (map->source & 31));
  145. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  146. return ret;
  147. }
  148. /**
  149. * ipu_irq_map() - map an IPU interrupt source to an IRQ number
  150. * @source: interrupt source bit position (see below)
  151. * @return: mapped IRQ number or negative error code
  152. *
  153. * The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
  154. * sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
  155. * However, the source argument of this function is not the sequence number of
  156. * the possible IRQ, but rather its bit position. So, first interrupt in fourth
  157. * register has source number 96, and not 88. This makes calculations easier,
  158. * and also provides forward compatibility with any future IPU implementations
  159. * with any interrupt bit assignments.
  160. */
  161. int ipu_irq_map(unsigned int source)
  162. {
  163. int i, ret = -ENOMEM;
  164. struct ipu_irq_map *map;
  165. might_sleep();
  166. mutex_lock(&map_lock);
  167. map = src2map(source);
  168. if (map) {
  169. pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
  170. ret = -EBUSY;
  171. goto out;
  172. }
  173. for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
  174. if (irq_map[i].source < 0) {
  175. unsigned long lock_flags;
  176. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  177. irq_map[i].source = source;
  178. irq_map[i].bank = irq_bank + source / 32;
  179. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  180. ret = irq_map[i].irq;
  181. pr_debug("IPU: mapped source %u to IRQ %u\n",
  182. source, ret);
  183. break;
  184. }
  185. }
  186. out:
  187. mutex_unlock(&map_lock);
  188. if (ret < 0)
  189. pr_err("IPU: couldn't map source %u: %d\n", source, ret);
  190. return ret;
  191. }
  192. /**
  193. * ipu_irq_map() - map an IPU interrupt source to an IRQ number
  194. * @source: interrupt source bit position (see ipu_irq_map())
  195. * @return: 0 or negative error code
  196. */
  197. int ipu_irq_unmap(unsigned int source)
  198. {
  199. int i, ret = -EINVAL;
  200. might_sleep();
  201. mutex_lock(&map_lock);
  202. for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
  203. if (irq_map[i].source == source) {
  204. unsigned long lock_flags;
  205. pr_debug("IPU: unmapped source %u from IRQ %u\n",
  206. source, irq_map[i].irq);
  207. raw_spin_lock_irqsave(&bank_lock, lock_flags);
  208. irq_map[i].source = -EINVAL;
  209. irq_map[i].bank = NULL;
  210. raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
  211. ret = 0;
  212. break;
  213. }
  214. }
  215. mutex_unlock(&map_lock);
  216. return ret;
  217. }
  218. /* Chained IRQ handler for IPU function and error interrupt */
  219. static void ipu_irq_handler(struct irq_desc *desc)
  220. {
  221. struct ipu *ipu = irq_desc_get_handler_data(desc);
  222. u32 status;
  223. int i, line;
  224. for (i = 0; i < IPU_IRQ_NR_BANKS; i++) {
  225. struct ipu_irq_bank *bank = irq_bank + i;
  226. raw_spin_lock(&bank_lock);
  227. status = ipu_read_reg(ipu, bank->status);
  228. /*
  229. * Don't think we have to clear all interrupts here, they will
  230. * be acked by ->handle_irq() (handle_level_irq). However, we
  231. * might want to clear unhandled interrupts after the loop...
  232. */
  233. status &= ipu_read_reg(ipu, bank->control);
  234. raw_spin_unlock(&bank_lock);
  235. while ((line = ffs(status))) {
  236. struct ipu_irq_map *map;
  237. unsigned int irq;
  238. line--;
  239. status &= ~(1UL << line);
  240. raw_spin_lock(&bank_lock);
  241. map = src2map(32 * i + line);
  242. if (!map) {
  243. raw_spin_unlock(&bank_lock);
  244. pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
  245. line, i);
  246. continue;
  247. }
  248. irq = map->irq;
  249. raw_spin_unlock(&bank_lock);
  250. generic_handle_irq(irq);
  251. }
  252. }
  253. }
  254. static struct irq_chip ipu_irq_chip = {
  255. .name = "ipu_irq",
  256. .irq_ack = ipu_irq_ack,
  257. .irq_mask = ipu_irq_mask,
  258. .irq_unmask = ipu_irq_unmask,
  259. };
  260. /* Install the IRQ handler */
  261. int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
  262. {
  263. unsigned int irq, i;
  264. int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
  265. numa_node_id());
  266. if (irq_base < 0)
  267. return irq_base;
  268. for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
  269. irq_bank[i].ipu = ipu;
  270. for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
  271. int ret;
  272. irq = irq_base + i;
  273. ret = irq_set_chip(irq, &ipu_irq_chip);
  274. if (ret < 0)
  275. return ret;
  276. ret = irq_set_chip_data(irq, irq_map + i);
  277. if (ret < 0)
  278. return ret;
  279. irq_map[i].ipu = ipu;
  280. irq_map[i].irq = irq;
  281. irq_map[i].source = -EINVAL;
  282. irq_set_handler(irq, handle_level_irq);
  283. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  284. }
  285. irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu);
  286. irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu);
  287. ipu->irq_base = irq_base;
  288. return 0;
  289. }
  290. void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
  291. {
  292. unsigned int irq, irq_base;
  293. irq_base = ipu->irq_base;
  294. irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL);
  295. irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
  296. for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
  297. irq_set_status_flags(irq, IRQ_NOREQUEST);
  298. irq_set_chip(irq, NULL);
  299. irq_set_chip_data(irq, NULL);
  300. }
  301. }