imx-dma.c 35 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280
  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // drivers/dma/imx-dma.c
  4. //
  5. // This file contains a driver for the Freescale i.MX DMA engine
  6. // found on i.MX1/21/27
  7. //
  8. // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  9. // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
  10. #include <linux/err.h>
  11. #include <linux/init.h>
  12. #include <linux/types.h>
  13. #include <linux/mm.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/slab.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/clk.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/module.h>
  23. #include <linux/of_device.h>
  24. #include <linux/of_dma.h>
  25. #include <asm/irq.h>
  26. #include <linux/platform_data/dma-imx.h>
  27. #include "dmaengine.h"
  28. #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
  29. #define IMX_DMA_CHANNELS 16
  30. #define IMX_DMA_2D_SLOTS 2
  31. #define IMX_DMA_2D_SLOT_A 0
  32. #define IMX_DMA_2D_SLOT_B 1
  33. #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
  34. #define IMX_DMA_MEMSIZE_32 (0 << 4)
  35. #define IMX_DMA_MEMSIZE_8 (1 << 4)
  36. #define IMX_DMA_MEMSIZE_16 (2 << 4)
  37. #define IMX_DMA_TYPE_LINEAR (0 << 10)
  38. #define IMX_DMA_TYPE_2D (1 << 10)
  39. #define IMX_DMA_TYPE_FIFO (2 << 10)
  40. #define IMX_DMA_ERR_BURST (1 << 0)
  41. #define IMX_DMA_ERR_REQUEST (1 << 1)
  42. #define IMX_DMA_ERR_TRANSFER (1 << 2)
  43. #define IMX_DMA_ERR_BUFFER (1 << 3)
  44. #define IMX_DMA_ERR_TIMEOUT (1 << 4)
  45. #define DMA_DCR 0x00 /* Control Register */
  46. #define DMA_DISR 0x04 /* Interrupt status Register */
  47. #define DMA_DIMR 0x08 /* Interrupt mask Register */
  48. #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
  49. #define DMA_DRTOSR 0x10 /* Request timeout Register */
  50. #define DMA_DSESR 0x14 /* Transfer Error Status Register */
  51. #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
  52. #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
  53. #define DMA_WSRA 0x40 /* W-Size Register A */
  54. #define DMA_XSRA 0x44 /* X-Size Register A */
  55. #define DMA_YSRA 0x48 /* Y-Size Register A */
  56. #define DMA_WSRB 0x4c /* W-Size Register B */
  57. #define DMA_XSRB 0x50 /* X-Size Register B */
  58. #define DMA_YSRB 0x54 /* Y-Size Register B */
  59. #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
  60. #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
  61. #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
  62. #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
  63. #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
  64. #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
  65. #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
  66. #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
  67. #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
  68. #define DCR_DRST (1<<1)
  69. #define DCR_DEN (1<<0)
  70. #define DBTOCR_EN (1<<15)
  71. #define DBTOCR_CNT(x) ((x) & 0x7fff)
  72. #define CNTR_CNT(x) ((x) & 0xffffff)
  73. #define CCR_ACRPT (1<<14)
  74. #define CCR_DMOD_LINEAR (0x0 << 12)
  75. #define CCR_DMOD_2D (0x1 << 12)
  76. #define CCR_DMOD_FIFO (0x2 << 12)
  77. #define CCR_DMOD_EOBFIFO (0x3 << 12)
  78. #define CCR_SMOD_LINEAR (0x0 << 10)
  79. #define CCR_SMOD_2D (0x1 << 10)
  80. #define CCR_SMOD_FIFO (0x2 << 10)
  81. #define CCR_SMOD_EOBFIFO (0x3 << 10)
  82. #define CCR_MDIR_DEC (1<<9)
  83. #define CCR_MSEL_B (1<<8)
  84. #define CCR_DSIZ_32 (0x0 << 6)
  85. #define CCR_DSIZ_8 (0x1 << 6)
  86. #define CCR_DSIZ_16 (0x2 << 6)
  87. #define CCR_SSIZ_32 (0x0 << 4)
  88. #define CCR_SSIZ_8 (0x1 << 4)
  89. #define CCR_SSIZ_16 (0x2 << 4)
  90. #define CCR_REN (1<<3)
  91. #define CCR_RPT (1<<2)
  92. #define CCR_FRC (1<<1)
  93. #define CCR_CEN (1<<0)
  94. #define RTOR_EN (1<<15)
  95. #define RTOR_CLK (1<<14)
  96. #define RTOR_PSC (1<<13)
  97. enum imxdma_prep_type {
  98. IMXDMA_DESC_MEMCPY,
  99. IMXDMA_DESC_INTERLEAVED,
  100. IMXDMA_DESC_SLAVE_SG,
  101. IMXDMA_DESC_CYCLIC,
  102. };
  103. struct imx_dma_2d_config {
  104. u16 xsr;
  105. u16 ysr;
  106. u16 wsr;
  107. int count;
  108. };
  109. struct imxdma_desc {
  110. struct list_head node;
  111. struct dma_async_tx_descriptor desc;
  112. enum dma_status status;
  113. dma_addr_t src;
  114. dma_addr_t dest;
  115. size_t len;
  116. enum dma_transfer_direction direction;
  117. enum imxdma_prep_type type;
  118. /* For memcpy and interleaved */
  119. unsigned int config_port;
  120. unsigned int config_mem;
  121. /* For interleaved transfers */
  122. unsigned int x;
  123. unsigned int y;
  124. unsigned int w;
  125. /* For slave sg and cyclic */
  126. struct scatterlist *sg;
  127. unsigned int sgcount;
  128. };
  129. struct imxdma_channel {
  130. int hw_chaining;
  131. struct timer_list watchdog;
  132. struct imxdma_engine *imxdma;
  133. unsigned int channel;
  134. struct tasklet_struct dma_tasklet;
  135. struct list_head ld_free;
  136. struct list_head ld_queue;
  137. struct list_head ld_active;
  138. int descs_allocated;
  139. enum dma_slave_buswidth word_size;
  140. dma_addr_t per_address;
  141. u32 watermark_level;
  142. struct dma_chan chan;
  143. struct dma_async_tx_descriptor desc;
  144. enum dma_status status;
  145. int dma_request;
  146. struct scatterlist *sg_list;
  147. u32 ccr_from_device;
  148. u32 ccr_to_device;
  149. bool enabled_2d;
  150. int slot_2d;
  151. unsigned int irq;
  152. struct dma_slave_config config;
  153. };
  154. enum imx_dma_type {
  155. IMX1_DMA,
  156. IMX21_DMA,
  157. IMX27_DMA,
  158. };
  159. struct imxdma_engine {
  160. struct device *dev;
  161. struct dma_device dma_device;
  162. void __iomem *base;
  163. struct clk *dma_ahb;
  164. struct clk *dma_ipg;
  165. spinlock_t lock;
  166. struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
  167. struct imxdma_channel channel[IMX_DMA_CHANNELS];
  168. enum imx_dma_type devtype;
  169. unsigned int irq;
  170. unsigned int irq_err;
  171. };
  172. struct imxdma_filter_data {
  173. struct imxdma_engine *imxdma;
  174. int request;
  175. };
  176. static const struct platform_device_id imx_dma_devtype[] = {
  177. {
  178. .name = "imx1-dma",
  179. .driver_data = IMX1_DMA,
  180. }, {
  181. .name = "imx21-dma",
  182. .driver_data = IMX21_DMA,
  183. }, {
  184. .name = "imx27-dma",
  185. .driver_data = IMX27_DMA,
  186. }, {
  187. /* sentinel */
  188. }
  189. };
  190. MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
  191. static const struct of_device_id imx_dma_of_dev_id[] = {
  192. {
  193. .compatible = "fsl,imx1-dma",
  194. .data = &imx_dma_devtype[IMX1_DMA],
  195. }, {
  196. .compatible = "fsl,imx21-dma",
  197. .data = &imx_dma_devtype[IMX21_DMA],
  198. }, {
  199. .compatible = "fsl,imx27-dma",
  200. .data = &imx_dma_devtype[IMX27_DMA],
  201. }, {
  202. /* sentinel */
  203. }
  204. };
  205. MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
  206. static inline int is_imx1_dma(struct imxdma_engine *imxdma)
  207. {
  208. return imxdma->devtype == IMX1_DMA;
  209. }
  210. static inline int is_imx27_dma(struct imxdma_engine *imxdma)
  211. {
  212. return imxdma->devtype == IMX27_DMA;
  213. }
  214. static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
  215. {
  216. return container_of(chan, struct imxdma_channel, chan);
  217. }
  218. static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
  219. {
  220. struct imxdma_desc *desc;
  221. if (!list_empty(&imxdmac->ld_active)) {
  222. desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
  223. node);
  224. if (desc->type == IMXDMA_DESC_CYCLIC)
  225. return true;
  226. }
  227. return false;
  228. }
  229. static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
  230. unsigned offset)
  231. {
  232. __raw_writel(val, imxdma->base + offset);
  233. }
  234. static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
  235. {
  236. return __raw_readl(imxdma->base + offset);
  237. }
  238. static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
  239. {
  240. struct imxdma_engine *imxdma = imxdmac->imxdma;
  241. if (is_imx27_dma(imxdma))
  242. return imxdmac->hw_chaining;
  243. else
  244. return 0;
  245. }
  246. /*
  247. * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  248. */
  249. static inline void imxdma_sg_next(struct imxdma_desc *d)
  250. {
  251. struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
  252. struct imxdma_engine *imxdma = imxdmac->imxdma;
  253. struct scatterlist *sg = d->sg;
  254. size_t now;
  255. now = min_t(size_t, d->len, sg_dma_len(sg));
  256. if (d->len != IMX_DMA_LENGTH_LOOP)
  257. d->len -= now;
  258. if (d->direction == DMA_DEV_TO_MEM)
  259. imx_dmav1_writel(imxdma, sg->dma_address,
  260. DMA_DAR(imxdmac->channel));
  261. else
  262. imx_dmav1_writel(imxdma, sg->dma_address,
  263. DMA_SAR(imxdmac->channel));
  264. imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
  265. dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
  266. "size 0x%08x\n", __func__, imxdmac->channel,
  267. imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
  268. imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
  269. imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
  270. }
  271. static void imxdma_enable_hw(struct imxdma_desc *d)
  272. {
  273. struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
  274. struct imxdma_engine *imxdma = imxdmac->imxdma;
  275. int channel = imxdmac->channel;
  276. unsigned long flags;
  277. dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
  278. local_irq_save(flags);
  279. imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
  280. imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
  281. ~(1 << channel), DMA_DIMR);
  282. imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
  283. CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
  284. if (!is_imx1_dma(imxdma) &&
  285. d->sg && imxdma_hw_chain(imxdmac)) {
  286. d->sg = sg_next(d->sg);
  287. if (d->sg) {
  288. u32 tmp;
  289. imxdma_sg_next(d);
  290. tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
  291. imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
  292. DMA_CCR(channel));
  293. }
  294. }
  295. local_irq_restore(flags);
  296. }
  297. static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
  298. {
  299. struct imxdma_engine *imxdma = imxdmac->imxdma;
  300. int channel = imxdmac->channel;
  301. unsigned long flags;
  302. dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
  303. if (imxdma_hw_chain(imxdmac))
  304. del_timer(&imxdmac->watchdog);
  305. local_irq_save(flags);
  306. imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
  307. (1 << channel), DMA_DIMR);
  308. imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
  309. ~CCR_CEN, DMA_CCR(channel));
  310. imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
  311. local_irq_restore(flags);
  312. }
  313. static void imxdma_watchdog(struct timer_list *t)
  314. {
  315. struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
  316. struct imxdma_engine *imxdma = imxdmac->imxdma;
  317. int channel = imxdmac->channel;
  318. imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
  319. /* Tasklet watchdog error handler */
  320. tasklet_schedule(&imxdmac->dma_tasklet);
  321. dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
  322. imxdmac->channel);
  323. }
  324. static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
  325. {
  326. struct imxdma_engine *imxdma = dev_id;
  327. unsigned int err_mask;
  328. int i, disr;
  329. int errcode;
  330. disr = imx_dmav1_readl(imxdma, DMA_DISR);
  331. err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
  332. imx_dmav1_readl(imxdma, DMA_DRTOSR) |
  333. imx_dmav1_readl(imxdma, DMA_DSESR) |
  334. imx_dmav1_readl(imxdma, DMA_DBOSR);
  335. if (!err_mask)
  336. return IRQ_HANDLED;
  337. imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
  338. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  339. if (!(err_mask & (1 << i)))
  340. continue;
  341. errcode = 0;
  342. if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
  343. imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
  344. errcode |= IMX_DMA_ERR_BURST;
  345. }
  346. if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
  347. imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
  348. errcode |= IMX_DMA_ERR_REQUEST;
  349. }
  350. if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
  351. imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
  352. errcode |= IMX_DMA_ERR_TRANSFER;
  353. }
  354. if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
  355. imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
  356. errcode |= IMX_DMA_ERR_BUFFER;
  357. }
  358. /* Tasklet error handler */
  359. tasklet_schedule(&imxdma->channel[i].dma_tasklet);
  360. dev_warn(imxdma->dev,
  361. "DMA timeout on channel %d -%s%s%s%s\n", i,
  362. errcode & IMX_DMA_ERR_BURST ? " burst" : "",
  363. errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
  364. errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
  365. errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
  366. }
  367. return IRQ_HANDLED;
  368. }
  369. static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
  370. {
  371. struct imxdma_engine *imxdma = imxdmac->imxdma;
  372. int chno = imxdmac->channel;
  373. struct imxdma_desc *desc;
  374. unsigned long flags;
  375. spin_lock_irqsave(&imxdma->lock, flags);
  376. if (list_empty(&imxdmac->ld_active)) {
  377. spin_unlock_irqrestore(&imxdma->lock, flags);
  378. goto out;
  379. }
  380. desc = list_first_entry(&imxdmac->ld_active,
  381. struct imxdma_desc,
  382. node);
  383. spin_unlock_irqrestore(&imxdma->lock, flags);
  384. if (desc->sg) {
  385. u32 tmp;
  386. desc->sg = sg_next(desc->sg);
  387. if (desc->sg) {
  388. imxdma_sg_next(desc);
  389. tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
  390. if (imxdma_hw_chain(imxdmac)) {
  391. /* FIXME: The timeout should probably be
  392. * configurable
  393. */
  394. mod_timer(&imxdmac->watchdog,
  395. jiffies + msecs_to_jiffies(500));
  396. tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
  397. imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
  398. } else {
  399. imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
  400. DMA_CCR(chno));
  401. tmp |= CCR_CEN;
  402. }
  403. imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
  404. if (imxdma_chan_is_doing_cyclic(imxdmac))
  405. /* Tasklet progression */
  406. tasklet_schedule(&imxdmac->dma_tasklet);
  407. return;
  408. }
  409. if (imxdma_hw_chain(imxdmac)) {
  410. del_timer(&imxdmac->watchdog);
  411. return;
  412. }
  413. }
  414. out:
  415. imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
  416. /* Tasklet irq */
  417. tasklet_schedule(&imxdmac->dma_tasklet);
  418. }
  419. static irqreturn_t dma_irq_handler(int irq, void *dev_id)
  420. {
  421. struct imxdma_engine *imxdma = dev_id;
  422. int i, disr;
  423. if (!is_imx1_dma(imxdma))
  424. imxdma_err_handler(irq, dev_id);
  425. disr = imx_dmav1_readl(imxdma, DMA_DISR);
  426. dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
  427. imx_dmav1_writel(imxdma, disr, DMA_DISR);
  428. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  429. if (disr & (1 << i))
  430. dma_irq_handle_channel(&imxdma->channel[i]);
  431. }
  432. return IRQ_HANDLED;
  433. }
  434. static int imxdma_xfer_desc(struct imxdma_desc *d)
  435. {
  436. struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
  437. struct imxdma_engine *imxdma = imxdmac->imxdma;
  438. int slot = -1;
  439. int i;
  440. /* Configure and enable */
  441. switch (d->type) {
  442. case IMXDMA_DESC_INTERLEAVED:
  443. /* Try to get a free 2D slot */
  444. for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
  445. if ((imxdma->slots_2d[i].count > 0) &&
  446. ((imxdma->slots_2d[i].xsr != d->x) ||
  447. (imxdma->slots_2d[i].ysr != d->y) ||
  448. (imxdma->slots_2d[i].wsr != d->w)))
  449. continue;
  450. slot = i;
  451. break;
  452. }
  453. if (slot < 0)
  454. return -EBUSY;
  455. imxdma->slots_2d[slot].xsr = d->x;
  456. imxdma->slots_2d[slot].ysr = d->y;
  457. imxdma->slots_2d[slot].wsr = d->w;
  458. imxdma->slots_2d[slot].count++;
  459. imxdmac->slot_2d = slot;
  460. imxdmac->enabled_2d = true;
  461. if (slot == IMX_DMA_2D_SLOT_A) {
  462. d->config_mem &= ~CCR_MSEL_B;
  463. d->config_port &= ~CCR_MSEL_B;
  464. imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
  465. imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
  466. imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
  467. } else {
  468. d->config_mem |= CCR_MSEL_B;
  469. d->config_port |= CCR_MSEL_B;
  470. imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
  471. imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
  472. imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
  473. }
  474. /*
  475. * We fall-through here intentionally, since a 2D transfer is
  476. * similar to MEMCPY just adding the 2D slot configuration.
  477. */
  478. fallthrough;
  479. case IMXDMA_DESC_MEMCPY:
  480. imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
  481. imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
  482. imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
  483. DMA_CCR(imxdmac->channel));
  484. imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
  485. dev_dbg(imxdma->dev,
  486. "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
  487. __func__, imxdmac->channel,
  488. (unsigned long long)d->dest,
  489. (unsigned long long)d->src, d->len);
  490. break;
  491. /* Cyclic transfer is the same as slave_sg with special sg configuration. */
  492. case IMXDMA_DESC_CYCLIC:
  493. case IMXDMA_DESC_SLAVE_SG:
  494. if (d->direction == DMA_DEV_TO_MEM) {
  495. imx_dmav1_writel(imxdma, imxdmac->per_address,
  496. DMA_SAR(imxdmac->channel));
  497. imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
  498. DMA_CCR(imxdmac->channel));
  499. dev_dbg(imxdma->dev,
  500. "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
  501. __func__, imxdmac->channel,
  502. d->sg, d->sgcount, d->len,
  503. (unsigned long long)imxdmac->per_address);
  504. } else if (d->direction == DMA_MEM_TO_DEV) {
  505. imx_dmav1_writel(imxdma, imxdmac->per_address,
  506. DMA_DAR(imxdmac->channel));
  507. imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
  508. DMA_CCR(imxdmac->channel));
  509. dev_dbg(imxdma->dev,
  510. "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
  511. __func__, imxdmac->channel,
  512. d->sg, d->sgcount, d->len,
  513. (unsigned long long)imxdmac->per_address);
  514. } else {
  515. dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
  516. __func__, imxdmac->channel);
  517. return -EINVAL;
  518. }
  519. imxdma_sg_next(d);
  520. break;
  521. default:
  522. return -EINVAL;
  523. }
  524. imxdma_enable_hw(d);
  525. return 0;
  526. }
  527. static void imxdma_tasklet(struct tasklet_struct *t)
  528. {
  529. struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet);
  530. struct imxdma_engine *imxdma = imxdmac->imxdma;
  531. struct imxdma_desc *desc, *next_desc;
  532. unsigned long flags;
  533. spin_lock_irqsave(&imxdma->lock, flags);
  534. if (list_empty(&imxdmac->ld_active)) {
  535. /* Someone might have called terminate all */
  536. spin_unlock_irqrestore(&imxdma->lock, flags);
  537. return;
  538. }
  539. desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
  540. /* If we are dealing with a cyclic descriptor, keep it on ld_active
  541. * and dont mark the descriptor as complete.
  542. * Only in non-cyclic cases it would be marked as complete
  543. */
  544. if (imxdma_chan_is_doing_cyclic(imxdmac))
  545. goto out;
  546. else
  547. dma_cookie_complete(&desc->desc);
  548. /* Free 2D slot if it was an interleaved transfer */
  549. if (imxdmac->enabled_2d) {
  550. imxdma->slots_2d[imxdmac->slot_2d].count--;
  551. imxdmac->enabled_2d = false;
  552. }
  553. list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
  554. if (!list_empty(&imxdmac->ld_queue)) {
  555. next_desc = list_first_entry(&imxdmac->ld_queue,
  556. struct imxdma_desc, node);
  557. list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
  558. if (imxdma_xfer_desc(next_desc) < 0)
  559. dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
  560. __func__, imxdmac->channel);
  561. }
  562. out:
  563. spin_unlock_irqrestore(&imxdma->lock, flags);
  564. dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
  565. }
  566. static int imxdma_terminate_all(struct dma_chan *chan)
  567. {
  568. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  569. struct imxdma_engine *imxdma = imxdmac->imxdma;
  570. unsigned long flags;
  571. imxdma_disable_hw(imxdmac);
  572. spin_lock_irqsave(&imxdma->lock, flags);
  573. list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
  574. list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
  575. spin_unlock_irqrestore(&imxdma->lock, flags);
  576. return 0;
  577. }
  578. static int imxdma_config_write(struct dma_chan *chan,
  579. struct dma_slave_config *dmaengine_cfg,
  580. enum dma_transfer_direction direction)
  581. {
  582. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  583. struct imxdma_engine *imxdma = imxdmac->imxdma;
  584. unsigned int mode = 0;
  585. if (direction == DMA_DEV_TO_MEM) {
  586. imxdmac->per_address = dmaengine_cfg->src_addr;
  587. imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
  588. imxdmac->word_size = dmaengine_cfg->src_addr_width;
  589. } else {
  590. imxdmac->per_address = dmaengine_cfg->dst_addr;
  591. imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
  592. imxdmac->word_size = dmaengine_cfg->dst_addr_width;
  593. }
  594. switch (imxdmac->word_size) {
  595. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  596. mode = IMX_DMA_MEMSIZE_8;
  597. break;
  598. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  599. mode = IMX_DMA_MEMSIZE_16;
  600. break;
  601. default:
  602. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  603. mode = IMX_DMA_MEMSIZE_32;
  604. break;
  605. }
  606. imxdmac->hw_chaining = 0;
  607. imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
  608. ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
  609. CCR_REN;
  610. imxdmac->ccr_to_device =
  611. (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
  612. ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
  613. imx_dmav1_writel(imxdma, imxdmac->dma_request,
  614. DMA_RSSR(imxdmac->channel));
  615. /* Set burst length */
  616. imx_dmav1_writel(imxdma, imxdmac->watermark_level *
  617. imxdmac->word_size, DMA_BLR(imxdmac->channel));
  618. return 0;
  619. }
  620. static int imxdma_config(struct dma_chan *chan,
  621. struct dma_slave_config *dmaengine_cfg)
  622. {
  623. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  624. memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
  625. return 0;
  626. }
  627. static enum dma_status imxdma_tx_status(struct dma_chan *chan,
  628. dma_cookie_t cookie,
  629. struct dma_tx_state *txstate)
  630. {
  631. return dma_cookie_status(chan, cookie, txstate);
  632. }
  633. static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
  634. {
  635. struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
  636. struct imxdma_engine *imxdma = imxdmac->imxdma;
  637. dma_cookie_t cookie;
  638. unsigned long flags;
  639. spin_lock_irqsave(&imxdma->lock, flags);
  640. list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
  641. cookie = dma_cookie_assign(tx);
  642. spin_unlock_irqrestore(&imxdma->lock, flags);
  643. return cookie;
  644. }
  645. static int imxdma_alloc_chan_resources(struct dma_chan *chan)
  646. {
  647. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  648. struct imx_dma_data *data = chan->private;
  649. if (data != NULL)
  650. imxdmac->dma_request = data->dma_request;
  651. while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
  652. struct imxdma_desc *desc;
  653. desc = kzalloc(sizeof(*desc), GFP_KERNEL);
  654. if (!desc)
  655. break;
  656. memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
  657. dma_async_tx_descriptor_init(&desc->desc, chan);
  658. desc->desc.tx_submit = imxdma_tx_submit;
  659. /* txd.flags will be overwritten in prep funcs */
  660. desc->desc.flags = DMA_CTRL_ACK;
  661. desc->status = DMA_COMPLETE;
  662. list_add_tail(&desc->node, &imxdmac->ld_free);
  663. imxdmac->descs_allocated++;
  664. }
  665. if (!imxdmac->descs_allocated)
  666. return -ENOMEM;
  667. return imxdmac->descs_allocated;
  668. }
  669. static void imxdma_free_chan_resources(struct dma_chan *chan)
  670. {
  671. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  672. struct imxdma_engine *imxdma = imxdmac->imxdma;
  673. struct imxdma_desc *desc, *_desc;
  674. unsigned long flags;
  675. spin_lock_irqsave(&imxdma->lock, flags);
  676. imxdma_disable_hw(imxdmac);
  677. list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
  678. list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
  679. spin_unlock_irqrestore(&imxdma->lock, flags);
  680. list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
  681. kfree(desc);
  682. imxdmac->descs_allocated--;
  683. }
  684. INIT_LIST_HEAD(&imxdmac->ld_free);
  685. kfree(imxdmac->sg_list);
  686. imxdmac->sg_list = NULL;
  687. }
  688. static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
  689. struct dma_chan *chan, struct scatterlist *sgl,
  690. unsigned int sg_len, enum dma_transfer_direction direction,
  691. unsigned long flags, void *context)
  692. {
  693. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  694. struct scatterlist *sg;
  695. int i, dma_length = 0;
  696. struct imxdma_desc *desc;
  697. if (list_empty(&imxdmac->ld_free) ||
  698. imxdma_chan_is_doing_cyclic(imxdmac))
  699. return NULL;
  700. desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
  701. for_each_sg(sgl, sg, sg_len, i) {
  702. dma_length += sg_dma_len(sg);
  703. }
  704. imxdma_config_write(chan, &imxdmac->config, direction);
  705. switch (imxdmac->word_size) {
  706. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  707. if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
  708. return NULL;
  709. break;
  710. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  711. if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
  712. return NULL;
  713. break;
  714. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  715. break;
  716. default:
  717. return NULL;
  718. }
  719. desc->type = IMXDMA_DESC_SLAVE_SG;
  720. desc->sg = sgl;
  721. desc->sgcount = sg_len;
  722. desc->len = dma_length;
  723. desc->direction = direction;
  724. if (direction == DMA_DEV_TO_MEM) {
  725. desc->src = imxdmac->per_address;
  726. } else {
  727. desc->dest = imxdmac->per_address;
  728. }
  729. desc->desc.callback = NULL;
  730. desc->desc.callback_param = NULL;
  731. return &desc->desc;
  732. }
  733. static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
  734. struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
  735. size_t period_len, enum dma_transfer_direction direction,
  736. unsigned long flags)
  737. {
  738. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  739. struct imxdma_engine *imxdma = imxdmac->imxdma;
  740. struct imxdma_desc *desc;
  741. int i;
  742. unsigned int periods = buf_len / period_len;
  743. dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
  744. __func__, imxdmac->channel, buf_len, period_len);
  745. if (list_empty(&imxdmac->ld_free) ||
  746. imxdma_chan_is_doing_cyclic(imxdmac))
  747. return NULL;
  748. desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
  749. kfree(imxdmac->sg_list);
  750. imxdmac->sg_list = kcalloc(periods + 1,
  751. sizeof(struct scatterlist), GFP_ATOMIC);
  752. if (!imxdmac->sg_list)
  753. return NULL;
  754. sg_init_table(imxdmac->sg_list, periods);
  755. for (i = 0; i < periods; i++) {
  756. sg_assign_page(&imxdmac->sg_list[i], NULL);
  757. imxdmac->sg_list[i].offset = 0;
  758. imxdmac->sg_list[i].dma_address = dma_addr;
  759. sg_dma_len(&imxdmac->sg_list[i]) = period_len;
  760. dma_addr += period_len;
  761. }
  762. /* close the loop */
  763. sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
  764. desc->type = IMXDMA_DESC_CYCLIC;
  765. desc->sg = imxdmac->sg_list;
  766. desc->sgcount = periods;
  767. desc->len = IMX_DMA_LENGTH_LOOP;
  768. desc->direction = direction;
  769. if (direction == DMA_DEV_TO_MEM) {
  770. desc->src = imxdmac->per_address;
  771. } else {
  772. desc->dest = imxdmac->per_address;
  773. }
  774. desc->desc.callback = NULL;
  775. desc->desc.callback_param = NULL;
  776. imxdma_config_write(chan, &imxdmac->config, direction);
  777. return &desc->desc;
  778. }
  779. static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
  780. struct dma_chan *chan, dma_addr_t dest,
  781. dma_addr_t src, size_t len, unsigned long flags)
  782. {
  783. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  784. struct imxdma_engine *imxdma = imxdmac->imxdma;
  785. struct imxdma_desc *desc;
  786. dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
  787. __func__, imxdmac->channel, (unsigned long long)src,
  788. (unsigned long long)dest, len);
  789. if (list_empty(&imxdmac->ld_free) ||
  790. imxdma_chan_is_doing_cyclic(imxdmac))
  791. return NULL;
  792. desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
  793. desc->type = IMXDMA_DESC_MEMCPY;
  794. desc->src = src;
  795. desc->dest = dest;
  796. desc->len = len;
  797. desc->direction = DMA_MEM_TO_MEM;
  798. desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
  799. desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
  800. desc->desc.callback = NULL;
  801. desc->desc.callback_param = NULL;
  802. return &desc->desc;
  803. }
  804. static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
  805. struct dma_chan *chan, struct dma_interleaved_template *xt,
  806. unsigned long flags)
  807. {
  808. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  809. struct imxdma_engine *imxdma = imxdmac->imxdma;
  810. struct imxdma_desc *desc;
  811. dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
  812. " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
  813. imxdmac->channel, (unsigned long long)xt->src_start,
  814. (unsigned long long) xt->dst_start,
  815. xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
  816. xt->numf, xt->frame_size);
  817. if (list_empty(&imxdmac->ld_free) ||
  818. imxdma_chan_is_doing_cyclic(imxdmac))
  819. return NULL;
  820. if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
  821. return NULL;
  822. desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
  823. desc->type = IMXDMA_DESC_INTERLEAVED;
  824. desc->src = xt->src_start;
  825. desc->dest = xt->dst_start;
  826. desc->x = xt->sgl[0].size;
  827. desc->y = xt->numf;
  828. desc->w = xt->sgl[0].icg + desc->x;
  829. desc->len = desc->x * desc->y;
  830. desc->direction = DMA_MEM_TO_MEM;
  831. desc->config_port = IMX_DMA_MEMSIZE_32;
  832. desc->config_mem = IMX_DMA_MEMSIZE_32;
  833. if (xt->src_sgl)
  834. desc->config_mem |= IMX_DMA_TYPE_2D;
  835. if (xt->dst_sgl)
  836. desc->config_port |= IMX_DMA_TYPE_2D;
  837. desc->desc.callback = NULL;
  838. desc->desc.callback_param = NULL;
  839. return &desc->desc;
  840. }
  841. static void imxdma_issue_pending(struct dma_chan *chan)
  842. {
  843. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  844. struct imxdma_engine *imxdma = imxdmac->imxdma;
  845. struct imxdma_desc *desc;
  846. unsigned long flags;
  847. spin_lock_irqsave(&imxdma->lock, flags);
  848. if (list_empty(&imxdmac->ld_active) &&
  849. !list_empty(&imxdmac->ld_queue)) {
  850. desc = list_first_entry(&imxdmac->ld_queue,
  851. struct imxdma_desc, node);
  852. if (imxdma_xfer_desc(desc) < 0) {
  853. dev_warn(imxdma->dev,
  854. "%s: channel: %d couldn't issue DMA xfer\n",
  855. __func__, imxdmac->channel);
  856. } else {
  857. list_move_tail(imxdmac->ld_queue.next,
  858. &imxdmac->ld_active);
  859. }
  860. }
  861. spin_unlock_irqrestore(&imxdma->lock, flags);
  862. }
  863. static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
  864. {
  865. struct imxdma_filter_data *fdata = param;
  866. struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
  867. if (chan->device->dev != fdata->imxdma->dev)
  868. return false;
  869. imxdma_chan->dma_request = fdata->request;
  870. chan->private = NULL;
  871. return true;
  872. }
  873. static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
  874. struct of_dma *ofdma)
  875. {
  876. int count = dma_spec->args_count;
  877. struct imxdma_engine *imxdma = ofdma->of_dma_data;
  878. struct imxdma_filter_data fdata = {
  879. .imxdma = imxdma,
  880. };
  881. if (count != 1)
  882. return NULL;
  883. fdata.request = dma_spec->args[0];
  884. return dma_request_channel(imxdma->dma_device.cap_mask,
  885. imxdma_filter_fn, &fdata);
  886. }
  887. static int __init imxdma_probe(struct platform_device *pdev)
  888. {
  889. struct imxdma_engine *imxdma;
  890. struct resource *res;
  891. const struct of_device_id *of_id;
  892. int ret, i;
  893. int irq, irq_err;
  894. of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
  895. if (of_id)
  896. pdev->id_entry = of_id->data;
  897. imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
  898. if (!imxdma)
  899. return -ENOMEM;
  900. imxdma->dev = &pdev->dev;
  901. imxdma->devtype = pdev->id_entry->driver_data;
  902. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  903. imxdma->base = devm_ioremap_resource(&pdev->dev, res);
  904. if (IS_ERR(imxdma->base))
  905. return PTR_ERR(imxdma->base);
  906. irq = platform_get_irq(pdev, 0);
  907. if (irq < 0)
  908. return irq;
  909. imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
  910. if (IS_ERR(imxdma->dma_ipg))
  911. return PTR_ERR(imxdma->dma_ipg);
  912. imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
  913. if (IS_ERR(imxdma->dma_ahb))
  914. return PTR_ERR(imxdma->dma_ahb);
  915. ret = clk_prepare_enable(imxdma->dma_ipg);
  916. if (ret)
  917. return ret;
  918. ret = clk_prepare_enable(imxdma->dma_ahb);
  919. if (ret)
  920. goto disable_dma_ipg_clk;
  921. /* reset DMA module */
  922. imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
  923. if (is_imx1_dma(imxdma)) {
  924. ret = devm_request_irq(&pdev->dev, irq,
  925. dma_irq_handler, 0, "DMA", imxdma);
  926. if (ret) {
  927. dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
  928. goto disable_dma_ahb_clk;
  929. }
  930. imxdma->irq = irq;
  931. irq_err = platform_get_irq(pdev, 1);
  932. if (irq_err < 0) {
  933. ret = irq_err;
  934. goto disable_dma_ahb_clk;
  935. }
  936. ret = devm_request_irq(&pdev->dev, irq_err,
  937. imxdma_err_handler, 0, "DMA", imxdma);
  938. if (ret) {
  939. dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
  940. goto disable_dma_ahb_clk;
  941. }
  942. imxdma->irq_err = irq_err;
  943. }
  944. /* enable DMA module */
  945. imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
  946. /* clear all interrupts */
  947. imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
  948. /* disable interrupts */
  949. imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
  950. INIT_LIST_HEAD(&imxdma->dma_device.channels);
  951. dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
  952. dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
  953. dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
  954. dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
  955. /* Initialize 2D global parameters */
  956. for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
  957. imxdma->slots_2d[i].count = 0;
  958. spin_lock_init(&imxdma->lock);
  959. /* Initialize channel parameters */
  960. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  961. struct imxdma_channel *imxdmac = &imxdma->channel[i];
  962. if (!is_imx1_dma(imxdma)) {
  963. ret = devm_request_irq(&pdev->dev, irq + i,
  964. dma_irq_handler, 0, "DMA", imxdma);
  965. if (ret) {
  966. dev_warn(imxdma->dev, "Can't register IRQ %d "
  967. "for DMA channel %d\n",
  968. irq + i, i);
  969. goto disable_dma_ahb_clk;
  970. }
  971. imxdmac->irq = irq + i;
  972. timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
  973. }
  974. imxdmac->imxdma = imxdma;
  975. INIT_LIST_HEAD(&imxdmac->ld_queue);
  976. INIT_LIST_HEAD(&imxdmac->ld_free);
  977. INIT_LIST_HEAD(&imxdmac->ld_active);
  978. tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
  979. imxdmac->chan.device = &imxdma->dma_device;
  980. dma_cookie_init(&imxdmac->chan);
  981. imxdmac->channel = i;
  982. /* Add the channel to the DMAC list */
  983. list_add_tail(&imxdmac->chan.device_node,
  984. &imxdma->dma_device.channels);
  985. }
  986. imxdma->dma_device.dev = &pdev->dev;
  987. imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
  988. imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
  989. imxdma->dma_device.device_tx_status = imxdma_tx_status;
  990. imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
  991. imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
  992. imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
  993. imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
  994. imxdma->dma_device.device_config = imxdma_config;
  995. imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
  996. imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
  997. platform_set_drvdata(pdev, imxdma);
  998. imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
  999. dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
  1000. ret = dma_async_device_register(&imxdma->dma_device);
  1001. if (ret) {
  1002. dev_err(&pdev->dev, "unable to register\n");
  1003. goto disable_dma_ahb_clk;
  1004. }
  1005. if (pdev->dev.of_node) {
  1006. ret = of_dma_controller_register(pdev->dev.of_node,
  1007. imxdma_xlate, imxdma);
  1008. if (ret) {
  1009. dev_err(&pdev->dev, "unable to register of_dma_controller\n");
  1010. goto err_of_dma_controller;
  1011. }
  1012. }
  1013. return 0;
  1014. err_of_dma_controller:
  1015. dma_async_device_unregister(&imxdma->dma_device);
  1016. disable_dma_ahb_clk:
  1017. clk_disable_unprepare(imxdma->dma_ahb);
  1018. disable_dma_ipg_clk:
  1019. clk_disable_unprepare(imxdma->dma_ipg);
  1020. return ret;
  1021. }
  1022. static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
  1023. {
  1024. int i;
  1025. if (is_imx1_dma(imxdma)) {
  1026. disable_irq(imxdma->irq);
  1027. disable_irq(imxdma->irq_err);
  1028. }
  1029. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  1030. struct imxdma_channel *imxdmac = &imxdma->channel[i];
  1031. if (!is_imx1_dma(imxdma))
  1032. disable_irq(imxdmac->irq);
  1033. tasklet_kill(&imxdmac->dma_tasklet);
  1034. }
  1035. }
  1036. static int imxdma_remove(struct platform_device *pdev)
  1037. {
  1038. struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
  1039. imxdma_free_irq(pdev, imxdma);
  1040. dma_async_device_unregister(&imxdma->dma_device);
  1041. if (pdev->dev.of_node)
  1042. of_dma_controller_free(pdev->dev.of_node);
  1043. clk_disable_unprepare(imxdma->dma_ipg);
  1044. clk_disable_unprepare(imxdma->dma_ahb);
  1045. return 0;
  1046. }
  1047. static struct platform_driver imxdma_driver = {
  1048. .driver = {
  1049. .name = "imx-dma",
  1050. .of_match_table = imx_dma_of_dev_id,
  1051. },
  1052. .id_table = imx_dma_devtype,
  1053. .remove = imxdma_remove,
  1054. };
  1055. static int __init imxdma_module_init(void)
  1056. {
  1057. return platform_driver_probe(&imxdma_driver, imxdma_probe);
  1058. }
  1059. subsys_initcall(imxdma_module_init);
  1060. MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
  1061. MODULE_DESCRIPTION("i.MX dma driver");
  1062. MODULE_LICENSE("GPL");