submit.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
  3. #include <linux/init.h>
  4. #include <linux/kernel.h>
  5. #include <linux/module.h>
  6. #include <linux/pci.h>
  7. #include <uapi/linux/idxd.h>
  8. #include "idxd.h"
  9. #include "registers.h"
  10. static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu)
  11. {
  12. struct idxd_desc *desc;
  13. desc = wq->descs[idx];
  14. memset(desc->hw, 0, sizeof(struct dsa_hw_desc));
  15. memset(desc->completion, 0, sizeof(struct dsa_completion_record));
  16. desc->cpu = cpu;
  17. return desc;
  18. }
  19. struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)
  20. {
  21. int cpu, idx;
  22. struct idxd_device *idxd = wq->idxd;
  23. DEFINE_SBQ_WAIT(wait);
  24. struct sbq_wait_state *ws;
  25. struct sbitmap_queue *sbq;
  26. if (idxd->state != IDXD_DEV_ENABLED)
  27. return ERR_PTR(-EIO);
  28. sbq = &wq->sbq;
  29. idx = sbitmap_queue_get(sbq, &cpu);
  30. if (idx < 0) {
  31. if (optype == IDXD_OP_NONBLOCK)
  32. return ERR_PTR(-EAGAIN);
  33. } else {
  34. return __get_desc(wq, idx, cpu);
  35. }
  36. ws = &sbq->ws[0];
  37. for (;;) {
  38. sbitmap_prepare_to_wait(sbq, ws, &wait, TASK_INTERRUPTIBLE);
  39. if (signal_pending_state(TASK_INTERRUPTIBLE, current))
  40. break;
  41. idx = sbitmap_queue_get(sbq, &cpu);
  42. if (idx >= 0)
  43. break;
  44. schedule();
  45. }
  46. sbitmap_finish_wait(sbq, ws, &wait);
  47. if (idx < 0)
  48. return ERR_PTR(-EAGAIN);
  49. return __get_desc(wq, idx, cpu);
  50. }
  51. void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc)
  52. {
  53. int cpu = desc->cpu;
  54. desc->cpu = -1;
  55. sbitmap_queue_clear(&wq->sbq, desc->id, cpu);
  56. }
  57. int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
  58. {
  59. struct idxd_device *idxd = wq->idxd;
  60. int vec = desc->hw->int_handle;
  61. void __iomem *portal;
  62. if (idxd->state != IDXD_DEV_ENABLED)
  63. return -EIO;
  64. portal = wq->dportal;
  65. /*
  66. * The wmb() flushes writes to coherent DMA data before possibly
  67. * triggering a DMA read. The wmb() is necessary even on UP because
  68. * the recipient is a device.
  69. */
  70. wmb();
  71. iosubmit_cmds512(portal, desc->hw, 1);
  72. /*
  73. * Pending the descriptor to the lockless list for the irq_entry
  74. * that we designated the descriptor to.
  75. */
  76. if (desc->hw->flags & IDXD_OP_FLAG_RCI)
  77. llist_add(&desc->llnode,
  78. &idxd->irq_entries[vec].pending_llist);
  79. return 0;
  80. }