idma64.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Driver for the Intel integrated DMA 64-bit
  4. *
  5. * Copyright (C) 2015 Intel Corporation
  6. */
  7. #ifndef __DMA_IDMA64_H__
  8. #define __DMA_IDMA64_H__
  9. #include <linux/device.h>
  10. #include <linux/io.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/types.h>
  13. #include <linux/io-64-nonatomic-lo-hi.h>
  14. #include "virt-dma.h"
  15. /* Channel registers */
  16. #define IDMA64_CH_SAR 0x00 /* Source Address Register */
  17. #define IDMA64_CH_DAR 0x08 /* Destination Address Register */
  18. #define IDMA64_CH_LLP 0x10 /* Linked List Pointer */
  19. #define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */
  20. #define IDMA64_CH_CTL_HI 0x1c /* Control Register High */
  21. #define IDMA64_CH_SSTAT 0x20
  22. #define IDMA64_CH_DSTAT 0x28
  23. #define IDMA64_CH_SSTATAR 0x30
  24. #define IDMA64_CH_DSTATAR 0x38
  25. #define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */
  26. #define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */
  27. #define IDMA64_CH_SGR 0x48
  28. #define IDMA64_CH_DSR 0x50
  29. #define IDMA64_CH_LENGTH 0x58
  30. /* Bitfields in CTL_LO */
  31. #define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */
  32. #define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */
  33. #define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4)
  34. #define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */
  35. #define IDMA64C_CTLL_DST_FIX (1 << 8)
  36. #define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */
  37. #define IDMA64C_CTLL_SRC_FIX (1 << 10)
  38. #define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */
  39. #define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14)
  40. #define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
  41. #define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
  42. #define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
  43. #define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */
  44. /* Bitfields in CTL_HI */
  45. #define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1)
  46. #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & IDMA64C_CTLH_BLOCK_TS_MASK)
  47. #define IDMA64C_CTLH_DONE (1 << 17)
  48. /* Bitfields in CFG_LO */
  49. #define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
  50. #define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
  51. #define IDMA64C_CFGL_CH_SUSP (1 << 8)
  52. #define IDMA64C_CFGL_FIFO_EMPTY (1 << 9)
  53. #define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
  54. #define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
  55. #define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
  56. /* Bitfields in CFG_HI */
  57. #define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */
  58. #define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */
  59. #define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
  60. #define IDMA64C_CFGH_WR_ISSUE_THD(x) ((x) << 18)
  61. /* Interrupt registers */
  62. #define IDMA64_INT_XFER 0x00
  63. #define IDMA64_INT_BLOCK 0x08
  64. #define IDMA64_INT_SRC_TRAN 0x10
  65. #define IDMA64_INT_DST_TRAN 0x18
  66. #define IDMA64_INT_ERROR 0x20
  67. #define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */
  68. #define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */
  69. #define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */
  70. #define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */
  71. /* Common registers */
  72. #define IDMA64_STATUS_INT 0x360 /* r */
  73. #define IDMA64_CFG 0x398
  74. #define IDMA64_CH_EN 0x3a0
  75. /* Bitfields in CFG */
  76. #define IDMA64_CFG_DMA_EN (1 << 0)
  77. /* Hardware descriptor for Linked LIst transfers */
  78. struct idma64_lli {
  79. u64 sar;
  80. u64 dar;
  81. u64 llp;
  82. u32 ctllo;
  83. u32 ctlhi;
  84. u32 sstat;
  85. u32 dstat;
  86. };
  87. struct idma64_hw_desc {
  88. struct idma64_lli *lli;
  89. dma_addr_t llp;
  90. dma_addr_t phys;
  91. unsigned int len;
  92. };
  93. struct idma64_desc {
  94. struct virt_dma_desc vdesc;
  95. enum dma_transfer_direction direction;
  96. struct idma64_hw_desc *hw;
  97. unsigned int ndesc;
  98. size_t length;
  99. enum dma_status status;
  100. };
  101. static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
  102. {
  103. return container_of(vdesc, struct idma64_desc, vdesc);
  104. }
  105. struct idma64_chan {
  106. struct virt_dma_chan vchan;
  107. void __iomem *regs;
  108. /* hardware configuration */
  109. enum dma_transfer_direction direction;
  110. unsigned int mask;
  111. struct dma_slave_config config;
  112. void *pool;
  113. struct idma64_desc *desc;
  114. };
  115. static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
  116. {
  117. return container_of(chan, struct idma64_chan, vchan.chan);
  118. }
  119. #define channel_set_bit(idma64, reg, mask) \
  120. dma_writel(idma64, reg, ((mask) << 8) | (mask))
  121. #define channel_clear_bit(idma64, reg, mask) \
  122. dma_writel(idma64, reg, ((mask) << 8) | 0)
  123. static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
  124. {
  125. return readl(idma64c->regs + offset);
  126. }
  127. static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
  128. u32 value)
  129. {
  130. writel(value, idma64c->regs + offset);
  131. }
  132. #define channel_readl(idma64c, reg) \
  133. idma64c_readl(idma64c, IDMA64_CH_##reg)
  134. #define channel_writel(idma64c, reg, value) \
  135. idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
  136. static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
  137. {
  138. return lo_hi_readq(idma64c->regs + offset);
  139. }
  140. static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
  141. u64 value)
  142. {
  143. lo_hi_writeq(value, idma64c->regs + offset);
  144. }
  145. #define channel_readq(idma64c, reg) \
  146. idma64c_readq(idma64c, IDMA64_CH_##reg)
  147. #define channel_writeq(idma64c, reg, value) \
  148. idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
  149. struct idma64 {
  150. struct dma_device dma;
  151. void __iomem *regs;
  152. /* channels */
  153. unsigned short all_chan_mask;
  154. struct idma64_chan *chan;
  155. };
  156. static inline struct idma64 *to_idma64(struct dma_device *ddev)
  157. {
  158. return container_of(ddev, struct idma64, dma);
  159. }
  160. static inline u32 idma64_readl(struct idma64 *idma64, int offset)
  161. {
  162. return readl(idma64->regs + offset);
  163. }
  164. static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
  165. {
  166. writel(value, idma64->regs + offset);
  167. }
  168. #define dma_readl(idma64, reg) \
  169. idma64_readl(idma64, IDMA64_##reg)
  170. #define dma_writel(idma64, reg, value) \
  171. idma64_writel(idma64, IDMA64_##reg, (value))
  172. /**
  173. * struct idma64_chip - representation of iDMA 64-bit controller hardware
  174. * @dev: struct device of the DMA controller
  175. * @sysdev: struct device of the physical device that does DMA
  176. * @irq: irq line
  177. * @regs: memory mapped I/O space
  178. * @idma64: struct idma64 that is filed by idma64_probe()
  179. */
  180. struct idma64_chip {
  181. struct device *dev;
  182. struct device *sysdev;
  183. int irq;
  184. void __iomem *regs;
  185. struct idma64 *idma64;
  186. };
  187. #endif /* __DMA_IDMA64_H__ */