fsldma.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  4. *
  5. * Author:
  6. * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  7. * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
  8. */
  9. #ifndef __DMA_FSLDMA_H
  10. #define __DMA_FSLDMA_H
  11. #include <linux/device.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/dmaengine.h>
  14. /* Define data structures needed by Freescale
  15. * MPC8540 and MPC8349 DMA controller.
  16. */
  17. #define FSL_DMA_MR_CS 0x00000001
  18. #define FSL_DMA_MR_CC 0x00000002
  19. #define FSL_DMA_MR_CA 0x00000008
  20. #define FSL_DMA_MR_EIE 0x00000040
  21. #define FSL_DMA_MR_XFE 0x00000020
  22. #define FSL_DMA_MR_EOLNIE 0x00000100
  23. #define FSL_DMA_MR_EOLSIE 0x00000080
  24. #define FSL_DMA_MR_EOSIE 0x00000200
  25. #define FSL_DMA_MR_CDSM 0x00000010
  26. #define FSL_DMA_MR_CTM 0x00000004
  27. #define FSL_DMA_MR_EMP_EN 0x00200000
  28. #define FSL_DMA_MR_EMS_EN 0x00040000
  29. #define FSL_DMA_MR_DAHE 0x00002000
  30. #define FSL_DMA_MR_SAHE 0x00001000
  31. #define FSL_DMA_MR_SAHTS_MASK 0x0000C000
  32. #define FSL_DMA_MR_DAHTS_MASK 0x00030000
  33. #define FSL_DMA_MR_BWC_MASK 0x0f000000
  34. /*
  35. * Bandwidth/pause control determines how many bytes a given
  36. * channel is allowed to transfer before the DMA engine pauses
  37. * the current channel and switches to the next channel
  38. */
  39. #define FSL_DMA_MR_BWC 0x0A000000
  40. /* Special MR definition for MPC8349 */
  41. #define FSL_DMA_MR_EOTIE 0x00000080
  42. #define FSL_DMA_MR_PRC_RM 0x00000800
  43. #define FSL_DMA_SR_CH 0x00000020
  44. #define FSL_DMA_SR_PE 0x00000010
  45. #define FSL_DMA_SR_CB 0x00000004
  46. #define FSL_DMA_SR_TE 0x00000080
  47. #define FSL_DMA_SR_EOSI 0x00000002
  48. #define FSL_DMA_SR_EOLSI 0x00000001
  49. #define FSL_DMA_SR_EOCDI 0x00000001
  50. #define FSL_DMA_SR_EOLNI 0x00000008
  51. #define FSL_DMA_SATR_SBPATMU 0x20000000
  52. #define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
  53. #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
  54. #define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
  55. #define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
  56. #define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
  57. #define FSL_DMA_DATR_DBPATMU 0x20000000
  58. #define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
  59. #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
  60. #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
  61. #define FSL_DMA_EOL ((u64)0x1)
  62. #define FSL_DMA_SNEN ((u64)0x10)
  63. #define FSL_DMA_EOSIE 0x8
  64. #define FSL_DMA_NLDA_MASK (~(u64)0x1f)
  65. #define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
  66. #define FSL_DMA_DGSR_TE 0x80
  67. #define FSL_DMA_DGSR_CH 0x20
  68. #define FSL_DMA_DGSR_PE 0x10
  69. #define FSL_DMA_DGSR_EOLNI 0x08
  70. #define FSL_DMA_DGSR_CB 0x04
  71. #define FSL_DMA_DGSR_EOSI 0x02
  72. #define FSL_DMA_DGSR_EOLSI 0x01
  73. #define FSL_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  74. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  75. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  76. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  77. typedef u64 __bitwise v64;
  78. typedef u32 __bitwise v32;
  79. struct fsl_dma_ld_hw {
  80. v64 src_addr;
  81. v64 dst_addr;
  82. v64 next_ln_addr;
  83. v32 count;
  84. v32 reserve;
  85. } __attribute__((aligned(32)));
  86. struct fsl_desc_sw {
  87. struct fsl_dma_ld_hw hw;
  88. struct list_head node;
  89. struct list_head tx_list;
  90. struct dma_async_tx_descriptor async_tx;
  91. } __attribute__((aligned(32)));
  92. struct fsldma_chan_regs {
  93. u32 mr; /* 0x00 - Mode Register */
  94. u32 sr; /* 0x04 - Status Register */
  95. u64 cdar; /* 0x08 - Current descriptor address register */
  96. u64 sar; /* 0x10 - Source Address Register */
  97. u64 dar; /* 0x18 - Destination Address Register */
  98. u32 bcr; /* 0x20 - Byte Count Register */
  99. u64 ndar; /* 0x24 - Next Descriptor Address Register */
  100. };
  101. struct fsldma_chan;
  102. #define FSL_DMA_MAX_CHANS_PER_DEVICE 8
  103. struct fsldma_device {
  104. void __iomem *regs; /* DGSR register base */
  105. struct device *dev;
  106. struct dma_device common;
  107. struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
  108. u32 feature; /* The same as DMA channels */
  109. int irq; /* Channel IRQ */
  110. };
  111. /* Define macros for fsldma_chan->feature property */
  112. #define FSL_DMA_LITTLE_ENDIAN 0x00000000
  113. #define FSL_DMA_BIG_ENDIAN 0x00000001
  114. #define FSL_DMA_IP_MASK 0x00000ff0
  115. #define FSL_DMA_IP_85XX 0x00000010
  116. #define FSL_DMA_IP_83XX 0x00000020
  117. #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
  118. #define FSL_DMA_CHAN_START_EXT 0x00002000
  119. #ifdef CONFIG_PM
  120. struct fsldma_chan_regs_save {
  121. u32 mr;
  122. };
  123. enum fsldma_pm_state {
  124. RUNNING = 0,
  125. SUSPENDED,
  126. };
  127. #endif
  128. struct fsldma_chan {
  129. char name[8]; /* Channel name */
  130. struct fsldma_chan_regs __iomem *regs;
  131. spinlock_t desc_lock; /* Descriptor operation lock */
  132. /*
  133. * Descriptors which are queued to run, but have not yet been
  134. * submitted to the hardware for execution
  135. */
  136. struct list_head ld_pending;
  137. /*
  138. * Descriptors which are currently being executed by the hardware
  139. */
  140. struct list_head ld_running;
  141. /*
  142. * Descriptors which have finished execution by the hardware. These
  143. * descriptors have already had their cleanup actions run. They are
  144. * waiting for the ACK bit to be set by the async_tx API.
  145. */
  146. struct list_head ld_completed; /* Link descriptors queue */
  147. struct dma_chan common; /* DMA common channel */
  148. struct dma_pool *desc_pool; /* Descriptors pool */
  149. struct device *dev; /* Channel device */
  150. int irq; /* Channel IRQ */
  151. int id; /* Raw id of this channel */
  152. struct tasklet_struct tasklet;
  153. u32 feature;
  154. bool idle; /* DMA controller is idle */
  155. #ifdef CONFIG_PM
  156. struct fsldma_chan_regs_save regs_save;
  157. enum fsldma_pm_state pm_state;
  158. #endif
  159. void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
  160. void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
  161. void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
  162. void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
  163. void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
  164. };
  165. #define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
  166. #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
  167. #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
  168. #ifdef CONFIG_PPC
  169. #define fsl_ioread32(p) in_le32(p)
  170. #define fsl_ioread32be(p) in_be32(p)
  171. #define fsl_iowrite32(v, p) out_le32(p, v)
  172. #define fsl_iowrite32be(v, p) out_be32(p, v)
  173. #ifdef __powerpc64__
  174. #define fsl_ioread64(p) in_le64(p)
  175. #define fsl_ioread64be(p) in_be64(p)
  176. #define fsl_iowrite64(v, p) out_le64(p, v)
  177. #define fsl_iowrite64be(v, p) out_be64(p, v)
  178. #else
  179. static u64 fsl_ioread64(const u64 __iomem *addr)
  180. {
  181. u32 val_lo = in_le32((u32 __iomem *)addr);
  182. u32 val_hi = in_le32((u32 __iomem *)addr + 1);
  183. return ((u64)val_hi << 32) + val_lo;
  184. }
  185. static void fsl_iowrite64(u64 val, u64 __iomem *addr)
  186. {
  187. out_le32((u32 __iomem *)addr + 1, val >> 32);
  188. out_le32((u32 __iomem *)addr, (u32)val);
  189. }
  190. static u64 fsl_ioread64be(const u64 __iomem *addr)
  191. {
  192. u32 val_hi = in_be32((u32 __iomem *)addr);
  193. u32 val_lo = in_be32((u32 __iomem *)addr + 1);
  194. return ((u64)val_hi << 32) + val_lo;
  195. }
  196. static void fsl_iowrite64be(u64 val, u64 __iomem *addr)
  197. {
  198. out_be32((u32 __iomem *)addr, val >> 32);
  199. out_be32((u32 __iomem *)addr + 1, (u32)val);
  200. }
  201. #endif
  202. #endif
  203. #if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
  204. #define fsl_ioread32(p) ioread32(p)
  205. #define fsl_ioread32be(p) ioread32be(p)
  206. #define fsl_iowrite32(v, p) iowrite32(v, p)
  207. #define fsl_iowrite32be(v, p) iowrite32be(v, p)
  208. #define fsl_ioread64(p) ioread64(p)
  209. #define fsl_ioread64be(p) ioread64be(p)
  210. #define fsl_iowrite64(v, p) iowrite64(v, p)
  211. #define fsl_iowrite64be(v, p) iowrite64be(v, p)
  212. #endif
  213. #define FSL_DMA_IN(fsl_dma, addr, width) \
  214. (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \
  215. fsl_ioread##width##be(addr) : fsl_ioread##width(addr))
  216. #define FSL_DMA_OUT(fsl_dma, addr, val, width) \
  217. (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \
  218. fsl_iowrite##width##be(val, addr) : fsl_iowrite \
  219. ##width(val, addr))
  220. #define DMA_TO_CPU(fsl_chan, d, width) \
  221. (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
  222. be##width##_to_cpu((__force __be##width)(v##width)d) : \
  223. le##width##_to_cpu((__force __le##width)(v##width)d))
  224. #define CPU_TO_DMA(fsl_chan, c, width) \
  225. (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
  226. (__force v##width)cpu_to_be##width(c) : \
  227. (__force v##width)cpu_to_le##width(c))
  228. #endif /* __DMA_FSLDMA_H */