fsldma.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale MPC85xx, MPC83xx DMA Engine support
  4. *
  5. * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  6. *
  7. * Author:
  8. * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  9. * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
  10. *
  11. * Description:
  12. * DMA engine driver for Freescale MPC8540 DMA controller, which is
  13. * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
  14. * The support for MPC8349 DMA controller is also added.
  15. *
  16. * This driver instructs the DMA controller to issue the PCI Read Multiple
  17. * command for PCI read operations, instead of using the default PCI Read Line
  18. * command. Please be aware that this setting may result in read pre-fetching
  19. * on some platforms.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/slab.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/dmaengine.h>
  27. #include <linux/delay.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/dmapool.h>
  30. #include <linux/of_address.h>
  31. #include <linux/of_irq.h>
  32. #include <linux/of_platform.h>
  33. #include <linux/fsldma.h>
  34. #include "dmaengine.h"
  35. #include "fsldma.h"
  36. #define chan_dbg(chan, fmt, arg...) \
  37. dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
  38. #define chan_err(chan, fmt, arg...) \
  39. dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
  40. static const char msg_ld_oom[] = "No free memory for link descriptor";
  41. /*
  42. * Register Helpers
  43. */
  44. static void set_sr(struct fsldma_chan *chan, u32 val)
  45. {
  46. FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
  47. }
  48. static u32 get_sr(struct fsldma_chan *chan)
  49. {
  50. return FSL_DMA_IN(chan, &chan->regs->sr, 32);
  51. }
  52. static void set_mr(struct fsldma_chan *chan, u32 val)
  53. {
  54. FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
  55. }
  56. static u32 get_mr(struct fsldma_chan *chan)
  57. {
  58. return FSL_DMA_IN(chan, &chan->regs->mr, 32);
  59. }
  60. static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
  61. {
  62. FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
  63. }
  64. static dma_addr_t get_cdar(struct fsldma_chan *chan)
  65. {
  66. return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
  67. }
  68. static void set_bcr(struct fsldma_chan *chan, u32 val)
  69. {
  70. FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
  71. }
  72. static u32 get_bcr(struct fsldma_chan *chan)
  73. {
  74. return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
  75. }
  76. /*
  77. * Descriptor Helpers
  78. */
  79. static void set_desc_cnt(struct fsldma_chan *chan,
  80. struct fsl_dma_ld_hw *hw, u32 count)
  81. {
  82. hw->count = CPU_TO_DMA(chan, count, 32);
  83. }
  84. static void set_desc_src(struct fsldma_chan *chan,
  85. struct fsl_dma_ld_hw *hw, dma_addr_t src)
  86. {
  87. u64 snoop_bits;
  88. snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  89. ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
  90. hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
  91. }
  92. static void set_desc_dst(struct fsldma_chan *chan,
  93. struct fsl_dma_ld_hw *hw, dma_addr_t dst)
  94. {
  95. u64 snoop_bits;
  96. snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  97. ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
  98. hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
  99. }
  100. static void set_desc_next(struct fsldma_chan *chan,
  101. struct fsl_dma_ld_hw *hw, dma_addr_t next)
  102. {
  103. u64 snoop_bits;
  104. snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
  105. ? FSL_DMA_SNEN : 0;
  106. hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
  107. }
  108. static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
  109. {
  110. u64 snoop_bits;
  111. snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
  112. ? FSL_DMA_SNEN : 0;
  113. desc->hw.next_ln_addr = CPU_TO_DMA(chan,
  114. DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
  115. | snoop_bits, 64);
  116. }
  117. /*
  118. * DMA Engine Hardware Control Helpers
  119. */
  120. static void dma_init(struct fsldma_chan *chan)
  121. {
  122. /* Reset the channel */
  123. set_mr(chan, 0);
  124. switch (chan->feature & FSL_DMA_IP_MASK) {
  125. case FSL_DMA_IP_85XX:
  126. /* Set the channel to below modes:
  127. * EIE - Error interrupt enable
  128. * EOLNIE - End of links interrupt enable
  129. * BWC - Bandwidth sharing among channels
  130. */
  131. set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
  132. | FSL_DMA_MR_EOLNIE);
  133. break;
  134. case FSL_DMA_IP_83XX:
  135. /* Set the channel to below modes:
  136. * EOTIE - End-of-transfer interrupt enable
  137. * PRC_RM - PCI read multiple
  138. */
  139. set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
  140. break;
  141. }
  142. }
  143. static int dma_is_idle(struct fsldma_chan *chan)
  144. {
  145. u32 sr = get_sr(chan);
  146. return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
  147. }
  148. /*
  149. * Start the DMA controller
  150. *
  151. * Preconditions:
  152. * - the CDAR register must point to the start descriptor
  153. * - the MRn[CS] bit must be cleared
  154. */
  155. static void dma_start(struct fsldma_chan *chan)
  156. {
  157. u32 mode;
  158. mode = get_mr(chan);
  159. if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
  160. set_bcr(chan, 0);
  161. mode |= FSL_DMA_MR_EMP_EN;
  162. } else {
  163. mode &= ~FSL_DMA_MR_EMP_EN;
  164. }
  165. if (chan->feature & FSL_DMA_CHAN_START_EXT) {
  166. mode |= FSL_DMA_MR_EMS_EN;
  167. } else {
  168. mode &= ~FSL_DMA_MR_EMS_EN;
  169. mode |= FSL_DMA_MR_CS;
  170. }
  171. set_mr(chan, mode);
  172. }
  173. static void dma_halt(struct fsldma_chan *chan)
  174. {
  175. u32 mode;
  176. int i;
  177. /* read the mode register */
  178. mode = get_mr(chan);
  179. /*
  180. * The 85xx controller supports channel abort, which will stop
  181. * the current transfer. On 83xx, this bit is the transfer error
  182. * mask bit, which should not be changed.
  183. */
  184. if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
  185. mode |= FSL_DMA_MR_CA;
  186. set_mr(chan, mode);
  187. mode &= ~FSL_DMA_MR_CA;
  188. }
  189. /* stop the DMA controller */
  190. mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
  191. set_mr(chan, mode);
  192. /* wait for the DMA controller to become idle */
  193. for (i = 0; i < 100; i++) {
  194. if (dma_is_idle(chan))
  195. return;
  196. udelay(10);
  197. }
  198. if (!dma_is_idle(chan))
  199. chan_err(chan, "DMA halt timeout!\n");
  200. }
  201. /**
  202. * fsl_chan_set_src_loop_size - Set source address hold transfer size
  203. * @chan : Freescale DMA channel
  204. * @size : Address loop size, 0 for disable loop
  205. *
  206. * The set source address hold transfer size. The source
  207. * address hold or loop transfer size is when the DMA transfer
  208. * data from source address (SA), if the loop size is 4, the DMA will
  209. * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
  210. * SA + 1 ... and so on.
  211. */
  212. static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
  213. {
  214. u32 mode;
  215. mode = get_mr(chan);
  216. switch (size) {
  217. case 0:
  218. mode &= ~FSL_DMA_MR_SAHE;
  219. break;
  220. case 1:
  221. case 2:
  222. case 4:
  223. case 8:
  224. mode &= ~FSL_DMA_MR_SAHTS_MASK;
  225. mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
  226. break;
  227. }
  228. set_mr(chan, mode);
  229. }
  230. /**
  231. * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
  232. * @chan : Freescale DMA channel
  233. * @size : Address loop size, 0 for disable loop
  234. *
  235. * The set destination address hold transfer size. The destination
  236. * address hold or loop transfer size is when the DMA transfer
  237. * data to destination address (TA), if the loop size is 4, the DMA will
  238. * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
  239. * TA + 1 ... and so on.
  240. */
  241. static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
  242. {
  243. u32 mode;
  244. mode = get_mr(chan);
  245. switch (size) {
  246. case 0:
  247. mode &= ~FSL_DMA_MR_DAHE;
  248. break;
  249. case 1:
  250. case 2:
  251. case 4:
  252. case 8:
  253. mode &= ~FSL_DMA_MR_DAHTS_MASK;
  254. mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
  255. break;
  256. }
  257. set_mr(chan, mode);
  258. }
  259. /**
  260. * fsl_chan_set_request_count - Set DMA Request Count for external control
  261. * @chan : Freescale DMA channel
  262. * @size : Number of bytes to transfer in a single request
  263. *
  264. * The Freescale DMA channel can be controlled by the external signal DREQ#.
  265. * The DMA request count is how many bytes are allowed to transfer before
  266. * pausing the channel, after which a new assertion of DREQ# resumes channel
  267. * operation.
  268. *
  269. * A size of 0 disables external pause control. The maximum size is 1024.
  270. */
  271. static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
  272. {
  273. u32 mode;
  274. BUG_ON(size > 1024);
  275. mode = get_mr(chan);
  276. mode &= ~FSL_DMA_MR_BWC_MASK;
  277. mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK;
  278. set_mr(chan, mode);
  279. }
  280. /**
  281. * fsl_chan_toggle_ext_pause - Toggle channel external pause status
  282. * @chan : Freescale DMA channel
  283. * @enable : 0 is disabled, 1 is enabled.
  284. *
  285. * The Freescale DMA channel can be controlled by the external signal DREQ#.
  286. * The DMA Request Count feature should be used in addition to this feature
  287. * to set the number of bytes to transfer before pausing the channel.
  288. */
  289. static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
  290. {
  291. if (enable)
  292. chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
  293. else
  294. chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
  295. }
  296. /**
  297. * fsl_chan_toggle_ext_start - Toggle channel external start status
  298. * @chan : Freescale DMA channel
  299. * @enable : 0 is disabled, 1 is enabled.
  300. *
  301. * If enable the external start, the channel can be started by an
  302. * external DMA start pin. So the dma_start() does not start the
  303. * transfer immediately. The DMA channel will wait for the
  304. * control pin asserted.
  305. */
  306. static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
  307. {
  308. if (enable)
  309. chan->feature |= FSL_DMA_CHAN_START_EXT;
  310. else
  311. chan->feature &= ~FSL_DMA_CHAN_START_EXT;
  312. }
  313. int fsl_dma_external_start(struct dma_chan *dchan, int enable)
  314. {
  315. struct fsldma_chan *chan;
  316. if (!dchan)
  317. return -EINVAL;
  318. chan = to_fsl_chan(dchan);
  319. fsl_chan_toggle_ext_start(chan, enable);
  320. return 0;
  321. }
  322. EXPORT_SYMBOL_GPL(fsl_dma_external_start);
  323. static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
  324. {
  325. struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
  326. if (list_empty(&chan->ld_pending))
  327. goto out_splice;
  328. /*
  329. * Add the hardware descriptor to the chain of hardware descriptors
  330. * that already exists in memory.
  331. *
  332. * This will un-set the EOL bit of the existing transaction, and the
  333. * last link in this transaction will become the EOL descriptor.
  334. */
  335. set_desc_next(chan, &tail->hw, desc->async_tx.phys);
  336. /*
  337. * Add the software descriptor and all children to the list
  338. * of pending transactions
  339. */
  340. out_splice:
  341. list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
  342. }
  343. static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
  344. {
  345. struct fsldma_chan *chan = to_fsl_chan(tx->chan);
  346. struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
  347. struct fsl_desc_sw *child;
  348. dma_cookie_t cookie = -EINVAL;
  349. spin_lock_bh(&chan->desc_lock);
  350. #ifdef CONFIG_PM
  351. if (unlikely(chan->pm_state != RUNNING)) {
  352. chan_dbg(chan, "cannot submit due to suspend\n");
  353. spin_unlock_bh(&chan->desc_lock);
  354. return -1;
  355. }
  356. #endif
  357. /*
  358. * assign cookies to all of the software descriptors
  359. * that make up this transaction
  360. */
  361. list_for_each_entry(child, &desc->tx_list, node) {
  362. cookie = dma_cookie_assign(&child->async_tx);
  363. }
  364. /* put this transaction onto the tail of the pending queue */
  365. append_ld_queue(chan, desc);
  366. spin_unlock_bh(&chan->desc_lock);
  367. return cookie;
  368. }
  369. /**
  370. * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
  371. * @chan : Freescale DMA channel
  372. * @desc: descriptor to be freed
  373. */
  374. static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
  375. struct fsl_desc_sw *desc)
  376. {
  377. list_del(&desc->node);
  378. chan_dbg(chan, "LD %p free\n", desc);
  379. dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
  380. }
  381. /**
  382. * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
  383. * @chan : Freescale DMA channel
  384. *
  385. * Return - The descriptor allocated. NULL for failed.
  386. */
  387. static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
  388. {
  389. struct fsl_desc_sw *desc;
  390. dma_addr_t pdesc;
  391. desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
  392. if (!desc) {
  393. chan_dbg(chan, "out of memory for link descriptor\n");
  394. return NULL;
  395. }
  396. INIT_LIST_HEAD(&desc->tx_list);
  397. dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
  398. desc->async_tx.tx_submit = fsl_dma_tx_submit;
  399. desc->async_tx.phys = pdesc;
  400. chan_dbg(chan, "LD %p allocated\n", desc);
  401. return desc;
  402. }
  403. /**
  404. * fsldma_clean_completed_descriptor - free all descriptors which
  405. * has been completed and acked
  406. * @chan: Freescale DMA channel
  407. *
  408. * This function is used on all completed and acked descriptors.
  409. * All descriptors should only be freed in this function.
  410. */
  411. static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
  412. {
  413. struct fsl_desc_sw *desc, *_desc;
  414. /* Run the callback for each descriptor, in order */
  415. list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
  416. if (async_tx_test_ack(&desc->async_tx))
  417. fsl_dma_free_descriptor(chan, desc);
  418. }
  419. /**
  420. * fsldma_run_tx_complete_actions - cleanup a single link descriptor
  421. * @chan: Freescale DMA channel
  422. * @desc: descriptor to cleanup and free
  423. * @cookie: Freescale DMA transaction identifier
  424. *
  425. * This function is used on a descriptor which has been executed by the DMA
  426. * controller. It will run any callbacks, submit any dependencies.
  427. */
  428. static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
  429. struct fsl_desc_sw *desc, dma_cookie_t cookie)
  430. {
  431. struct dma_async_tx_descriptor *txd = &desc->async_tx;
  432. dma_cookie_t ret = cookie;
  433. BUG_ON(txd->cookie < 0);
  434. if (txd->cookie > 0) {
  435. ret = txd->cookie;
  436. dma_descriptor_unmap(txd);
  437. /* Run the link descriptor callback function */
  438. dmaengine_desc_get_callback_invoke(txd, NULL);
  439. }
  440. /* Run any dependencies */
  441. dma_run_dependencies(txd);
  442. return ret;
  443. }
  444. /**
  445. * fsldma_clean_running_descriptor - move the completed descriptor from
  446. * ld_running to ld_completed
  447. * @chan: Freescale DMA channel
  448. * @desc: the descriptor which is completed
  449. *
  450. * Free the descriptor directly if acked by async_tx api, or move it to
  451. * queue ld_completed.
  452. */
  453. static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
  454. struct fsl_desc_sw *desc)
  455. {
  456. /* Remove from the list of transactions */
  457. list_del(&desc->node);
  458. /*
  459. * the client is allowed to attach dependent operations
  460. * until 'ack' is set
  461. */
  462. if (!async_tx_test_ack(&desc->async_tx)) {
  463. /*
  464. * Move this descriptor to the list of descriptors which is
  465. * completed, but still awaiting the 'ack' bit to be set.
  466. */
  467. list_add_tail(&desc->node, &chan->ld_completed);
  468. return;
  469. }
  470. dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
  471. }
  472. /**
  473. * fsl_chan_xfer_ld_queue - transfer any pending transactions
  474. * @chan : Freescale DMA channel
  475. *
  476. * HARDWARE STATE: idle
  477. * LOCKING: must hold chan->desc_lock
  478. */
  479. static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
  480. {
  481. struct fsl_desc_sw *desc;
  482. /*
  483. * If the list of pending descriptors is empty, then we
  484. * don't need to do any work at all
  485. */
  486. if (list_empty(&chan->ld_pending)) {
  487. chan_dbg(chan, "no pending LDs\n");
  488. return;
  489. }
  490. /*
  491. * The DMA controller is not idle, which means that the interrupt
  492. * handler will start any queued transactions when it runs after
  493. * this transaction finishes
  494. */
  495. if (!chan->idle) {
  496. chan_dbg(chan, "DMA controller still busy\n");
  497. return;
  498. }
  499. /*
  500. * If there are some link descriptors which have not been
  501. * transferred, we need to start the controller
  502. */
  503. /*
  504. * Move all elements from the queue of pending transactions
  505. * onto the list of running transactions
  506. */
  507. chan_dbg(chan, "idle, starting controller\n");
  508. desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
  509. list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
  510. /*
  511. * The 85xx DMA controller doesn't clear the channel start bit
  512. * automatically at the end of a transfer. Therefore we must clear
  513. * it in software before starting the transfer.
  514. */
  515. if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
  516. u32 mode;
  517. mode = get_mr(chan);
  518. mode &= ~FSL_DMA_MR_CS;
  519. set_mr(chan, mode);
  520. }
  521. /*
  522. * Program the descriptor's address into the DMA controller,
  523. * then start the DMA transaction
  524. */
  525. set_cdar(chan, desc->async_tx.phys);
  526. get_cdar(chan);
  527. dma_start(chan);
  528. chan->idle = false;
  529. }
  530. /**
  531. * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
  532. * and move them to ld_completed to free until flag 'ack' is set
  533. * @chan: Freescale DMA channel
  534. *
  535. * This function is used on descriptors which have been executed by the DMA
  536. * controller. It will run any callbacks, submit any dependencies, then
  537. * free these descriptors if flag 'ack' is set.
  538. */
  539. static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
  540. {
  541. struct fsl_desc_sw *desc, *_desc;
  542. dma_cookie_t cookie = 0;
  543. dma_addr_t curr_phys = get_cdar(chan);
  544. int seen_current = 0;
  545. fsldma_clean_completed_descriptor(chan);
  546. /* Run the callback for each descriptor, in order */
  547. list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
  548. /*
  549. * do not advance past the current descriptor loaded into the
  550. * hardware channel, subsequent descriptors are either in
  551. * process or have not been submitted
  552. */
  553. if (seen_current)
  554. break;
  555. /*
  556. * stop the search if we reach the current descriptor and the
  557. * channel is busy
  558. */
  559. if (desc->async_tx.phys == curr_phys) {
  560. seen_current = 1;
  561. if (!dma_is_idle(chan))
  562. break;
  563. }
  564. cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
  565. fsldma_clean_running_descriptor(chan, desc);
  566. }
  567. /*
  568. * Start any pending transactions automatically
  569. *
  570. * In the ideal case, we keep the DMA controller busy while we go
  571. * ahead and free the descriptors below.
  572. */
  573. fsl_chan_xfer_ld_queue(chan);
  574. if (cookie > 0)
  575. chan->common.completed_cookie = cookie;
  576. }
  577. /**
  578. * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
  579. * @chan : Freescale DMA channel
  580. *
  581. * This function will create a dma pool for descriptor allocation.
  582. *
  583. * Return - The number of descriptors allocated.
  584. */
  585. static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
  586. {
  587. struct fsldma_chan *chan = to_fsl_chan(dchan);
  588. /* Has this channel already been allocated? */
  589. if (chan->desc_pool)
  590. return 1;
  591. /*
  592. * We need the descriptor to be aligned to 32bytes
  593. * for meeting FSL DMA specification requirement.
  594. */
  595. chan->desc_pool = dma_pool_create(chan->name, chan->dev,
  596. sizeof(struct fsl_desc_sw),
  597. __alignof__(struct fsl_desc_sw), 0);
  598. if (!chan->desc_pool) {
  599. chan_err(chan, "unable to allocate descriptor pool\n");
  600. return -ENOMEM;
  601. }
  602. /* there is at least one descriptor free to be allocated */
  603. return 1;
  604. }
  605. /**
  606. * fsldma_free_desc_list - Free all descriptors in a queue
  607. * @chan: Freescae DMA channel
  608. * @list: the list to free
  609. *
  610. * LOCKING: must hold chan->desc_lock
  611. */
  612. static void fsldma_free_desc_list(struct fsldma_chan *chan,
  613. struct list_head *list)
  614. {
  615. struct fsl_desc_sw *desc, *_desc;
  616. list_for_each_entry_safe(desc, _desc, list, node)
  617. fsl_dma_free_descriptor(chan, desc);
  618. }
  619. static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
  620. struct list_head *list)
  621. {
  622. struct fsl_desc_sw *desc, *_desc;
  623. list_for_each_entry_safe_reverse(desc, _desc, list, node)
  624. fsl_dma_free_descriptor(chan, desc);
  625. }
  626. /**
  627. * fsl_dma_free_chan_resources - Free all resources of the channel.
  628. * @chan : Freescale DMA channel
  629. */
  630. static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
  631. {
  632. struct fsldma_chan *chan = to_fsl_chan(dchan);
  633. chan_dbg(chan, "free all channel resources\n");
  634. spin_lock_bh(&chan->desc_lock);
  635. fsldma_cleanup_descriptors(chan);
  636. fsldma_free_desc_list(chan, &chan->ld_pending);
  637. fsldma_free_desc_list(chan, &chan->ld_running);
  638. fsldma_free_desc_list(chan, &chan->ld_completed);
  639. spin_unlock_bh(&chan->desc_lock);
  640. dma_pool_destroy(chan->desc_pool);
  641. chan->desc_pool = NULL;
  642. }
  643. static struct dma_async_tx_descriptor *
  644. fsl_dma_prep_memcpy(struct dma_chan *dchan,
  645. dma_addr_t dma_dst, dma_addr_t dma_src,
  646. size_t len, unsigned long flags)
  647. {
  648. struct fsldma_chan *chan;
  649. struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
  650. size_t copy;
  651. if (!dchan)
  652. return NULL;
  653. if (!len)
  654. return NULL;
  655. chan = to_fsl_chan(dchan);
  656. do {
  657. /* Allocate the link descriptor from DMA pool */
  658. new = fsl_dma_alloc_descriptor(chan);
  659. if (!new) {
  660. chan_err(chan, "%s\n", msg_ld_oom);
  661. goto fail;
  662. }
  663. copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
  664. set_desc_cnt(chan, &new->hw, copy);
  665. set_desc_src(chan, &new->hw, dma_src);
  666. set_desc_dst(chan, &new->hw, dma_dst);
  667. if (!first)
  668. first = new;
  669. else
  670. set_desc_next(chan, &prev->hw, new->async_tx.phys);
  671. new->async_tx.cookie = 0;
  672. async_tx_ack(&new->async_tx);
  673. prev = new;
  674. len -= copy;
  675. dma_src += copy;
  676. dma_dst += copy;
  677. /* Insert the link descriptor to the LD ring */
  678. list_add_tail(&new->node, &first->tx_list);
  679. } while (len);
  680. new->async_tx.flags = flags; /* client is in control of this ack */
  681. new->async_tx.cookie = -EBUSY;
  682. /* Set End-of-link to the last link descriptor of new list */
  683. set_ld_eol(chan, new);
  684. return &first->async_tx;
  685. fail:
  686. if (!first)
  687. return NULL;
  688. fsldma_free_desc_list_reverse(chan, &first->tx_list);
  689. return NULL;
  690. }
  691. static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
  692. {
  693. struct fsldma_chan *chan;
  694. if (!dchan)
  695. return -EINVAL;
  696. chan = to_fsl_chan(dchan);
  697. spin_lock_bh(&chan->desc_lock);
  698. /* Halt the DMA engine */
  699. dma_halt(chan);
  700. /* Remove and free all of the descriptors in the LD queue */
  701. fsldma_free_desc_list(chan, &chan->ld_pending);
  702. fsldma_free_desc_list(chan, &chan->ld_running);
  703. fsldma_free_desc_list(chan, &chan->ld_completed);
  704. chan->idle = true;
  705. spin_unlock_bh(&chan->desc_lock);
  706. return 0;
  707. }
  708. static int fsl_dma_device_config(struct dma_chan *dchan,
  709. struct dma_slave_config *config)
  710. {
  711. struct fsldma_chan *chan;
  712. int size;
  713. if (!dchan)
  714. return -EINVAL;
  715. chan = to_fsl_chan(dchan);
  716. /* make sure the channel supports setting burst size */
  717. if (!chan->set_request_count)
  718. return -ENXIO;
  719. /* we set the controller burst size depending on direction */
  720. if (config->direction == DMA_MEM_TO_DEV)
  721. size = config->dst_addr_width * config->dst_maxburst;
  722. else
  723. size = config->src_addr_width * config->src_maxburst;
  724. chan->set_request_count(chan, size);
  725. return 0;
  726. }
  727. /**
  728. * fsl_dma_memcpy_issue_pending - Issue the DMA start command
  729. * @chan : Freescale DMA channel
  730. */
  731. static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
  732. {
  733. struct fsldma_chan *chan = to_fsl_chan(dchan);
  734. spin_lock_bh(&chan->desc_lock);
  735. fsl_chan_xfer_ld_queue(chan);
  736. spin_unlock_bh(&chan->desc_lock);
  737. }
  738. /**
  739. * fsl_tx_status - Determine the DMA status
  740. * @chan : Freescale DMA channel
  741. */
  742. static enum dma_status fsl_tx_status(struct dma_chan *dchan,
  743. dma_cookie_t cookie,
  744. struct dma_tx_state *txstate)
  745. {
  746. struct fsldma_chan *chan = to_fsl_chan(dchan);
  747. enum dma_status ret;
  748. ret = dma_cookie_status(dchan, cookie, txstate);
  749. if (ret == DMA_COMPLETE)
  750. return ret;
  751. spin_lock_bh(&chan->desc_lock);
  752. fsldma_cleanup_descriptors(chan);
  753. spin_unlock_bh(&chan->desc_lock);
  754. return dma_cookie_status(dchan, cookie, txstate);
  755. }
  756. /*----------------------------------------------------------------------------*/
  757. /* Interrupt Handling */
  758. /*----------------------------------------------------------------------------*/
  759. static irqreturn_t fsldma_chan_irq(int irq, void *data)
  760. {
  761. struct fsldma_chan *chan = data;
  762. u32 stat;
  763. /* save and clear the status register */
  764. stat = get_sr(chan);
  765. set_sr(chan, stat);
  766. chan_dbg(chan, "irq: stat = 0x%x\n", stat);
  767. /* check that this was really our device */
  768. stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
  769. if (!stat)
  770. return IRQ_NONE;
  771. if (stat & FSL_DMA_SR_TE)
  772. chan_err(chan, "Transfer Error!\n");
  773. /*
  774. * Programming Error
  775. * The DMA_INTERRUPT async_tx is a NULL transfer, which will
  776. * trigger a PE interrupt.
  777. */
  778. if (stat & FSL_DMA_SR_PE) {
  779. chan_dbg(chan, "irq: Programming Error INT\n");
  780. stat &= ~FSL_DMA_SR_PE;
  781. if (get_bcr(chan) != 0)
  782. chan_err(chan, "Programming Error!\n");
  783. }
  784. /*
  785. * For MPC8349, EOCDI event need to update cookie
  786. * and start the next transfer if it exist.
  787. */
  788. if (stat & FSL_DMA_SR_EOCDI) {
  789. chan_dbg(chan, "irq: End-of-Chain link INT\n");
  790. stat &= ~FSL_DMA_SR_EOCDI;
  791. }
  792. /*
  793. * If it current transfer is the end-of-transfer,
  794. * we should clear the Channel Start bit for
  795. * prepare next transfer.
  796. */
  797. if (stat & FSL_DMA_SR_EOLNI) {
  798. chan_dbg(chan, "irq: End-of-link INT\n");
  799. stat &= ~FSL_DMA_SR_EOLNI;
  800. }
  801. /* check that the DMA controller is really idle */
  802. if (!dma_is_idle(chan))
  803. chan_err(chan, "irq: controller not idle!\n");
  804. /* check that we handled all of the bits */
  805. if (stat)
  806. chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
  807. /*
  808. * Schedule the tasklet to handle all cleanup of the current
  809. * transaction. It will start a new transaction if there is
  810. * one pending.
  811. */
  812. tasklet_schedule(&chan->tasklet);
  813. chan_dbg(chan, "irq: Exit\n");
  814. return IRQ_HANDLED;
  815. }
  816. static void dma_do_tasklet(struct tasklet_struct *t)
  817. {
  818. struct fsldma_chan *chan = from_tasklet(chan, t, tasklet);
  819. chan_dbg(chan, "tasklet entry\n");
  820. spin_lock(&chan->desc_lock);
  821. /* the hardware is now idle and ready for more */
  822. chan->idle = true;
  823. /* Run all cleanup for descriptors which have been completed */
  824. fsldma_cleanup_descriptors(chan);
  825. spin_unlock(&chan->desc_lock);
  826. chan_dbg(chan, "tasklet exit\n");
  827. }
  828. static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
  829. {
  830. struct fsldma_device *fdev = data;
  831. struct fsldma_chan *chan;
  832. unsigned int handled = 0;
  833. u32 gsr, mask;
  834. int i;
  835. gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
  836. : in_le32(fdev->regs);
  837. mask = 0xff000000;
  838. dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
  839. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  840. chan = fdev->chan[i];
  841. if (!chan)
  842. continue;
  843. if (gsr & mask) {
  844. dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
  845. fsldma_chan_irq(irq, chan);
  846. handled++;
  847. }
  848. gsr &= ~mask;
  849. mask >>= 8;
  850. }
  851. return IRQ_RETVAL(handled);
  852. }
  853. static void fsldma_free_irqs(struct fsldma_device *fdev)
  854. {
  855. struct fsldma_chan *chan;
  856. int i;
  857. if (fdev->irq) {
  858. dev_dbg(fdev->dev, "free per-controller IRQ\n");
  859. free_irq(fdev->irq, fdev);
  860. return;
  861. }
  862. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  863. chan = fdev->chan[i];
  864. if (chan && chan->irq) {
  865. chan_dbg(chan, "free per-channel IRQ\n");
  866. free_irq(chan->irq, chan);
  867. }
  868. }
  869. }
  870. static int fsldma_request_irqs(struct fsldma_device *fdev)
  871. {
  872. struct fsldma_chan *chan;
  873. int ret;
  874. int i;
  875. /* if we have a per-controller IRQ, use that */
  876. if (fdev->irq) {
  877. dev_dbg(fdev->dev, "request per-controller IRQ\n");
  878. ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
  879. "fsldma-controller", fdev);
  880. return ret;
  881. }
  882. /* no per-controller IRQ, use the per-channel IRQs */
  883. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  884. chan = fdev->chan[i];
  885. if (!chan)
  886. continue;
  887. if (!chan->irq) {
  888. chan_err(chan, "interrupts property missing in device tree\n");
  889. ret = -ENODEV;
  890. goto out_unwind;
  891. }
  892. chan_dbg(chan, "request per-channel IRQ\n");
  893. ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
  894. "fsldma-chan", chan);
  895. if (ret) {
  896. chan_err(chan, "unable to request per-channel IRQ\n");
  897. goto out_unwind;
  898. }
  899. }
  900. return 0;
  901. out_unwind:
  902. for (/* none */; i >= 0; i--) {
  903. chan = fdev->chan[i];
  904. if (!chan)
  905. continue;
  906. if (!chan->irq)
  907. continue;
  908. free_irq(chan->irq, chan);
  909. }
  910. return ret;
  911. }
  912. /*----------------------------------------------------------------------------*/
  913. /* OpenFirmware Subsystem */
  914. /*----------------------------------------------------------------------------*/
  915. static int fsl_dma_chan_probe(struct fsldma_device *fdev,
  916. struct device_node *node, u32 feature, const char *compatible)
  917. {
  918. struct fsldma_chan *chan;
  919. struct resource res;
  920. int err;
  921. /* alloc channel */
  922. chan = kzalloc(sizeof(*chan), GFP_KERNEL);
  923. if (!chan) {
  924. err = -ENOMEM;
  925. goto out_return;
  926. }
  927. /* ioremap registers for use */
  928. chan->regs = of_iomap(node, 0);
  929. if (!chan->regs) {
  930. dev_err(fdev->dev, "unable to ioremap registers\n");
  931. err = -ENOMEM;
  932. goto out_free_chan;
  933. }
  934. err = of_address_to_resource(node, 0, &res);
  935. if (err) {
  936. dev_err(fdev->dev, "unable to find 'reg' property\n");
  937. goto out_iounmap_regs;
  938. }
  939. chan->feature = feature;
  940. if (!fdev->feature)
  941. fdev->feature = chan->feature;
  942. /*
  943. * If the DMA device's feature is different than the feature
  944. * of its channels, report the bug
  945. */
  946. WARN_ON(fdev->feature != chan->feature);
  947. chan->dev = fdev->dev;
  948. chan->id = (res.start & 0xfff) < 0x300 ?
  949. ((res.start - 0x100) & 0xfff) >> 7 :
  950. ((res.start - 0x200) & 0xfff) >> 7;
  951. if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
  952. dev_err(fdev->dev, "too many channels for device\n");
  953. err = -EINVAL;
  954. goto out_iounmap_regs;
  955. }
  956. fdev->chan[chan->id] = chan;
  957. tasklet_setup(&chan->tasklet, dma_do_tasklet);
  958. snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
  959. /* Initialize the channel */
  960. dma_init(chan);
  961. /* Clear cdar registers */
  962. set_cdar(chan, 0);
  963. switch (chan->feature & FSL_DMA_IP_MASK) {
  964. case FSL_DMA_IP_85XX:
  965. chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
  966. fallthrough;
  967. case FSL_DMA_IP_83XX:
  968. chan->toggle_ext_start = fsl_chan_toggle_ext_start;
  969. chan->set_src_loop_size = fsl_chan_set_src_loop_size;
  970. chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
  971. chan->set_request_count = fsl_chan_set_request_count;
  972. }
  973. spin_lock_init(&chan->desc_lock);
  974. INIT_LIST_HEAD(&chan->ld_pending);
  975. INIT_LIST_HEAD(&chan->ld_running);
  976. INIT_LIST_HEAD(&chan->ld_completed);
  977. chan->idle = true;
  978. #ifdef CONFIG_PM
  979. chan->pm_state = RUNNING;
  980. #endif
  981. chan->common.device = &fdev->common;
  982. dma_cookie_init(&chan->common);
  983. /* find the IRQ line, if it exists in the device tree */
  984. chan->irq = irq_of_parse_and_map(node, 0);
  985. /* Add the channel to DMA device channel list */
  986. list_add_tail(&chan->common.device_node, &fdev->common.channels);
  987. dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
  988. chan->irq ? chan->irq : fdev->irq);
  989. return 0;
  990. out_iounmap_regs:
  991. iounmap(chan->regs);
  992. out_free_chan:
  993. kfree(chan);
  994. out_return:
  995. return err;
  996. }
  997. static void fsl_dma_chan_remove(struct fsldma_chan *chan)
  998. {
  999. irq_dispose_mapping(chan->irq);
  1000. list_del(&chan->common.device_node);
  1001. iounmap(chan->regs);
  1002. kfree(chan);
  1003. }
  1004. static int fsldma_of_probe(struct platform_device *op)
  1005. {
  1006. struct fsldma_device *fdev;
  1007. struct device_node *child;
  1008. unsigned int i;
  1009. int err;
  1010. fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
  1011. if (!fdev) {
  1012. err = -ENOMEM;
  1013. goto out_return;
  1014. }
  1015. fdev->dev = &op->dev;
  1016. INIT_LIST_HEAD(&fdev->common.channels);
  1017. /* ioremap the registers for use */
  1018. fdev->regs = of_iomap(op->dev.of_node, 0);
  1019. if (!fdev->regs) {
  1020. dev_err(&op->dev, "unable to ioremap registers\n");
  1021. err = -ENOMEM;
  1022. goto out_free;
  1023. }
  1024. /* map the channel IRQ if it exists, but don't hookup the handler yet */
  1025. fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
  1026. dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
  1027. dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
  1028. fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
  1029. fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
  1030. fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
  1031. fdev->common.device_tx_status = fsl_tx_status;
  1032. fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
  1033. fdev->common.device_config = fsl_dma_device_config;
  1034. fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
  1035. fdev->common.dev = &op->dev;
  1036. fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
  1037. fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
  1038. fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  1039. fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  1040. dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
  1041. platform_set_drvdata(op, fdev);
  1042. /*
  1043. * We cannot use of_platform_bus_probe() because there is no
  1044. * of_platform_bus_remove(). Instead, we manually instantiate every DMA
  1045. * channel object.
  1046. */
  1047. for_each_child_of_node(op->dev.of_node, child) {
  1048. if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
  1049. fsl_dma_chan_probe(fdev, child,
  1050. FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
  1051. "fsl,eloplus-dma-channel");
  1052. }
  1053. if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
  1054. fsl_dma_chan_probe(fdev, child,
  1055. FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
  1056. "fsl,elo-dma-channel");
  1057. }
  1058. }
  1059. /*
  1060. * Hookup the IRQ handler(s)
  1061. *
  1062. * If we have a per-controller interrupt, we prefer that to the
  1063. * per-channel interrupts to reduce the number of shared interrupt
  1064. * handlers on the same IRQ line
  1065. */
  1066. err = fsldma_request_irqs(fdev);
  1067. if (err) {
  1068. dev_err(fdev->dev, "unable to request IRQs\n");
  1069. goto out_free_fdev;
  1070. }
  1071. dma_async_device_register(&fdev->common);
  1072. return 0;
  1073. out_free_fdev:
  1074. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  1075. if (fdev->chan[i])
  1076. fsl_dma_chan_remove(fdev->chan[i]);
  1077. }
  1078. irq_dispose_mapping(fdev->irq);
  1079. iounmap(fdev->regs);
  1080. out_free:
  1081. kfree(fdev);
  1082. out_return:
  1083. return err;
  1084. }
  1085. static int fsldma_of_remove(struct platform_device *op)
  1086. {
  1087. struct fsldma_device *fdev;
  1088. unsigned int i;
  1089. fdev = platform_get_drvdata(op);
  1090. dma_async_device_unregister(&fdev->common);
  1091. fsldma_free_irqs(fdev);
  1092. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  1093. if (fdev->chan[i])
  1094. fsl_dma_chan_remove(fdev->chan[i]);
  1095. }
  1096. irq_dispose_mapping(fdev->irq);
  1097. iounmap(fdev->regs);
  1098. kfree(fdev);
  1099. return 0;
  1100. }
  1101. #ifdef CONFIG_PM
  1102. static int fsldma_suspend_late(struct device *dev)
  1103. {
  1104. struct fsldma_device *fdev = dev_get_drvdata(dev);
  1105. struct fsldma_chan *chan;
  1106. int i;
  1107. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  1108. chan = fdev->chan[i];
  1109. if (!chan)
  1110. continue;
  1111. spin_lock_bh(&chan->desc_lock);
  1112. if (unlikely(!chan->idle))
  1113. goto out;
  1114. chan->regs_save.mr = get_mr(chan);
  1115. chan->pm_state = SUSPENDED;
  1116. spin_unlock_bh(&chan->desc_lock);
  1117. }
  1118. return 0;
  1119. out:
  1120. for (; i >= 0; i--) {
  1121. chan = fdev->chan[i];
  1122. if (!chan)
  1123. continue;
  1124. chan->pm_state = RUNNING;
  1125. spin_unlock_bh(&chan->desc_lock);
  1126. }
  1127. return -EBUSY;
  1128. }
  1129. static int fsldma_resume_early(struct device *dev)
  1130. {
  1131. struct fsldma_device *fdev = dev_get_drvdata(dev);
  1132. struct fsldma_chan *chan;
  1133. u32 mode;
  1134. int i;
  1135. for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
  1136. chan = fdev->chan[i];
  1137. if (!chan)
  1138. continue;
  1139. spin_lock_bh(&chan->desc_lock);
  1140. mode = chan->regs_save.mr
  1141. & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
  1142. set_mr(chan, mode);
  1143. chan->pm_state = RUNNING;
  1144. spin_unlock_bh(&chan->desc_lock);
  1145. }
  1146. return 0;
  1147. }
  1148. static const struct dev_pm_ops fsldma_pm_ops = {
  1149. .suspend_late = fsldma_suspend_late,
  1150. .resume_early = fsldma_resume_early,
  1151. };
  1152. #endif
  1153. static const struct of_device_id fsldma_of_ids[] = {
  1154. { .compatible = "fsl,elo3-dma", },
  1155. { .compatible = "fsl,eloplus-dma", },
  1156. { .compatible = "fsl,elo-dma", },
  1157. {}
  1158. };
  1159. MODULE_DEVICE_TABLE(of, fsldma_of_ids);
  1160. static struct platform_driver fsldma_of_driver = {
  1161. .driver = {
  1162. .name = "fsl-elo-dma",
  1163. .of_match_table = fsldma_of_ids,
  1164. #ifdef CONFIG_PM
  1165. .pm = &fsldma_pm_ops,
  1166. #endif
  1167. },
  1168. .probe = fsldma_of_probe,
  1169. .remove = fsldma_of_remove,
  1170. };
  1171. /*----------------------------------------------------------------------------*/
  1172. /* Module Init / Exit */
  1173. /*----------------------------------------------------------------------------*/
  1174. static __init int fsldma_init(void)
  1175. {
  1176. pr_info("Freescale Elo series DMA driver\n");
  1177. return platform_driver_register(&fsldma_of_driver);
  1178. }
  1179. static void __exit fsldma_exit(void)
  1180. {
  1181. platform_driver_unregister(&fsldma_of_driver);
  1182. }
  1183. subsys_initcall(fsldma_init);
  1184. module_exit(fsldma_exit);
  1185. MODULE_DESCRIPTION("Freescale Elo series DMA driver");
  1186. MODULE_LICENSE("GPL");