fsl-edma-common.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
  5. */
  6. #ifndef _FSL_EDMA_COMMON_H_
  7. #define _FSL_EDMA_COMMON_H_
  8. #include <linux/dma-direction.h>
  9. #include <linux/platform_device.h>
  10. #include "virt-dma.h"
  11. #define EDMA_CR_EDBG BIT(1)
  12. #define EDMA_CR_ERCA BIT(2)
  13. #define EDMA_CR_ERGA BIT(3)
  14. #define EDMA_CR_HOE BIT(4)
  15. #define EDMA_CR_HALT BIT(5)
  16. #define EDMA_CR_CLM BIT(6)
  17. #define EDMA_CR_EMLM BIT(7)
  18. #define EDMA_CR_ECX BIT(16)
  19. #define EDMA_CR_CX BIT(17)
  20. #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
  21. #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
  22. #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
  23. #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
  24. #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
  25. #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
  26. #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
  27. #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
  28. #define EDMA_TCD_ATTR_DSIZE_8BIT 0
  29. #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0)
  30. #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1)
  31. #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1))
  32. #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(2) | BIT(0))
  33. #define EDMA_TCD_ATTR_SSIZE_8BIT 0
  34. #define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8)
  35. #define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
  36. #define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8)
  37. #define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8)
  38. #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
  39. #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
  40. #define EDMA_TCD_CSR_START BIT(0)
  41. #define EDMA_TCD_CSR_INT_MAJOR BIT(1)
  42. #define EDMA_TCD_CSR_INT_HALF BIT(2)
  43. #define EDMA_TCD_CSR_D_REQ BIT(3)
  44. #define EDMA_TCD_CSR_E_SG BIT(4)
  45. #define EDMA_TCD_CSR_E_LINK BIT(5)
  46. #define EDMA_TCD_CSR_ACTIVE BIT(6)
  47. #define EDMA_TCD_CSR_DONE BIT(7)
  48. #define EDMAMUX_CHCFG_DIS 0x0
  49. #define EDMAMUX_CHCFG_ENBL 0x80
  50. #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
  51. #define DMAMUX_NR 2
  52. #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  53. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  54. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  55. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  56. enum fsl_edma_pm_state {
  57. RUNNING = 0,
  58. SUSPENDED,
  59. };
  60. struct fsl_edma_hw_tcd {
  61. __le32 saddr;
  62. __le16 soff;
  63. __le16 attr;
  64. __le32 nbytes;
  65. __le32 slast;
  66. __le32 daddr;
  67. __le16 doff;
  68. __le16 citer;
  69. __le32 dlast_sga;
  70. __le16 csr;
  71. __le16 biter;
  72. };
  73. /*
  74. * These are iomem pointers, for both v32 and v64.
  75. */
  76. struct edma_regs {
  77. void __iomem *cr;
  78. void __iomem *es;
  79. void __iomem *erqh;
  80. void __iomem *erql; /* aka erq on v32 */
  81. void __iomem *eeih;
  82. void __iomem *eeil; /* aka eei on v32 */
  83. void __iomem *seei;
  84. void __iomem *ceei;
  85. void __iomem *serq;
  86. void __iomem *cerq;
  87. void __iomem *cint;
  88. void __iomem *cerr;
  89. void __iomem *ssrt;
  90. void __iomem *cdne;
  91. void __iomem *inth;
  92. void __iomem *intl;
  93. void __iomem *errh;
  94. void __iomem *errl;
  95. struct fsl_edma_hw_tcd __iomem *tcd;
  96. };
  97. struct fsl_edma_sw_tcd {
  98. dma_addr_t ptcd;
  99. struct fsl_edma_hw_tcd *vtcd;
  100. };
  101. struct fsl_edma_chan {
  102. struct virt_dma_chan vchan;
  103. enum dma_status status;
  104. enum fsl_edma_pm_state pm_state;
  105. bool idle;
  106. u32 slave_id;
  107. struct fsl_edma_engine *edma;
  108. struct fsl_edma_desc *edesc;
  109. struct dma_slave_config cfg;
  110. u32 attr;
  111. struct dma_pool *tcd_pool;
  112. dma_addr_t dma_dev_addr;
  113. u32 dma_dev_size;
  114. enum dma_data_direction dma_dir;
  115. char chan_name[16];
  116. };
  117. struct fsl_edma_desc {
  118. struct virt_dma_desc vdesc;
  119. struct fsl_edma_chan *echan;
  120. bool iscyclic;
  121. enum dma_transfer_direction dirn;
  122. unsigned int n_tcds;
  123. struct fsl_edma_sw_tcd tcd[];
  124. };
  125. enum edma_version {
  126. v1, /* 32ch, Vybrid, mpc57x, etc */
  127. v2, /* 64ch Coldfire */
  128. v3, /* 32ch, i.mx7ulp */
  129. };
  130. struct fsl_edma_drvdata {
  131. enum edma_version version;
  132. u32 dmamuxs;
  133. bool has_dmaclk;
  134. bool mux_swap;
  135. int (*setup_irq)(struct platform_device *pdev,
  136. struct fsl_edma_engine *fsl_edma);
  137. };
  138. struct fsl_edma_engine {
  139. struct dma_device dma_dev;
  140. void __iomem *membase;
  141. void __iomem *muxbase[DMAMUX_NR];
  142. struct clk *muxclk[DMAMUX_NR];
  143. struct clk *dmaclk;
  144. struct mutex fsl_edma_mutex;
  145. const struct fsl_edma_drvdata *drvdata;
  146. u32 n_chans;
  147. int txirq;
  148. int errirq;
  149. bool big_endian;
  150. struct edma_regs regs;
  151. struct fsl_edma_chan chans[];
  152. };
  153. /*
  154. * R/W functions for big- or little-endian registers:
  155. * The eDMA controller's endian is independent of the CPU core's endian.
  156. * For the big-endian IP module, the offset for 8-bit or 16-bit registers
  157. * should also be swapped opposite to that in little-endian IP.
  158. */
  159. static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
  160. {
  161. if (edma->big_endian)
  162. return ioread32be(addr);
  163. else
  164. return ioread32(addr);
  165. }
  166. static inline void edma_writeb(struct fsl_edma_engine *edma,
  167. u8 val, void __iomem *addr)
  168. {
  169. /* swap the reg offset for these in big-endian mode */
  170. if (edma->big_endian)
  171. iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
  172. else
  173. iowrite8(val, addr);
  174. }
  175. static inline void edma_writew(struct fsl_edma_engine *edma,
  176. u16 val, void __iomem *addr)
  177. {
  178. /* swap the reg offset for these in big-endian mode */
  179. if (edma->big_endian)
  180. iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
  181. else
  182. iowrite16(val, addr);
  183. }
  184. static inline void edma_writel(struct fsl_edma_engine *edma,
  185. u32 val, void __iomem *addr)
  186. {
  187. if (edma->big_endian)
  188. iowrite32be(val, addr);
  189. else
  190. iowrite32(val, addr);
  191. }
  192. static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
  193. {
  194. return container_of(chan, struct fsl_edma_chan, vchan.chan);
  195. }
  196. static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
  197. {
  198. return container_of(vd, struct fsl_edma_desc, vdesc);
  199. }
  200. void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
  201. void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
  202. unsigned int slot, bool enable);
  203. void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
  204. int fsl_edma_terminate_all(struct dma_chan *chan);
  205. int fsl_edma_pause(struct dma_chan *chan);
  206. int fsl_edma_resume(struct dma_chan *chan);
  207. int fsl_edma_slave_config(struct dma_chan *chan,
  208. struct dma_slave_config *cfg);
  209. enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
  210. dma_cookie_t cookie, struct dma_tx_state *txstate);
  211. struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
  212. struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
  213. size_t period_len, enum dma_transfer_direction direction,
  214. unsigned long flags);
  215. struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
  216. struct dma_chan *chan, struct scatterlist *sgl,
  217. unsigned int sg_len, enum dma_transfer_direction direction,
  218. unsigned long flags, void *context);
  219. void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
  220. void fsl_edma_issue_pending(struct dma_chan *chan);
  221. int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
  222. void fsl_edma_free_chan_resources(struct dma_chan *chan);
  223. void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
  224. void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
  225. #endif /* _FSL_EDMA_COMMON_H_ */