dpaa2-qdma.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright 2019 NXP */
  3. #ifndef __DPAA2_QDMA_H
  4. #define __DPAA2_QDMA_H
  5. #define DPAA2_QDMA_STORE_SIZE 16
  6. #define NUM_CH 8
  7. struct dpaa2_qdma_sd_d {
  8. u32 rsv:32;
  9. union {
  10. struct {
  11. u32 ssd:12; /* souce stride distance */
  12. u32 sss:12; /* souce stride size */
  13. u32 rsv1:8;
  14. } sdf;
  15. struct {
  16. u32 dsd:12; /* Destination stride distance */
  17. u32 dss:12; /* Destination stride size */
  18. u32 rsv2:8;
  19. } ddf;
  20. } df;
  21. u32 rbpcmd; /* Route-by-port command */
  22. u32 cmd;
  23. } __attribute__((__packed__));
  24. /* Source descriptor command read transaction type for RBP=0: */
  25. /* coherent copy of cacheable memory */
  26. #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28)
  27. /* Destination descriptor command write transaction type for RBP=0: */
  28. /* coherent copy of cacheable memory */
  29. #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
  30. #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
  31. #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
  32. #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
  33. #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
  34. #define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */
  35. #define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */
  36. #define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */
  37. #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
  38. #define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */
  39. #define QDMA_FD_LONG_FORMAT (0) /* long format */
  40. #define QDMA_SER_DISABLE (8) /* no notification */
  41. #define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */
  42. #define QDMA_SER_DEST (2 << 8) /* notification by destination desc */
  43. #define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */
  44. #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
  45. #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */
  46. #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */
  47. /* Flow Context: 49bit physical address */
  48. #define QMAN_FD_CBMT_ENABLE BIT(15)
  49. #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */
  50. #define QMAN_FD_SC_DISABLE (0) /* stashing control */
  51. #define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */
  52. #define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */
  53. #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
  54. #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
  55. #define QDMA_FL_SL_LONG (0x0)/* long length */
  56. #define QDMA_FL_SL_SHORT (0x1) /* short length */
  57. #define QDMA_FL_F (0x1)/* last frame list bit */
  58. /*Description of Frame list table structure*/
  59. struct dpaa2_qdma_chan {
  60. struct dpaa2_qdma_engine *qdma;
  61. struct virt_dma_chan vchan;
  62. struct virt_dma_desc vdesc;
  63. enum dma_status status;
  64. u32 fqid;
  65. /* spinlock used by dpaa2 qdma driver */
  66. spinlock_t queue_lock;
  67. struct dma_pool *fd_pool;
  68. struct dma_pool *fl_pool;
  69. struct dma_pool *sdd_pool;
  70. struct list_head comp_used;
  71. struct list_head comp_free;
  72. };
  73. struct dpaa2_qdma_comp {
  74. dma_addr_t fd_bus_addr;
  75. dma_addr_t fl_bus_addr;
  76. dma_addr_t desc_bus_addr;
  77. struct dpaa2_fd *fd_virt_addr;
  78. struct dpaa2_fl_entry *fl_virt_addr;
  79. struct dpaa2_qdma_sd_d *desc_virt_addr;
  80. struct dpaa2_qdma_chan *qchan;
  81. struct virt_dma_desc vdesc;
  82. struct list_head list;
  83. };
  84. struct dpaa2_qdma_engine {
  85. struct dma_device dma_dev;
  86. u32 n_chans;
  87. struct dpaa2_qdma_chan chans[NUM_CH];
  88. int qdma_wrtype_fixup;
  89. int desc_allocated;
  90. struct dpaa2_qdma_priv *priv;
  91. };
  92. /*
  93. * dpaa2_qdma_priv - driver private data
  94. */
  95. struct dpaa2_qdma_priv {
  96. int dpqdma_id;
  97. struct iommu_domain *iommu_domain;
  98. struct dpdmai_attr dpdmai_attr;
  99. struct device *dev;
  100. struct fsl_mc_io *mc_io;
  101. struct fsl_mc_device *dpdmai_dev;
  102. u8 num_pairs;
  103. struct dpaa2_qdma_engine *dpaa2_qdma;
  104. struct dpaa2_qdma_priv_per_prio *ppriv;
  105. struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM];
  106. u32 tx_fqid[DPDMAI_PRIO_NUM];
  107. };
  108. struct dpaa2_qdma_priv_per_prio {
  109. int req_fqid;
  110. int rsp_fqid;
  111. int prio;
  112. struct dpaa2_io_store *store;
  113. struct dpaa2_io_notification_ctx nctx;
  114. struct dpaa2_qdma_priv *priv;
  115. };
  116. static struct soc_device_attribute soc_fixup_tuning[] = {
  117. { .family = "QorIQ LX2160A"},
  118. { },
  119. };
  120. /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
  121. #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
  122. sizeof(struct dpaa2_fl_entry) * 3 + \
  123. sizeof(struct dpaa2_qdma_sd_d) * 2)
  124. static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma);
  125. static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan,
  126. struct list_head *head);
  127. #endif /* __DPAA2_QDMA_H */