idma32.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2013,2018 Intel Corporation
  3. #include <linux/bitops.h>
  4. #include <linux/dmaengine.h>
  5. #include <linux/errno.h>
  6. #include <linux/slab.h>
  7. #include <linux/types.h>
  8. #include "internal.h"
  9. static void idma32_initialize_chan(struct dw_dma_chan *dwc)
  10. {
  11. u32 cfghi = 0;
  12. u32 cfglo = 0;
  13. /* Set default burst alignment */
  14. cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
  15. /* Low 4 bits of the request lines */
  16. cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
  17. cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
  18. /* Request line extension (2 bits) */
  19. cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
  20. cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
  21. channel_writel(dwc, CFG_LO, cfglo);
  22. channel_writel(dwc, CFG_HI, cfghi);
  23. }
  24. static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
  25. {
  26. u32 cfglo = channel_readl(dwc, CFG_LO);
  27. if (drain)
  28. cfglo |= IDMA32C_CFGL_CH_DRAIN;
  29. channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
  30. }
  31. static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
  32. {
  33. u32 cfglo = channel_readl(dwc, CFG_LO);
  34. if (drain)
  35. cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
  36. channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
  37. }
  38. static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
  39. size_t bytes, unsigned int width, size_t *len)
  40. {
  41. u32 block;
  42. if (bytes > dwc->block_size) {
  43. block = dwc->block_size;
  44. *len = dwc->block_size;
  45. } else {
  46. block = bytes;
  47. *len = bytes;
  48. }
  49. return block;
  50. }
  51. static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
  52. {
  53. return IDMA32C_CTLH_BLOCK_TS(block);
  54. }
  55. static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
  56. {
  57. struct dma_slave_config *sconfig = &dwc->dma_sconfig;
  58. u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
  59. u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
  60. return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
  61. DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
  62. }
  63. static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
  64. {
  65. *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
  66. }
  67. static void idma32_set_device_name(struct dw_dma *dw, int id)
  68. {
  69. snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
  70. }
  71. /*
  72. * Program FIFO size of channels.
  73. *
  74. * By default full FIFO (512 bytes) is assigned to channel 0. Here we
  75. * slice FIFO on equal parts between channels.
  76. */
  77. static void idma32_fifo_partition(struct dw_dma *dw)
  78. {
  79. u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
  80. IDMA32C_FP_UPDATE;
  81. u64 fifo_partition = 0;
  82. /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
  83. fifo_partition |= value << 0;
  84. /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
  85. fifo_partition |= value << 32;
  86. /* Program FIFO Partition registers - 64 bytes per channel */
  87. idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
  88. idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
  89. }
  90. static void idma32_disable(struct dw_dma *dw)
  91. {
  92. do_dw_dma_off(dw);
  93. idma32_fifo_partition(dw);
  94. }
  95. static void idma32_enable(struct dw_dma *dw)
  96. {
  97. idma32_fifo_partition(dw);
  98. do_dw_dma_on(dw);
  99. }
  100. int idma32_dma_probe(struct dw_dma_chip *chip)
  101. {
  102. struct dw_dma *dw;
  103. dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
  104. if (!dw)
  105. return -ENOMEM;
  106. /* Channel operations */
  107. dw->initialize_chan = idma32_initialize_chan;
  108. dw->suspend_chan = idma32_suspend_chan;
  109. dw->resume_chan = idma32_resume_chan;
  110. dw->prepare_ctllo = idma32_prepare_ctllo;
  111. dw->encode_maxburst = idma32_encode_maxburst;
  112. dw->bytes2block = idma32_bytes2block;
  113. dw->block2bytes = idma32_block2bytes;
  114. /* Device operations */
  115. dw->set_device_name = idma32_set_device_name;
  116. dw->disable = idma32_disable;
  117. dw->enable = idma32_enable;
  118. chip->dw = dw;
  119. return do_dma_probe(chip);
  120. }
  121. EXPORT_SYMBOL_GPL(idma32_dma_probe);
  122. int idma32_dma_remove(struct dw_dma_chip *chip)
  123. {
  124. return do_dma_remove(chip);
  125. }
  126. EXPORT_SYMBOL_GPL(idma32_dma_remove);