dw-edma-v0-regs.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. * Synopsys DesignWare eDMA v0 core
  5. *
  6. * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  7. */
  8. #ifndef _DW_EDMA_V0_REGS_H
  9. #define _DW_EDMA_V0_REGS_H
  10. #include <linux/dmaengine.h>
  11. #define EDMA_V0_MAX_NR_CH 8
  12. #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
  13. #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
  14. #define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)
  15. #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
  16. #define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)
  17. #define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)
  18. #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
  19. #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
  20. #define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)
  21. #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
  22. struct dw_edma_v0_ch_regs {
  23. u32 ch_control1; /* 0x000 */
  24. u32 ch_control2; /* 0x004 */
  25. u32 transfer_size; /* 0x008 */
  26. u32 sar_low; /* 0x00c */
  27. u32 sar_high; /* 0x010 */
  28. u32 dar_low; /* 0x014 */
  29. u32 dar_high; /* 0x018 */
  30. u32 llp_low; /* 0x01c */
  31. u32 llp_high; /* 0x020 */
  32. };
  33. struct dw_edma_v0_ch {
  34. struct dw_edma_v0_ch_regs wr; /* 0x200 */
  35. u32 padding_1[55]; /* [0x224..0x2fc] */
  36. struct dw_edma_v0_ch_regs rd; /* 0x300 */
  37. u32 padding_2[55]; /* [0x324..0x3fc] */
  38. };
  39. struct dw_edma_v0_unroll {
  40. u32 padding_1; /* 0x0f8 */
  41. u32 wr_engine_chgroup; /* 0x100 */
  42. u32 rd_engine_chgroup; /* 0x104 */
  43. u32 wr_engine_hshake_cnt_low; /* 0x108 */
  44. u32 wr_engine_hshake_cnt_high; /* 0x10c */
  45. u32 padding_2[2]; /* [0x110..0x114] */
  46. u32 rd_engine_hshake_cnt_low; /* 0x118 */
  47. u32 rd_engine_hshake_cnt_high; /* 0x11c */
  48. u32 padding_3[2]; /* [0x120..0x124] */
  49. u32 wr_ch0_pwr_en; /* 0x128 */
  50. u32 wr_ch1_pwr_en; /* 0x12c */
  51. u32 wr_ch2_pwr_en; /* 0x130 */
  52. u32 wr_ch3_pwr_en; /* 0x134 */
  53. u32 wr_ch4_pwr_en; /* 0x138 */
  54. u32 wr_ch5_pwr_en; /* 0x13c */
  55. u32 wr_ch6_pwr_en; /* 0x140 */
  56. u32 wr_ch7_pwr_en; /* 0x144 */
  57. u32 padding_4[8]; /* [0x148..0x164] */
  58. u32 rd_ch0_pwr_en; /* 0x168 */
  59. u32 rd_ch1_pwr_en; /* 0x16c */
  60. u32 rd_ch2_pwr_en; /* 0x170 */
  61. u32 rd_ch3_pwr_en; /* 0x174 */
  62. u32 rd_ch4_pwr_en; /* 0x178 */
  63. u32 rd_ch5_pwr_en; /* 0x18c */
  64. u32 rd_ch6_pwr_en; /* 0x180 */
  65. u32 rd_ch7_pwr_en; /* 0x184 */
  66. u32 padding_5[30]; /* [0x188..0x1fc] */
  67. struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; /* [0x200..0x1120] */
  68. };
  69. struct dw_edma_v0_legacy {
  70. u32 viewport_sel; /* 0x0f8 */
  71. struct dw_edma_v0_ch_regs ch; /* [0x100..0x120] */
  72. };
  73. struct dw_edma_v0_regs {
  74. /* eDMA global registers */
  75. u32 ctrl_data_arb_prior; /* 0x000 */
  76. u32 padding_1; /* 0x004 */
  77. u32 ctrl; /* 0x008 */
  78. u32 wr_engine_en; /* 0x00c */
  79. u32 wr_doorbell; /* 0x010 */
  80. u32 padding_2; /* 0x014 */
  81. u32 wr_ch_arb_weight_low; /* 0x018 */
  82. u32 wr_ch_arb_weight_high; /* 0x01c */
  83. u32 padding_3[3]; /* [0x020..0x028] */
  84. u32 rd_engine_en; /* 0x02c */
  85. u32 rd_doorbell; /* 0x030 */
  86. u32 padding_4; /* 0x034 */
  87. u32 rd_ch_arb_weight_low; /* 0x038 */
  88. u32 rd_ch_arb_weight_high; /* 0x03c */
  89. u32 padding_5[3]; /* [0x040..0x048] */
  90. /* eDMA interrupts registers */
  91. u32 wr_int_status; /* 0x04c */
  92. u32 padding_6; /* 0x050 */
  93. u32 wr_int_mask; /* 0x054 */
  94. u32 wr_int_clear; /* 0x058 */
  95. u32 wr_err_status; /* 0x05c */
  96. u32 wr_done_imwr_low; /* 0x060 */
  97. u32 wr_done_imwr_high; /* 0x064 */
  98. u32 wr_abort_imwr_low; /* 0x068 */
  99. u32 wr_abort_imwr_high; /* 0x06c */
  100. u32 wr_ch01_imwr_data; /* 0x070 */
  101. u32 wr_ch23_imwr_data; /* 0x074 */
  102. u32 wr_ch45_imwr_data; /* 0x078 */
  103. u32 wr_ch67_imwr_data; /* 0x07c */
  104. u32 padding_7[4]; /* [0x080..0x08c] */
  105. u32 wr_linked_list_err_en; /* 0x090 */
  106. u32 padding_8[3]; /* [0x094..0x09c] */
  107. u32 rd_int_status; /* 0x0a0 */
  108. u32 padding_9; /* 0x0a4 */
  109. u32 rd_int_mask; /* 0x0a8 */
  110. u32 rd_int_clear; /* 0x0ac */
  111. u32 padding_10; /* 0x0b0 */
  112. u32 rd_err_status_low; /* 0x0b4 */
  113. u32 rd_err_status_high; /* 0x0b8 */
  114. u32 padding_11[2]; /* [0x0bc..0x0c0] */
  115. u32 rd_linked_list_err_en; /* 0x0c4 */
  116. u32 padding_12; /* 0x0c8 */
  117. u32 rd_done_imwr_low; /* 0x0cc */
  118. u32 rd_done_imwr_high; /* 0x0d0 */
  119. u32 rd_abort_imwr_low; /* 0x0d4 */
  120. u32 rd_abort_imwr_high; /* 0x0d8 */
  121. u32 rd_ch01_imwr_data; /* 0x0dc */
  122. u32 rd_ch23_imwr_data; /* 0x0e0 */
  123. u32 rd_ch45_imwr_data; /* 0x0e4 */
  124. u32 rd_ch67_imwr_data; /* 0x0e8 */
  125. u32 padding_13[4]; /* [0x0ec..0x0f8] */
  126. /* eDMA channel context grouping */
  127. union dw_edma_v0_type {
  128. struct dw_edma_v0_legacy legacy; /* [0x0f8..0x120] */
  129. struct dw_edma_v0_unroll unroll; /* [0x0f8..0x1120] */
  130. } type;
  131. };
  132. struct dw_edma_v0_lli {
  133. u32 control;
  134. u32 transfer_size;
  135. u32 sar_low;
  136. u32 sar_high;
  137. u32 dar_low;
  138. u32 dar_high;
  139. };
  140. struct dw_edma_v0_llp {
  141. u32 control;
  142. u32 reserved;
  143. u32 llp_low;
  144. u32 llp_high;
  145. };
  146. #endif /* _DW_EDMA_V0_REGS_H */