dw-edma-core.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. * Synopsys DesignWare eDMA core driver
  5. *
  6. * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/device.h>
  10. #include <linux/kernel.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/dma/edma.h>
  17. #include <linux/dma-mapping.h>
  18. #include "dw-edma-core.h"
  19. #include "dw-edma-v0-core.h"
  20. #include "../dmaengine.h"
  21. #include "../virt-dma.h"
  22. static inline
  23. struct device *dchan2dev(struct dma_chan *dchan)
  24. {
  25. return &dchan->dev->device;
  26. }
  27. static inline
  28. struct device *chan2dev(struct dw_edma_chan *chan)
  29. {
  30. return &chan->vc.chan.dev->device;
  31. }
  32. static inline
  33. struct dw_edma_desc *vd2dw_edma_desc(struct virt_dma_desc *vd)
  34. {
  35. return container_of(vd, struct dw_edma_desc, vd);
  36. }
  37. static struct dw_edma_burst *dw_edma_alloc_burst(struct dw_edma_chunk *chunk)
  38. {
  39. struct dw_edma_burst *burst;
  40. burst = kzalloc(sizeof(*burst), GFP_NOWAIT);
  41. if (unlikely(!burst))
  42. return NULL;
  43. INIT_LIST_HEAD(&burst->list);
  44. if (chunk->burst) {
  45. /* Create and add new element into the linked list */
  46. chunk->bursts_alloc++;
  47. list_add_tail(&burst->list, &chunk->burst->list);
  48. } else {
  49. /* List head */
  50. chunk->bursts_alloc = 0;
  51. chunk->burst = burst;
  52. }
  53. return burst;
  54. }
  55. static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc)
  56. {
  57. struct dw_edma_chan *chan = desc->chan;
  58. struct dw_edma *dw = chan->chip->dw;
  59. struct dw_edma_chunk *chunk;
  60. chunk = kzalloc(sizeof(*chunk), GFP_NOWAIT);
  61. if (unlikely(!chunk))
  62. return NULL;
  63. INIT_LIST_HEAD(&chunk->list);
  64. chunk->chan = chan;
  65. /* Toggling change bit (CB) in each chunk, this is a mechanism to
  66. * inform the eDMA HW block that this is a new linked list ready
  67. * to be consumed.
  68. * - Odd chunks originate CB equal to 0
  69. * - Even chunks originate CB equal to 1
  70. */
  71. chunk->cb = !(desc->chunks_alloc % 2);
  72. chunk->ll_region.paddr = dw->ll_region.paddr + chan->ll_off;
  73. chunk->ll_region.vaddr = dw->ll_region.vaddr + chan->ll_off;
  74. if (desc->chunk) {
  75. /* Create and add new element into the linked list */
  76. if (!dw_edma_alloc_burst(chunk)) {
  77. kfree(chunk);
  78. return NULL;
  79. }
  80. desc->chunks_alloc++;
  81. list_add_tail(&chunk->list, &desc->chunk->list);
  82. } else {
  83. /* List head */
  84. chunk->burst = NULL;
  85. desc->chunks_alloc = 0;
  86. desc->chunk = chunk;
  87. }
  88. return chunk;
  89. }
  90. static struct dw_edma_desc *dw_edma_alloc_desc(struct dw_edma_chan *chan)
  91. {
  92. struct dw_edma_desc *desc;
  93. desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
  94. if (unlikely(!desc))
  95. return NULL;
  96. desc->chan = chan;
  97. if (!dw_edma_alloc_chunk(desc)) {
  98. kfree(desc);
  99. return NULL;
  100. }
  101. return desc;
  102. }
  103. static void dw_edma_free_burst(struct dw_edma_chunk *chunk)
  104. {
  105. struct dw_edma_burst *child, *_next;
  106. /* Remove all the list elements */
  107. list_for_each_entry_safe(child, _next, &chunk->burst->list, list) {
  108. list_del(&child->list);
  109. kfree(child);
  110. chunk->bursts_alloc--;
  111. }
  112. /* Remove the list head */
  113. kfree(child);
  114. chunk->burst = NULL;
  115. }
  116. static void dw_edma_free_chunk(struct dw_edma_desc *desc)
  117. {
  118. struct dw_edma_chunk *child, *_next;
  119. if (!desc->chunk)
  120. return;
  121. /* Remove all the list elements */
  122. list_for_each_entry_safe(child, _next, &desc->chunk->list, list) {
  123. dw_edma_free_burst(child);
  124. list_del(&child->list);
  125. kfree(child);
  126. desc->chunks_alloc--;
  127. }
  128. /* Remove the list head */
  129. kfree(child);
  130. desc->chunk = NULL;
  131. }
  132. static void dw_edma_free_desc(struct dw_edma_desc *desc)
  133. {
  134. dw_edma_free_chunk(desc);
  135. kfree(desc);
  136. }
  137. static void vchan_free_desc(struct virt_dma_desc *vdesc)
  138. {
  139. dw_edma_free_desc(vd2dw_edma_desc(vdesc));
  140. }
  141. static void dw_edma_start_transfer(struct dw_edma_chan *chan)
  142. {
  143. struct dw_edma_chunk *child;
  144. struct dw_edma_desc *desc;
  145. struct virt_dma_desc *vd;
  146. vd = vchan_next_desc(&chan->vc);
  147. if (!vd)
  148. return;
  149. desc = vd2dw_edma_desc(vd);
  150. if (!desc)
  151. return;
  152. child = list_first_entry_or_null(&desc->chunk->list,
  153. struct dw_edma_chunk, list);
  154. if (!child)
  155. return;
  156. dw_edma_v0_core_start(child, !desc->xfer_sz);
  157. desc->xfer_sz += child->ll_region.sz;
  158. dw_edma_free_burst(child);
  159. list_del(&child->list);
  160. kfree(child);
  161. desc->chunks_alloc--;
  162. }
  163. static int dw_edma_device_config(struct dma_chan *dchan,
  164. struct dma_slave_config *config)
  165. {
  166. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  167. memcpy(&chan->config, config, sizeof(*config));
  168. chan->configured = true;
  169. return 0;
  170. }
  171. static int dw_edma_device_pause(struct dma_chan *dchan)
  172. {
  173. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  174. int err = 0;
  175. if (!chan->configured)
  176. err = -EPERM;
  177. else if (chan->status != EDMA_ST_BUSY)
  178. err = -EPERM;
  179. else if (chan->request != EDMA_REQ_NONE)
  180. err = -EPERM;
  181. else
  182. chan->request = EDMA_REQ_PAUSE;
  183. return err;
  184. }
  185. static int dw_edma_device_resume(struct dma_chan *dchan)
  186. {
  187. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  188. int err = 0;
  189. if (!chan->configured) {
  190. err = -EPERM;
  191. } else if (chan->status != EDMA_ST_PAUSE) {
  192. err = -EPERM;
  193. } else if (chan->request != EDMA_REQ_NONE) {
  194. err = -EPERM;
  195. } else {
  196. chan->status = EDMA_ST_BUSY;
  197. dw_edma_start_transfer(chan);
  198. }
  199. return err;
  200. }
  201. static int dw_edma_device_terminate_all(struct dma_chan *dchan)
  202. {
  203. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  204. int err = 0;
  205. LIST_HEAD(head);
  206. if (!chan->configured) {
  207. /* Do nothing */
  208. } else if (chan->status == EDMA_ST_PAUSE) {
  209. chan->status = EDMA_ST_IDLE;
  210. chan->configured = false;
  211. } else if (chan->status == EDMA_ST_IDLE) {
  212. chan->configured = false;
  213. } else if (dw_edma_v0_core_ch_status(chan) == DMA_COMPLETE) {
  214. /*
  215. * The channel is in a false BUSY state, probably didn't
  216. * receive or lost an interrupt
  217. */
  218. chan->status = EDMA_ST_IDLE;
  219. chan->configured = false;
  220. } else if (chan->request > EDMA_REQ_PAUSE) {
  221. err = -EPERM;
  222. } else {
  223. chan->request = EDMA_REQ_STOP;
  224. }
  225. return err;
  226. }
  227. static void dw_edma_device_issue_pending(struct dma_chan *dchan)
  228. {
  229. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  230. unsigned long flags;
  231. spin_lock_irqsave(&chan->vc.lock, flags);
  232. if (chan->configured && chan->request == EDMA_REQ_NONE &&
  233. chan->status == EDMA_ST_IDLE && vchan_issue_pending(&chan->vc)) {
  234. chan->status = EDMA_ST_BUSY;
  235. dw_edma_start_transfer(chan);
  236. }
  237. spin_unlock_irqrestore(&chan->vc.lock, flags);
  238. }
  239. static enum dma_status
  240. dw_edma_device_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
  241. struct dma_tx_state *txstate)
  242. {
  243. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  244. struct dw_edma_desc *desc;
  245. struct virt_dma_desc *vd;
  246. unsigned long flags;
  247. enum dma_status ret;
  248. u32 residue = 0;
  249. ret = dma_cookie_status(dchan, cookie, txstate);
  250. if (ret == DMA_COMPLETE)
  251. return ret;
  252. if (ret == DMA_IN_PROGRESS && chan->status == EDMA_ST_PAUSE)
  253. ret = DMA_PAUSED;
  254. if (!txstate)
  255. goto ret_residue;
  256. spin_lock_irqsave(&chan->vc.lock, flags);
  257. vd = vchan_find_desc(&chan->vc, cookie);
  258. if (vd) {
  259. desc = vd2dw_edma_desc(vd);
  260. if (desc)
  261. residue = desc->alloc_sz - desc->xfer_sz;
  262. }
  263. spin_unlock_irqrestore(&chan->vc.lock, flags);
  264. ret_residue:
  265. dma_set_residue(txstate, residue);
  266. return ret;
  267. }
  268. static struct dma_async_tx_descriptor *
  269. dw_edma_device_transfer(struct dw_edma_transfer *xfer)
  270. {
  271. struct dw_edma_chan *chan = dchan2dw_edma_chan(xfer->dchan);
  272. enum dma_transfer_direction dir = xfer->direction;
  273. phys_addr_t src_addr, dst_addr;
  274. struct scatterlist *sg = NULL;
  275. struct dw_edma_chunk *chunk;
  276. struct dw_edma_burst *burst;
  277. struct dw_edma_desc *desc;
  278. u32 cnt;
  279. int i;
  280. if (!chan->configured)
  281. return NULL;
  282. switch (chan->config.direction) {
  283. case DMA_DEV_TO_MEM: /* local dma */
  284. if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ)
  285. break;
  286. return NULL;
  287. case DMA_MEM_TO_DEV: /* local dma */
  288. if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_WRITE)
  289. break;
  290. return NULL;
  291. default: /* remote dma */
  292. if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ)
  293. break;
  294. if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE)
  295. break;
  296. return NULL;
  297. }
  298. if (xfer->cyclic) {
  299. if (!xfer->xfer.cyclic.len || !xfer->xfer.cyclic.cnt)
  300. return NULL;
  301. } else {
  302. if (xfer->xfer.sg.len < 1)
  303. return NULL;
  304. }
  305. desc = dw_edma_alloc_desc(chan);
  306. if (unlikely(!desc))
  307. goto err_alloc;
  308. chunk = dw_edma_alloc_chunk(desc);
  309. if (unlikely(!chunk))
  310. goto err_alloc;
  311. src_addr = chan->config.src_addr;
  312. dst_addr = chan->config.dst_addr;
  313. if (xfer->cyclic) {
  314. cnt = xfer->xfer.cyclic.cnt;
  315. } else {
  316. cnt = xfer->xfer.sg.len;
  317. sg = xfer->xfer.sg.sgl;
  318. }
  319. for (i = 0; i < cnt; i++) {
  320. if (!xfer->cyclic && !sg)
  321. break;
  322. if (chunk->bursts_alloc == chan->ll_max) {
  323. chunk = dw_edma_alloc_chunk(desc);
  324. if (unlikely(!chunk))
  325. goto err_alloc;
  326. }
  327. burst = dw_edma_alloc_burst(chunk);
  328. if (unlikely(!burst))
  329. goto err_alloc;
  330. if (xfer->cyclic)
  331. burst->sz = xfer->xfer.cyclic.len;
  332. else
  333. burst->sz = sg_dma_len(sg);
  334. chunk->ll_region.sz += burst->sz;
  335. desc->alloc_sz += burst->sz;
  336. if (chan->dir == EDMA_DIR_WRITE) {
  337. burst->sar = src_addr;
  338. if (xfer->cyclic) {
  339. burst->dar = xfer->xfer.cyclic.paddr;
  340. } else {
  341. burst->dar = dst_addr;
  342. /* Unlike the typical assumption by other
  343. * drivers/IPs the peripheral memory isn't
  344. * a FIFO memory, in this case, it's a
  345. * linear memory and that why the source
  346. * and destination addresses are increased
  347. * by the same portion (data length)
  348. */
  349. }
  350. } else {
  351. burst->dar = dst_addr;
  352. if (xfer->cyclic) {
  353. burst->sar = xfer->xfer.cyclic.paddr;
  354. } else {
  355. burst->sar = src_addr;
  356. /* Unlike the typical assumption by other
  357. * drivers/IPs the peripheral memory isn't
  358. * a FIFO memory, in this case, it's a
  359. * linear memory and that why the source
  360. * and destination addresses are increased
  361. * by the same portion (data length)
  362. */
  363. }
  364. }
  365. if (!xfer->cyclic) {
  366. src_addr += sg_dma_len(sg);
  367. dst_addr += sg_dma_len(sg);
  368. sg = sg_next(sg);
  369. }
  370. }
  371. return vchan_tx_prep(&chan->vc, &desc->vd, xfer->flags);
  372. err_alloc:
  373. if (desc)
  374. dw_edma_free_desc(desc);
  375. return NULL;
  376. }
  377. static struct dma_async_tx_descriptor *
  378. dw_edma_device_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
  379. unsigned int len,
  380. enum dma_transfer_direction direction,
  381. unsigned long flags, void *context)
  382. {
  383. struct dw_edma_transfer xfer;
  384. xfer.dchan = dchan;
  385. xfer.direction = direction;
  386. xfer.xfer.sg.sgl = sgl;
  387. xfer.xfer.sg.len = len;
  388. xfer.flags = flags;
  389. xfer.cyclic = false;
  390. return dw_edma_device_transfer(&xfer);
  391. }
  392. static struct dma_async_tx_descriptor *
  393. dw_edma_device_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t paddr,
  394. size_t len, size_t count,
  395. enum dma_transfer_direction direction,
  396. unsigned long flags)
  397. {
  398. struct dw_edma_transfer xfer;
  399. xfer.dchan = dchan;
  400. xfer.direction = direction;
  401. xfer.xfer.cyclic.paddr = paddr;
  402. xfer.xfer.cyclic.len = len;
  403. xfer.xfer.cyclic.cnt = count;
  404. xfer.flags = flags;
  405. xfer.cyclic = true;
  406. return dw_edma_device_transfer(&xfer);
  407. }
  408. static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
  409. {
  410. struct dw_edma_desc *desc;
  411. struct virt_dma_desc *vd;
  412. unsigned long flags;
  413. dw_edma_v0_core_clear_done_int(chan);
  414. spin_lock_irqsave(&chan->vc.lock, flags);
  415. vd = vchan_next_desc(&chan->vc);
  416. if (vd) {
  417. switch (chan->request) {
  418. case EDMA_REQ_NONE:
  419. desc = vd2dw_edma_desc(vd);
  420. if (desc->chunks_alloc) {
  421. chan->status = EDMA_ST_BUSY;
  422. dw_edma_start_transfer(chan);
  423. } else {
  424. list_del(&vd->node);
  425. vchan_cookie_complete(vd);
  426. chan->status = EDMA_ST_IDLE;
  427. }
  428. break;
  429. case EDMA_REQ_STOP:
  430. list_del(&vd->node);
  431. vchan_cookie_complete(vd);
  432. chan->request = EDMA_REQ_NONE;
  433. chan->status = EDMA_ST_IDLE;
  434. break;
  435. case EDMA_REQ_PAUSE:
  436. chan->request = EDMA_REQ_NONE;
  437. chan->status = EDMA_ST_PAUSE;
  438. break;
  439. default:
  440. break;
  441. }
  442. }
  443. spin_unlock_irqrestore(&chan->vc.lock, flags);
  444. }
  445. static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
  446. {
  447. struct virt_dma_desc *vd;
  448. unsigned long flags;
  449. dw_edma_v0_core_clear_abort_int(chan);
  450. spin_lock_irqsave(&chan->vc.lock, flags);
  451. vd = vchan_next_desc(&chan->vc);
  452. if (vd) {
  453. list_del(&vd->node);
  454. vchan_cookie_complete(vd);
  455. }
  456. spin_unlock_irqrestore(&chan->vc.lock, flags);
  457. chan->request = EDMA_REQ_NONE;
  458. chan->status = EDMA_ST_IDLE;
  459. }
  460. static irqreturn_t dw_edma_interrupt(int irq, void *data, bool write)
  461. {
  462. struct dw_edma_irq *dw_irq = data;
  463. struct dw_edma *dw = dw_irq->dw;
  464. unsigned long total, pos, val;
  465. unsigned long off;
  466. u32 mask;
  467. if (write) {
  468. total = dw->wr_ch_cnt;
  469. off = 0;
  470. mask = dw_irq->wr_mask;
  471. } else {
  472. total = dw->rd_ch_cnt;
  473. off = dw->wr_ch_cnt;
  474. mask = dw_irq->rd_mask;
  475. }
  476. val = dw_edma_v0_core_status_done_int(dw, write ?
  477. EDMA_DIR_WRITE :
  478. EDMA_DIR_READ);
  479. val &= mask;
  480. for_each_set_bit(pos, &val, total) {
  481. struct dw_edma_chan *chan = &dw->chan[pos + off];
  482. dw_edma_done_interrupt(chan);
  483. }
  484. val = dw_edma_v0_core_status_abort_int(dw, write ?
  485. EDMA_DIR_WRITE :
  486. EDMA_DIR_READ);
  487. val &= mask;
  488. for_each_set_bit(pos, &val, total) {
  489. struct dw_edma_chan *chan = &dw->chan[pos + off];
  490. dw_edma_abort_interrupt(chan);
  491. }
  492. return IRQ_HANDLED;
  493. }
  494. static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data)
  495. {
  496. return dw_edma_interrupt(irq, data, true);
  497. }
  498. static inline irqreturn_t dw_edma_interrupt_read(int irq, void *data)
  499. {
  500. return dw_edma_interrupt(irq, data, false);
  501. }
  502. static irqreturn_t dw_edma_interrupt_common(int irq, void *data)
  503. {
  504. dw_edma_interrupt(irq, data, true);
  505. dw_edma_interrupt(irq, data, false);
  506. return IRQ_HANDLED;
  507. }
  508. static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
  509. {
  510. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  511. if (chan->status != EDMA_ST_IDLE)
  512. return -EBUSY;
  513. pm_runtime_get(chan->chip->dev);
  514. return 0;
  515. }
  516. static void dw_edma_free_chan_resources(struct dma_chan *dchan)
  517. {
  518. unsigned long timeout = jiffies + msecs_to_jiffies(5000);
  519. struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
  520. int ret;
  521. while (time_before(jiffies, timeout)) {
  522. ret = dw_edma_device_terminate_all(dchan);
  523. if (!ret)
  524. break;
  525. if (time_after_eq(jiffies, timeout))
  526. return;
  527. cpu_relax();
  528. }
  529. pm_runtime_put(chan->chip->dev);
  530. }
  531. static int dw_edma_channel_setup(struct dw_edma_chip *chip, bool write,
  532. u32 wr_alloc, u32 rd_alloc)
  533. {
  534. struct dw_edma_region *dt_region;
  535. struct device *dev = chip->dev;
  536. struct dw_edma *dw = chip->dw;
  537. struct dw_edma_chan *chan;
  538. size_t ll_chunk, dt_chunk;
  539. struct dw_edma_irq *irq;
  540. struct dma_device *dma;
  541. u32 i, j, cnt, ch_cnt;
  542. u32 alloc, off_alloc;
  543. int err = 0;
  544. u32 pos;
  545. ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
  546. ll_chunk = dw->ll_region.sz;
  547. dt_chunk = dw->dt_region.sz;
  548. /* Calculate linked list chunk for each channel */
  549. ll_chunk /= roundup_pow_of_two(ch_cnt);
  550. /* Calculate linked list chunk for each channel */
  551. dt_chunk /= roundup_pow_of_two(ch_cnt);
  552. if (write) {
  553. i = 0;
  554. cnt = dw->wr_ch_cnt;
  555. dma = &dw->wr_edma;
  556. alloc = wr_alloc;
  557. off_alloc = 0;
  558. } else {
  559. i = dw->wr_ch_cnt;
  560. cnt = dw->rd_ch_cnt;
  561. dma = &dw->rd_edma;
  562. alloc = rd_alloc;
  563. off_alloc = wr_alloc;
  564. }
  565. INIT_LIST_HEAD(&dma->channels);
  566. for (j = 0; (alloc || dw->nr_irqs == 1) && j < cnt; j++, i++) {
  567. chan = &dw->chan[i];
  568. dt_region = devm_kzalloc(dev, sizeof(*dt_region), GFP_KERNEL);
  569. if (!dt_region)
  570. return -ENOMEM;
  571. chan->vc.chan.private = dt_region;
  572. chan->chip = chip;
  573. chan->id = j;
  574. chan->dir = write ? EDMA_DIR_WRITE : EDMA_DIR_READ;
  575. chan->configured = false;
  576. chan->request = EDMA_REQ_NONE;
  577. chan->status = EDMA_ST_IDLE;
  578. chan->ll_off = (ll_chunk * i);
  579. chan->ll_max = (ll_chunk / EDMA_LL_SZ) - 1;
  580. chan->dt_off = (dt_chunk * i);
  581. dev_vdbg(dev, "L. List:\tChannel %s[%u] off=0x%.8lx, max_cnt=%u\n",
  582. write ? "write" : "read", j,
  583. chan->ll_off, chan->ll_max);
  584. if (dw->nr_irqs == 1)
  585. pos = 0;
  586. else
  587. pos = off_alloc + (j % alloc);
  588. irq = &dw->irq[pos];
  589. if (write)
  590. irq->wr_mask |= BIT(j);
  591. else
  592. irq->rd_mask |= BIT(j);
  593. irq->dw = dw;
  594. memcpy(&chan->msi, &irq->msi, sizeof(chan->msi));
  595. dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n",
  596. write ? "write" : "read", j,
  597. chan->msi.address_hi, chan->msi.address_lo,
  598. chan->msi.data);
  599. chan->vc.desc_free = vchan_free_desc;
  600. vchan_init(&chan->vc, dma);
  601. dt_region->paddr = dw->dt_region.paddr + chan->dt_off;
  602. dt_region->vaddr = dw->dt_region.vaddr + chan->dt_off;
  603. dt_region->sz = dt_chunk;
  604. dev_vdbg(dev, "Data:\tChannel %s[%u] off=0x%.8lx\n",
  605. write ? "write" : "read", j, chan->dt_off);
  606. dw_edma_v0_core_device_config(chan);
  607. }
  608. /* Set DMA channel capabilities */
  609. dma_cap_zero(dma->cap_mask);
  610. dma_cap_set(DMA_SLAVE, dma->cap_mask);
  611. dma_cap_set(DMA_CYCLIC, dma->cap_mask);
  612. dma_cap_set(DMA_PRIVATE, dma->cap_mask);
  613. dma->directions = BIT(write ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV);
  614. dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  615. dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  616. dma->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  617. dma->chancnt = cnt;
  618. /* Set DMA channel callbacks */
  619. dma->dev = chip->dev;
  620. dma->device_alloc_chan_resources = dw_edma_alloc_chan_resources;
  621. dma->device_free_chan_resources = dw_edma_free_chan_resources;
  622. dma->device_config = dw_edma_device_config;
  623. dma->device_pause = dw_edma_device_pause;
  624. dma->device_resume = dw_edma_device_resume;
  625. dma->device_terminate_all = dw_edma_device_terminate_all;
  626. dma->device_issue_pending = dw_edma_device_issue_pending;
  627. dma->device_tx_status = dw_edma_device_tx_status;
  628. dma->device_prep_slave_sg = dw_edma_device_prep_slave_sg;
  629. dma->device_prep_dma_cyclic = dw_edma_device_prep_dma_cyclic;
  630. dma_set_max_seg_size(dma->dev, U32_MAX);
  631. /* Register DMA device */
  632. err = dma_async_device_register(dma);
  633. return err;
  634. }
  635. static inline void dw_edma_dec_irq_alloc(int *nr_irqs, u32 *alloc, u16 cnt)
  636. {
  637. if (*nr_irqs && *alloc < cnt) {
  638. (*alloc)++;
  639. (*nr_irqs)--;
  640. }
  641. }
  642. static inline void dw_edma_add_irq_mask(u32 *mask, u32 alloc, u16 cnt)
  643. {
  644. while (*mask * alloc < cnt)
  645. (*mask)++;
  646. }
  647. static int dw_edma_irq_request(struct dw_edma_chip *chip,
  648. u32 *wr_alloc, u32 *rd_alloc)
  649. {
  650. struct device *dev = chip->dev;
  651. struct dw_edma *dw = chip->dw;
  652. u32 wr_mask = 1;
  653. u32 rd_mask = 1;
  654. int i, err = 0;
  655. u32 ch_cnt;
  656. int irq;
  657. ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
  658. if (dw->nr_irqs < 1)
  659. return -EINVAL;
  660. if (dw->nr_irqs == 1) {
  661. /* Common IRQ shared among all channels */
  662. irq = dw->ops->irq_vector(dev, 0);
  663. err = request_irq(irq, dw_edma_interrupt_common,
  664. IRQF_SHARED, dw->name, &dw->irq[0]);
  665. if (err) {
  666. dw->nr_irqs = 0;
  667. return err;
  668. }
  669. if (irq_get_msi_desc(irq))
  670. get_cached_msi_msg(irq, &dw->irq[0].msi);
  671. } else {
  672. /* Distribute IRQs equally among all channels */
  673. int tmp = dw->nr_irqs;
  674. while (tmp && (*wr_alloc + *rd_alloc) < ch_cnt) {
  675. dw_edma_dec_irq_alloc(&tmp, wr_alloc, dw->wr_ch_cnt);
  676. dw_edma_dec_irq_alloc(&tmp, rd_alloc, dw->rd_ch_cnt);
  677. }
  678. dw_edma_add_irq_mask(&wr_mask, *wr_alloc, dw->wr_ch_cnt);
  679. dw_edma_add_irq_mask(&rd_mask, *rd_alloc, dw->rd_ch_cnt);
  680. for (i = 0; i < (*wr_alloc + *rd_alloc); i++) {
  681. irq = dw->ops->irq_vector(dev, i);
  682. err = request_irq(irq,
  683. i < *wr_alloc ?
  684. dw_edma_interrupt_write :
  685. dw_edma_interrupt_read,
  686. IRQF_SHARED, dw->name,
  687. &dw->irq[i]);
  688. if (err) {
  689. dw->nr_irqs = i;
  690. return err;
  691. }
  692. if (irq_get_msi_desc(irq))
  693. get_cached_msi_msg(irq, &dw->irq[i].msi);
  694. }
  695. dw->nr_irqs = i;
  696. }
  697. return err;
  698. }
  699. int dw_edma_probe(struct dw_edma_chip *chip)
  700. {
  701. struct device *dev;
  702. struct dw_edma *dw;
  703. u32 wr_alloc = 0;
  704. u32 rd_alloc = 0;
  705. int i, err;
  706. if (!chip)
  707. return -EINVAL;
  708. dev = chip->dev;
  709. if (!dev)
  710. return -EINVAL;
  711. dw = chip->dw;
  712. if (!dw || !dw->irq || !dw->ops || !dw->ops->irq_vector)
  713. return -EINVAL;
  714. raw_spin_lock_init(&dw->lock);
  715. /* Find out how many write channels are supported by hardware */
  716. dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE);
  717. if (!dw->wr_ch_cnt)
  718. return -EINVAL;
  719. /* Find out how many read channels are supported by hardware */
  720. dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ);
  721. if (!dw->rd_ch_cnt)
  722. return -EINVAL;
  723. dev_vdbg(dev, "Channels:\twrite=%d, read=%d\n",
  724. dw->wr_ch_cnt, dw->rd_ch_cnt);
  725. /* Allocate channels */
  726. dw->chan = devm_kcalloc(dev, dw->wr_ch_cnt + dw->rd_ch_cnt,
  727. sizeof(*dw->chan), GFP_KERNEL);
  728. if (!dw->chan)
  729. return -ENOMEM;
  730. snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%d", chip->id);
  731. /* Disable eDMA, only to establish the ideal initial conditions */
  732. dw_edma_v0_core_off(dw);
  733. /* Request IRQs */
  734. err = dw_edma_irq_request(chip, &wr_alloc, &rd_alloc);
  735. if (err)
  736. return err;
  737. /* Setup write channels */
  738. err = dw_edma_channel_setup(chip, true, wr_alloc, rd_alloc);
  739. if (err)
  740. goto err_irq_free;
  741. /* Setup read channels */
  742. err = dw_edma_channel_setup(chip, false, wr_alloc, rd_alloc);
  743. if (err)
  744. goto err_irq_free;
  745. /* Power management */
  746. pm_runtime_enable(dev);
  747. /* Turn debugfs on */
  748. dw_edma_v0_core_debugfs_on(chip);
  749. return 0;
  750. err_irq_free:
  751. for (i = (dw->nr_irqs - 1); i >= 0; i--)
  752. free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
  753. dw->nr_irqs = 0;
  754. return err;
  755. }
  756. EXPORT_SYMBOL_GPL(dw_edma_probe);
  757. int dw_edma_remove(struct dw_edma_chip *chip)
  758. {
  759. struct dw_edma_chan *chan, *_chan;
  760. struct device *dev = chip->dev;
  761. struct dw_edma *dw = chip->dw;
  762. int i;
  763. /* Disable eDMA */
  764. dw_edma_v0_core_off(dw);
  765. /* Free irqs */
  766. for (i = (dw->nr_irqs - 1); i >= 0; i--)
  767. free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
  768. /* Power management */
  769. pm_runtime_disable(dev);
  770. /* Deregister eDMA device */
  771. dma_async_device_unregister(&dw->wr_edma);
  772. list_for_each_entry_safe(chan, _chan, &dw->wr_edma.channels,
  773. vc.chan.device_node) {
  774. tasklet_kill(&chan->vc.task);
  775. list_del(&chan->vc.chan.device_node);
  776. }
  777. dma_async_device_unregister(&dw->rd_edma);
  778. list_for_each_entry_safe(chan, _chan, &dw->rd_edma.channels,
  779. vc.chan.device_node) {
  780. tasklet_kill(&chan->vc.task);
  781. list_del(&chan->vc.chan.device_node);
  782. }
  783. /* Turn debugfs off */
  784. dw_edma_v0_core_debugfs_off();
  785. return 0;
  786. }
  787. EXPORT_SYMBOL_GPL(dw_edma_remove);
  788. MODULE_LICENSE("GPL v2");
  789. MODULE_DESCRIPTION("Synopsys DesignWare eDMA controller core driver");
  790. MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");