dw-axi-dmac.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383
  1. // SPDX-License-Identifier: GPL-2.0
  2. // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
  3. /*
  4. * Synopsys DesignWare AXI DMA Controller driver.
  5. *
  6. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  7. */
  8. #ifndef _AXI_DMA_PLATFORM_H
  9. #define _AXI_DMA_PLATFORM_H
  10. #include <linux/bitops.h>
  11. #include <linux/clk.h>
  12. #include <linux/device.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/types.h>
  15. #include "../virt-dma.h"
  16. #define DMAC_MAX_CHANNELS 16
  17. #define DMAC_MAX_MASTERS 2
  18. #define DMAC_MAX_BLK_SIZE 0x200000
  19. struct dw_axi_dma_hcfg {
  20. u32 nr_channels;
  21. u32 nr_masters;
  22. u32 m_data_width;
  23. u32 block_size[DMAC_MAX_CHANNELS];
  24. u32 priority[DMAC_MAX_CHANNELS];
  25. /* maximum supported axi burst length */
  26. u32 axi_rw_burst_len;
  27. /* Register map for DMAX_NUM_CHANNELS <= 8 */
  28. bool reg_map_8_channels;
  29. bool restrict_axi_burst_len;
  30. };
  31. struct axi_dma_chan {
  32. struct axi_dma_chip *chip;
  33. void __iomem *chan_regs;
  34. u8 id;
  35. u8 hw_handshake_num;
  36. atomic_t descs_allocated;
  37. struct dma_pool *desc_pool;
  38. struct virt_dma_chan vc;
  39. struct axi_dma_desc *desc;
  40. struct dma_slave_config config;
  41. enum dma_transfer_direction direction;
  42. bool cyclic;
  43. /* these other elements are all protected by vc.lock */
  44. bool is_paused;
  45. };
  46. struct dw_axi_dma {
  47. struct dma_device dma;
  48. struct dw_axi_dma_hcfg *hdata;
  49. struct device_dma_parameters dma_parms;
  50. /* channels */
  51. struct axi_dma_chan *chan;
  52. };
  53. struct axi_dma_chip {
  54. struct device *dev;
  55. int irq;
  56. void __iomem *regs;
  57. void __iomem *apb_regs;
  58. struct clk *core_clk;
  59. struct clk *cfgr_clk;
  60. struct dw_axi_dma *dw;
  61. spinlock_t lock;
  62. };
  63. /* LLI == Linked List Item */
  64. struct __packed axi_dma_lli {
  65. __le64 sar;
  66. __le64 dar;
  67. __le32 block_ts_lo;
  68. __le32 block_ts_hi;
  69. __le64 llp;
  70. __le32 ctl_lo;
  71. __le32 ctl_hi;
  72. __le32 sstat;
  73. __le32 dstat;
  74. __le32 status_lo;
  75. __le32 status_hi;
  76. __le32 reserved_lo;
  77. __le32 reserved_hi;
  78. };
  79. struct axi_dma_hw_desc {
  80. struct axi_dma_lli *lli;
  81. dma_addr_t llp;
  82. u32 len;
  83. };
  84. struct axi_dma_desc {
  85. struct axi_dma_hw_desc *hw_desc;
  86. struct virt_dma_desc vd;
  87. struct axi_dma_chan *chan;
  88. u32 completed_blocks;
  89. u32 length;
  90. u32 period_len;
  91. };
  92. static inline struct device *dchan2dev(struct dma_chan *dchan)
  93. {
  94. return &dchan->dev->device;
  95. }
  96. static inline struct device *chan2dev(struct axi_dma_chan *chan)
  97. {
  98. return &chan->vc.chan.dev->device;
  99. }
  100. static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
  101. {
  102. return container_of(vd, struct axi_dma_desc, vd);
  103. }
  104. static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
  105. {
  106. return container_of(vc, struct axi_dma_chan, vc);
  107. }
  108. static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
  109. {
  110. return vc_to_axi_dma_chan(to_virt_chan(dchan));
  111. }
  112. #define COMMON_REG_LEN 0x100
  113. #define CHAN_REG_LEN 0x100
  114. /* Common registers offset */
  115. #define DMAC_ID 0x000 /* R DMAC ID */
  116. #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
  117. #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
  118. #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
  119. #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
  120. #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
  121. #define DMAC_CHSUSPREG 0x020 /* R/W DMAC Channel Suspend */
  122. #define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
  123. #define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
  124. #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
  125. #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
  126. #define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
  127. #define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
  128. /* DMA channel registers offset */
  129. #define CH_SAR 0x000 /* R/W Chan Source Address */
  130. #define CH_DAR 0x008 /* R/W Chan Destination Address */
  131. #define CH_BLOCK_TS 0x010 /* R/W Chan Block Transfer Size */
  132. #define CH_CTL 0x018 /* R/W Chan Control */
  133. #define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
  134. #define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
  135. #define CH_CFG 0x020 /* R/W Chan Configuration */
  136. #define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
  137. #define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
  138. #define CH_LLP 0x028 /* R/W Chan Linked List Pointer */
  139. #define CH_STATUS 0x030 /* R Chan Status */
  140. #define CH_SWHSSRC 0x038 /* R/W Chan SW Handshake Source */
  141. #define CH_SWHSDST 0x040 /* R/W Chan SW Handshake Destination */
  142. #define CH_BLK_TFR_RESUMEREQ 0x048 /* W Chan Block Transfer Resume Req */
  143. #define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
  144. #define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
  145. #define CH_SSTAT 0x060 /* R Chan Source Status */
  146. #define CH_DSTAT 0x068 /* R Chan Destination Status */
  147. #define CH_SSTATAR 0x070 /* R/W Chan Source Status Fetch Addr */
  148. #define CH_DSTATAR 0x078 /* R/W Chan Destination Status Fetch Addr */
  149. #define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt Status Enable */
  150. #define CH_INTSTATUS 0x088 /* R/W Chan Interrupt Status */
  151. #define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
  152. #define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
  153. /* These Apb registers are used by Intel KeemBay SoC */
  154. #define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
  155. #define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
  156. #define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
  157. #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
  158. #define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
  159. #define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
  160. #define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
  161. #define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
  162. #define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
  163. #define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
  164. #define DMA_APB_HS_SEL_BIT_SIZE 0x08 /* HW handshake bits per channel */
  165. #define DMA_APB_HS_SEL_MASK 0xFF /* HW handshake select masks */
  166. #define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
  167. #define DMA_REG_MAP_CH_REF 0x08 /* Channel count to choose register map */
  168. /* DMAC_CFG */
  169. #define DMAC_EN_POS 0
  170. #define DMAC_EN_MASK BIT(DMAC_EN_POS)
  171. #define INT_EN_POS 1
  172. #define INT_EN_MASK BIT(INT_EN_POS)
  173. #define DMAC_CHAN_EN_SHIFT 0
  174. #define DMAC_CHAN_EN_WE_SHIFT 8
  175. #define DMAC_CHAN_SUSP_SHIFT 16
  176. #define DMAC_CHAN_SUSP_WE_SHIFT 24
  177. /* DMAC_CHEN2 */
  178. #define DMAC_CHAN_EN2_WE_SHIFT 16
  179. /* DMAC_CHSUSP */
  180. #define DMAC_CHAN_SUSP2_SHIFT 0
  181. #define DMAC_CHAN_SUSP2_WE_SHIFT 16
  182. /* CH_CTL_H */
  183. #define CH_CTL_H_ARLEN_EN BIT(6)
  184. #define CH_CTL_H_ARLEN_POS 7
  185. #define CH_CTL_H_AWLEN_EN BIT(15)
  186. #define CH_CTL_H_AWLEN_POS 16
  187. enum {
  188. DWAXIDMAC_ARWLEN_1 = 0,
  189. DWAXIDMAC_ARWLEN_2 = 1,
  190. DWAXIDMAC_ARWLEN_4 = 3,
  191. DWAXIDMAC_ARWLEN_8 = 7,
  192. DWAXIDMAC_ARWLEN_16 = 15,
  193. DWAXIDMAC_ARWLEN_32 = 31,
  194. DWAXIDMAC_ARWLEN_64 = 63,
  195. DWAXIDMAC_ARWLEN_128 = 127,
  196. DWAXIDMAC_ARWLEN_256 = 255,
  197. DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1,
  198. DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256
  199. };
  200. #define CH_CTL_H_LLI_LAST BIT(30)
  201. #define CH_CTL_H_LLI_VALID BIT(31)
  202. /* CH_CTL_L */
  203. #define CH_CTL_L_LAST_WRITE_EN BIT(30)
  204. #define CH_CTL_L_DST_MSIZE_POS 18
  205. #define CH_CTL_L_SRC_MSIZE_POS 14
  206. enum {
  207. DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
  208. DWAXIDMAC_BURST_TRANS_LEN_4,
  209. DWAXIDMAC_BURST_TRANS_LEN_8,
  210. DWAXIDMAC_BURST_TRANS_LEN_16,
  211. DWAXIDMAC_BURST_TRANS_LEN_32,
  212. DWAXIDMAC_BURST_TRANS_LEN_64,
  213. DWAXIDMAC_BURST_TRANS_LEN_128,
  214. DWAXIDMAC_BURST_TRANS_LEN_256,
  215. DWAXIDMAC_BURST_TRANS_LEN_512,
  216. DWAXIDMAC_BURST_TRANS_LEN_1024
  217. };
  218. #define CH_CTL_L_DST_WIDTH_POS 11
  219. #define CH_CTL_L_SRC_WIDTH_POS 8
  220. #define CH_CTL_L_DST_INC_POS 6
  221. #define CH_CTL_L_SRC_INC_POS 4
  222. enum {
  223. DWAXIDMAC_CH_CTL_L_INC = 0,
  224. DWAXIDMAC_CH_CTL_L_NOINC
  225. };
  226. #define CH_CTL_L_DST_MAST BIT(2)
  227. #define CH_CTL_L_SRC_MAST BIT(0)
  228. /* CH_CFG_H */
  229. #define CH_CFG_H_PRIORITY_POS 17
  230. #define CH_CFG_H_DST_PER_POS 12
  231. #define CH_CFG_H_SRC_PER_POS 7
  232. #define CH_CFG_H_HS_SEL_DST_POS 4
  233. #define CH_CFG_H_HS_SEL_SRC_POS 3
  234. /* CH_CFG_TT_FC */
  235. #define CH_CFG_L_SRC_PER 4
  236. #define CH_CFG_L_DST_PER 11
  237. enum {
  238. DWAXIDMAC_HS_SEL_HW = 0,
  239. DWAXIDMAC_HS_SEL_SW
  240. };
  241. #define CH_CFG_H_TT_FC_POS 0
  242. enum {
  243. DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,
  244. DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
  245. DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
  246. DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
  247. DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
  248. DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
  249. DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
  250. DWAXIDMAC_TT_FC_PER_TO_PER_DST
  251. };
  252. /* CH_CFG_L */
  253. #define CH_CFG_L_DST_MULTBLK_TYPE_POS 2
  254. #define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0
  255. enum {
  256. DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,
  257. DWAXIDMAC_MBLK_TYPE_RELOAD,
  258. DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
  259. DWAXIDMAC_MBLK_TYPE_LL
  260. };
  261. /**
  262. * DW AXI DMA channel interrupts
  263. *
  264. * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
  265. * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
  266. * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
  267. * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
  268. * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
  269. * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
  270. * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
  271. * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
  272. * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
  273. * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
  274. * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
  275. * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
  276. * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
  277. * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
  278. * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
  279. * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
  280. * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
  281. * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
  282. * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
  283. * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
  284. * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
  285. * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
  286. * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
  287. * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
  288. * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
  289. * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
  290. * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
  291. * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
  292. */
  293. enum {
  294. DWAXIDMAC_IRQ_NONE = 0,
  295. DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0),
  296. DWAXIDMAC_IRQ_DMA_TRF = BIT(1),
  297. DWAXIDMAC_IRQ_SRC_TRAN = BIT(3),
  298. DWAXIDMAC_IRQ_DST_TRAN = BIT(4),
  299. DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5),
  300. DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6),
  301. DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7),
  302. DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8),
  303. DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9),
  304. DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10),
  305. DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11),
  306. DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12),
  307. DWAXIDMAC_IRQ_INVALID_ERR = BIT(13),
  308. DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14),
  309. DWAXIDMAC_IRQ_DEC_ERR = BIT(16),
  310. DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17),
  311. DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18),
  312. DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19),
  313. DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20),
  314. DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21),
  315. DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27),
  316. DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28),
  317. DWAXIDMAC_IRQ_SUSPENDED = BIT(29),
  318. DWAXIDMAC_IRQ_DISABLED = BIT(30),
  319. DWAXIDMAC_IRQ_ABORTED = BIT(31),
  320. DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)),
  321. DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)
  322. };
  323. enum {
  324. DWAXIDMAC_TRANS_WIDTH_8 = 0,
  325. DWAXIDMAC_TRANS_WIDTH_16,
  326. DWAXIDMAC_TRANS_WIDTH_32,
  327. DWAXIDMAC_TRANS_WIDTH_64,
  328. DWAXIDMAC_TRANS_WIDTH_128,
  329. DWAXIDMAC_TRANS_WIDTH_256,
  330. DWAXIDMAC_TRANS_WIDTH_512,
  331. DWAXIDMAC_TRANS_WIDTH_MAX = DWAXIDMAC_TRANS_WIDTH_512
  332. };
  333. #endif /* _AXI_DMA_PLATFORM_H */