dw-axi-dmac-platform.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
  3. /*
  4. * Synopsys DesignWare AXI DMA Controller driver.
  5. *
  6. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/err.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/io-64-nonatomic-lo-hi.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_dma.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/property.h>
  26. #include <linux/slab.h>
  27. #include <linux/types.h>
  28. #include "dw-axi-dmac.h"
  29. #include "../dmaengine.h"
  30. #include "../virt-dma.h"
  31. /*
  32. * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
  33. * master data bus width up to 512 bits (for both AXI master interfaces), but
  34. * it depends on IP block configurarion.
  35. */
  36. #define AXI_DMA_BUSWIDTHS \
  37. (DMA_SLAVE_BUSWIDTH_1_BYTE | \
  38. DMA_SLAVE_BUSWIDTH_2_BYTES | \
  39. DMA_SLAVE_BUSWIDTH_4_BYTES | \
  40. DMA_SLAVE_BUSWIDTH_8_BYTES | \
  41. DMA_SLAVE_BUSWIDTH_16_BYTES | \
  42. DMA_SLAVE_BUSWIDTH_32_BYTES | \
  43. DMA_SLAVE_BUSWIDTH_64_BYTES)
  44. static inline void
  45. axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
  46. {
  47. iowrite32(val, chip->regs + reg);
  48. }
  49. static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg)
  50. {
  51. return ioread32(chip->regs + reg);
  52. }
  53. static inline void
  54. axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
  55. {
  56. iowrite32(val, chan->chan_regs + reg);
  57. }
  58. static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg)
  59. {
  60. return ioread32(chan->chan_regs + reg);
  61. }
  62. static inline void
  63. axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
  64. {
  65. /*
  66. * We split one 64 bit write for two 32 bit write as some HW doesn't
  67. * support 64 bit access.
  68. */
  69. iowrite32(lower_32_bits(val), chan->chan_regs + reg);
  70. iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
  71. }
  72. static inline void axi_dma_disable(struct axi_dma_chip *chip)
  73. {
  74. u32 val;
  75. unsigned long flags;
  76. spin_lock_irqsave(&chip->lock, flags);
  77. val = axi_dma_ioread32(chip, DMAC_CFG);
  78. val &= ~DMAC_EN_MASK;
  79. axi_dma_iowrite32(chip, DMAC_CFG, val);
  80. spin_unlock_irqrestore(&chip->lock, flags);
  81. }
  82. static inline void axi_dma_enable(struct axi_dma_chip *chip)
  83. {
  84. u32 val;
  85. unsigned long flags;
  86. spin_lock_irqsave(&chip->lock, flags);
  87. val = axi_dma_ioread32(chip, DMAC_CFG);
  88. val |= DMAC_EN_MASK;
  89. axi_dma_iowrite32(chip, DMAC_CFG, val);
  90. spin_unlock_irqrestore(&chip->lock, flags);
  91. }
  92. static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
  93. {
  94. u32 val;
  95. unsigned long flags;
  96. spin_lock_irqsave(&chip->lock, flags);
  97. val = axi_dma_ioread32(chip, DMAC_CFG);
  98. val &= ~INT_EN_MASK;
  99. axi_dma_iowrite32(chip, DMAC_CFG, val);
  100. spin_unlock_irqrestore(&chip->lock, flags);
  101. }
  102. static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
  103. {
  104. u32 val;
  105. unsigned long flags;
  106. spin_lock_irqsave(&chip->lock, flags);
  107. val = axi_dma_ioread32(chip, DMAC_CFG);
  108. val |= INT_EN_MASK;
  109. axi_dma_iowrite32(chip, DMAC_CFG, val);
  110. spin_unlock_irqrestore(&chip->lock, flags);
  111. }
  112. static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
  113. {
  114. u32 val;
  115. if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) {
  116. axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE);
  117. } else {
  118. val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
  119. val &= ~irq_mask;
  120. axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
  121. }
  122. }
  123. static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask)
  124. {
  125. axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask);
  126. }
  127. static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask)
  128. {
  129. axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask);
  130. }
  131. static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask)
  132. {
  133. axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask);
  134. }
  135. static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
  136. {
  137. return axi_chan_ioread32(chan, CH_INTSTATUS);
  138. }
  139. static inline void axi_chan_disable(struct axi_dma_chan *chan)
  140. {
  141. u32 val;
  142. val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
  143. val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
  144. if (chan->chip->dw->hdata->reg_map_8_channels)
  145. val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
  146. else
  147. val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
  148. axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
  149. }
  150. static inline void axi_chan_enable(struct axi_dma_chan *chan)
  151. {
  152. u32 val;
  153. val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
  154. if (chan->chip->dw->hdata->reg_map_8_channels)
  155. val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
  156. BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
  157. else
  158. val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
  159. BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
  160. axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
  161. }
  162. static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
  163. {
  164. u32 val;
  165. val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
  166. return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
  167. }
  168. static void axi_dma_hw_init(struct axi_dma_chip *chip)
  169. {
  170. u32 i;
  171. for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
  172. axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
  173. axi_chan_disable(&chip->dw->chan[i]);
  174. }
  175. }
  176. static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
  177. dma_addr_t dst, size_t len)
  178. {
  179. u32 max_width = chan->chip->dw->hdata->m_data_width;
  180. return __ffs(src | dst | len | BIT(max_width));
  181. }
  182. static inline const char *axi_chan_name(struct axi_dma_chan *chan)
  183. {
  184. return dma_chan_name(&chan->vc.chan);
  185. }
  186. static struct axi_dma_desc *axi_desc_alloc(u32 num)
  187. {
  188. struct axi_dma_desc *desc;
  189. desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
  190. if (!desc)
  191. return NULL;
  192. desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
  193. if (!desc->hw_desc) {
  194. kfree(desc);
  195. return NULL;
  196. }
  197. return desc;
  198. }
  199. static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
  200. dma_addr_t *addr)
  201. {
  202. struct axi_dma_lli *lli;
  203. dma_addr_t phys;
  204. lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
  205. if (unlikely(!lli)) {
  206. dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
  207. axi_chan_name(chan));
  208. return NULL;
  209. }
  210. atomic_inc(&chan->descs_allocated);
  211. *addr = phys;
  212. return lli;
  213. }
  214. static void axi_desc_put(struct axi_dma_desc *desc)
  215. {
  216. struct axi_dma_chan *chan = desc->chan;
  217. int count = atomic_read(&chan->descs_allocated);
  218. struct axi_dma_hw_desc *hw_desc;
  219. int descs_put;
  220. for (descs_put = 0; descs_put < count; descs_put++) {
  221. hw_desc = &desc->hw_desc[descs_put];
  222. dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
  223. }
  224. kfree(desc->hw_desc);
  225. kfree(desc);
  226. atomic_sub(descs_put, &chan->descs_allocated);
  227. dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
  228. axi_chan_name(chan), descs_put,
  229. atomic_read(&chan->descs_allocated));
  230. }
  231. static void vchan_desc_put(struct virt_dma_desc *vdesc)
  232. {
  233. axi_desc_put(vd_to_axi_desc(vdesc));
  234. }
  235. static enum dma_status
  236. dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
  237. struct dma_tx_state *txstate)
  238. {
  239. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  240. struct virt_dma_desc *vdesc;
  241. enum dma_status status;
  242. u32 completed_length;
  243. unsigned long flags;
  244. u32 completed_blocks;
  245. size_t bytes = 0;
  246. u32 length;
  247. u32 len;
  248. status = dma_cookie_status(dchan, cookie, txstate);
  249. if (status == DMA_COMPLETE || !txstate)
  250. return status;
  251. spin_lock_irqsave(&chan->vc.lock, flags);
  252. vdesc = vchan_find_desc(&chan->vc, cookie);
  253. if (vdesc) {
  254. length = vd_to_axi_desc(vdesc)->length;
  255. completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
  256. len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
  257. completed_length = completed_blocks * len;
  258. bytes = length - completed_length;
  259. }
  260. spin_unlock_irqrestore(&chan->vc.lock, flags);
  261. dma_set_residue(txstate, bytes);
  262. return status;
  263. }
  264. static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
  265. {
  266. desc->lli->llp = cpu_to_le64(adr);
  267. }
  268. static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
  269. {
  270. axi_chan_iowrite64(chan, CH_LLP, adr);
  271. }
  272. static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
  273. {
  274. u32 offset = DMAC_APB_BYTE_WR_CH_EN;
  275. u32 reg_width, val;
  276. if (!chan->chip->apb_regs) {
  277. dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
  278. return;
  279. }
  280. reg_width = __ffs(chan->config.dst_addr_width);
  281. if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
  282. offset = DMAC_APB_HALFWORD_WR_CH_EN;
  283. val = ioread32(chan->chip->apb_regs + offset);
  284. if (set)
  285. val |= BIT(chan->id);
  286. else
  287. val &= ~BIT(chan->id);
  288. iowrite32(val, chan->chip->apb_regs + offset);
  289. }
  290. /* Called in chan locked context */
  291. static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
  292. struct axi_dma_desc *first)
  293. {
  294. u32 priority = chan->chip->dw->hdata->priority[chan->id];
  295. u32 reg_l, reg_h, irq_mask;
  296. u8 lms = 0; /* Select AXI0 master for LLI fetching */
  297. if (unlikely(axi_chan_is_hw_enable(chan))) {
  298. dev_err(chan2dev(chan), "%s is non-idle!\n",
  299. axi_chan_name(chan));
  300. return;
  301. }
  302. axi_dma_enable(chan->chip);
  303. reg_l = (DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_DST_MULTBLK_TYPE_POS |
  304. DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
  305. reg_h = (DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC << CH_CFG_H_TT_FC_POS |
  306. priority << CH_CFG_H_PRIORITY_POS |
  307. DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
  308. DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
  309. switch (chan->direction) {
  310. case DMA_MEM_TO_DEV:
  311. dw_axi_dma_set_byte_halfword(chan, true);
  312. reg_h |= (chan->config.device_fc ?
  313. DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
  314. DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
  315. << CH_CFG_H_TT_FC_POS;
  316. if (chan->chip->apb_regs)
  317. reg_h |= (chan->id << CH_CFG_H_DST_PER_POS);
  318. reg_l |= chan->hw_handshake_num << CH_CFG_L_DST_PER;
  319. break;
  320. case DMA_DEV_TO_MEM:
  321. reg_h |= (chan->config.device_fc ?
  322. DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
  323. DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
  324. << CH_CFG_H_TT_FC_POS;
  325. if (chan->chip->apb_regs)
  326. reg_h |= (chan->id << CH_CFG_H_SRC_PER_POS);
  327. reg_l |= chan->hw_handshake_num << CH_CFG_L_SRC_PER;
  328. break;
  329. default:
  330. break;
  331. }
  332. axi_chan_iowrite32(chan, CH_CFG_L, reg_l);
  333. axi_chan_iowrite32(chan, CH_CFG_H, reg_h);
  334. write_chan_llp(chan, first->hw_desc[0].llp | lms);
  335. irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
  336. axi_chan_irq_sig_set(chan, irq_mask);
  337. /* Generate 'suspend' status but don't generate interrupt */
  338. irq_mask |= DWAXIDMAC_IRQ_SUSPENDED;
  339. axi_chan_irq_set(chan, irq_mask);
  340. axi_chan_enable(chan);
  341. }
  342. static void axi_chan_start_first_queued(struct axi_dma_chan *chan)
  343. {
  344. struct axi_dma_desc *desc;
  345. struct virt_dma_desc *vd;
  346. vd = vchan_next_desc(&chan->vc);
  347. if (!vd)
  348. return;
  349. desc = vd_to_axi_desc(vd);
  350. dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan),
  351. vd->tx.cookie);
  352. axi_chan_block_xfer_start(chan, desc);
  353. }
  354. static void dma_chan_issue_pending(struct dma_chan *dchan)
  355. {
  356. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  357. unsigned long flags;
  358. spin_lock_irqsave(&chan->vc.lock, flags);
  359. if (vchan_issue_pending(&chan->vc))
  360. axi_chan_start_first_queued(chan);
  361. spin_unlock_irqrestore(&chan->vc.lock, flags);
  362. }
  363. static void dw_axi_dma_synchronize(struct dma_chan *dchan)
  364. {
  365. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  366. vchan_synchronize(&chan->vc);
  367. }
  368. static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
  369. {
  370. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  371. /* ASSERT: channel is idle */
  372. if (axi_chan_is_hw_enable(chan)) {
  373. dev_err(chan2dev(chan), "%s is non-idle!\n",
  374. axi_chan_name(chan));
  375. return -EBUSY;
  376. }
  377. /* LLI address must be aligned to a 64-byte boundary */
  378. chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
  379. chan->chip->dev,
  380. sizeof(struct axi_dma_lli),
  381. 64, 0);
  382. if (!chan->desc_pool) {
  383. dev_err(chan2dev(chan), "No memory for descriptors\n");
  384. return -ENOMEM;
  385. }
  386. dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
  387. pm_runtime_get(chan->chip->dev);
  388. return 0;
  389. }
  390. static void dma_chan_free_chan_resources(struct dma_chan *dchan)
  391. {
  392. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  393. /* ASSERT: channel is idle */
  394. if (axi_chan_is_hw_enable(chan))
  395. dev_err(dchan2dev(dchan), "%s is non-idle!\n",
  396. axi_chan_name(chan));
  397. axi_chan_disable(chan);
  398. axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
  399. vchan_free_chan_resources(&chan->vc);
  400. dma_pool_destroy(chan->desc_pool);
  401. chan->desc_pool = NULL;
  402. dev_vdbg(dchan2dev(dchan),
  403. "%s: free resources, descriptor still allocated: %u\n",
  404. axi_chan_name(chan), atomic_read(&chan->descs_allocated));
  405. pm_runtime_put(chan->chip->dev);
  406. }
  407. static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
  408. {
  409. struct axi_dma_chip *chip = chan->chip;
  410. unsigned long reg_value, val;
  411. if (!chip->apb_regs) {
  412. dev_dbg(chip->dev, "apb_regs not initialized\n");
  413. return;
  414. }
  415. /*
  416. * An unused DMA channel has a default value of 0x3F.
  417. * Lock the DMA channel by assign a handshake number to the channel.
  418. * Unlock the DMA channel by assign 0x3F to the channel.
  419. */
  420. if (set)
  421. val = chan->hw_handshake_num;
  422. else
  423. val = UNUSED_CHANNEL;
  424. reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
  425. /* Channel is already allocated, set handshake as per channel ID */
  426. /* 64 bit write should handle for 8 channels */
  427. reg_value &= ~(DMA_APB_HS_SEL_MASK <<
  428. (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
  429. reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
  430. lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
  431. return;
  432. }
  433. /*
  434. * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
  435. * as 1, it understands that the current block is the final block in the
  436. * transfer and completes the DMA transfer operation at the end of current
  437. * block transfer.
  438. */
  439. static void set_desc_last(struct axi_dma_hw_desc *desc)
  440. {
  441. u32 val;
  442. val = le32_to_cpu(desc->lli->ctl_hi);
  443. val |= CH_CTL_H_LLI_LAST;
  444. desc->lli->ctl_hi = cpu_to_le32(val);
  445. }
  446. static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
  447. {
  448. desc->lli->sar = cpu_to_le64(adr);
  449. }
  450. static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
  451. {
  452. desc->lli->dar = cpu_to_le64(adr);
  453. }
  454. static void set_desc_src_master(struct axi_dma_hw_desc *desc)
  455. {
  456. u32 val;
  457. /* Select AXI0 for source master */
  458. val = le32_to_cpu(desc->lli->ctl_lo);
  459. val &= ~CH_CTL_L_SRC_MAST;
  460. desc->lli->ctl_lo = cpu_to_le32(val);
  461. }
  462. static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
  463. struct axi_dma_desc *desc)
  464. {
  465. u32 val;
  466. /* Select AXI1 for source master if available */
  467. val = le32_to_cpu(hw_desc->lli->ctl_lo);
  468. if (desc->chan->chip->dw->hdata->nr_masters > 1)
  469. val |= CH_CTL_L_DST_MAST;
  470. else
  471. val &= ~CH_CTL_L_DST_MAST;
  472. hw_desc->lli->ctl_lo = cpu_to_le32(val);
  473. }
  474. static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
  475. struct axi_dma_hw_desc *hw_desc,
  476. dma_addr_t mem_addr, size_t len)
  477. {
  478. unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
  479. unsigned int reg_width;
  480. unsigned int mem_width;
  481. dma_addr_t device_addr;
  482. size_t axi_block_ts;
  483. size_t block_ts;
  484. u32 ctllo, ctlhi;
  485. u32 burst_len;
  486. axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
  487. mem_width = __ffs(data_width | mem_addr | len);
  488. if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
  489. mem_width = DWAXIDMAC_TRANS_WIDTH_32;
  490. if (!IS_ALIGNED(mem_addr, 4)) {
  491. dev_err(chan->chip->dev, "invalid buffer alignment\n");
  492. return -EINVAL;
  493. }
  494. switch (chan->direction) {
  495. case DMA_MEM_TO_DEV:
  496. reg_width = __ffs(chan->config.dst_addr_width);
  497. device_addr = chan->config.dst_addr;
  498. ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
  499. mem_width << CH_CTL_L_SRC_WIDTH_POS |
  500. DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
  501. DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
  502. block_ts = len >> mem_width;
  503. break;
  504. case DMA_DEV_TO_MEM:
  505. reg_width = __ffs(chan->config.src_addr_width);
  506. device_addr = chan->config.src_addr;
  507. ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
  508. mem_width << CH_CTL_L_DST_WIDTH_POS |
  509. DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
  510. DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
  511. block_ts = len >> reg_width;
  512. break;
  513. default:
  514. return -EINVAL;
  515. }
  516. if (block_ts > axi_block_ts)
  517. return -EINVAL;
  518. hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
  519. if (unlikely(!hw_desc->lli))
  520. return -ENOMEM;
  521. ctlhi = CH_CTL_H_LLI_VALID;
  522. if (chan->chip->dw->hdata->restrict_axi_burst_len) {
  523. burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
  524. ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
  525. burst_len << CH_CTL_H_ARLEN_POS |
  526. burst_len << CH_CTL_H_AWLEN_POS;
  527. }
  528. hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
  529. if (chan->direction == DMA_MEM_TO_DEV) {
  530. write_desc_sar(hw_desc, mem_addr);
  531. write_desc_dar(hw_desc, device_addr);
  532. } else {
  533. write_desc_sar(hw_desc, device_addr);
  534. write_desc_dar(hw_desc, mem_addr);
  535. }
  536. hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
  537. ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
  538. DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
  539. hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
  540. set_desc_src_master(hw_desc);
  541. hw_desc->len = len;
  542. return 0;
  543. }
  544. static size_t calculate_block_len(struct axi_dma_chan *chan,
  545. dma_addr_t dma_addr, size_t buf_len,
  546. enum dma_transfer_direction direction)
  547. {
  548. u32 data_width, reg_width, mem_width;
  549. size_t axi_block_ts, block_len;
  550. axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
  551. switch (direction) {
  552. case DMA_MEM_TO_DEV:
  553. data_width = BIT(chan->chip->dw->hdata->m_data_width);
  554. mem_width = __ffs(data_width | dma_addr | buf_len);
  555. if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
  556. mem_width = DWAXIDMAC_TRANS_WIDTH_32;
  557. block_len = axi_block_ts << mem_width;
  558. break;
  559. case DMA_DEV_TO_MEM:
  560. reg_width = __ffs(chan->config.src_addr_width);
  561. block_len = axi_block_ts << reg_width;
  562. break;
  563. default:
  564. block_len = 0;
  565. }
  566. return block_len;
  567. }
  568. static struct dma_async_tx_descriptor *
  569. dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
  570. size_t buf_len, size_t period_len,
  571. enum dma_transfer_direction direction,
  572. unsigned long flags)
  573. {
  574. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  575. struct axi_dma_hw_desc *hw_desc = NULL;
  576. struct axi_dma_desc *desc = NULL;
  577. dma_addr_t src_addr = dma_addr;
  578. u32 num_periods, num_segments;
  579. size_t axi_block_len;
  580. u32 total_segments;
  581. u32 segment_len;
  582. unsigned int i;
  583. int status;
  584. u64 llp = 0;
  585. u8 lms = 0; /* Select AXI0 master for LLI fetching */
  586. num_periods = buf_len / period_len;
  587. axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
  588. if (axi_block_len == 0)
  589. return NULL;
  590. num_segments = DIV_ROUND_UP(period_len, axi_block_len);
  591. segment_len = DIV_ROUND_UP(period_len, num_segments);
  592. total_segments = num_periods * num_segments;
  593. desc = axi_desc_alloc(total_segments);
  594. if (unlikely(!desc))
  595. goto err_desc_get;
  596. chan->direction = direction;
  597. desc->chan = chan;
  598. chan->cyclic = true;
  599. desc->length = 0;
  600. desc->period_len = period_len;
  601. for (i = 0; i < total_segments; i++) {
  602. hw_desc = &desc->hw_desc[i];
  603. status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
  604. segment_len);
  605. if (status < 0)
  606. goto err_desc_get;
  607. desc->length += hw_desc->len;
  608. /* Set end-of-link to the linked descriptor, so that cyclic
  609. * callback function can be triggered during interrupt.
  610. */
  611. set_desc_last(hw_desc);
  612. src_addr += segment_len;
  613. }
  614. llp = desc->hw_desc[0].llp;
  615. /* Managed transfer list */
  616. do {
  617. hw_desc = &desc->hw_desc[--total_segments];
  618. write_desc_llp(hw_desc, llp | lms);
  619. llp = hw_desc->llp;
  620. } while (total_segments);
  621. dw_axi_dma_set_hw_channel(chan, true);
  622. return vchan_tx_prep(&chan->vc, &desc->vd, flags);
  623. err_desc_get:
  624. if (desc)
  625. axi_desc_put(desc);
  626. return NULL;
  627. }
  628. static struct dma_async_tx_descriptor *
  629. dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
  630. unsigned int sg_len,
  631. enum dma_transfer_direction direction,
  632. unsigned long flags, void *context)
  633. {
  634. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  635. struct axi_dma_hw_desc *hw_desc = NULL;
  636. struct axi_dma_desc *desc = NULL;
  637. u32 num_segments, segment_len;
  638. unsigned int loop = 0;
  639. struct scatterlist *sg;
  640. size_t axi_block_len;
  641. u32 len, num_sgs = 0;
  642. unsigned int i;
  643. dma_addr_t mem;
  644. int status;
  645. u64 llp = 0;
  646. u8 lms = 0; /* Select AXI0 master for LLI fetching */
  647. if (unlikely(!is_slave_direction(direction) || !sg_len))
  648. return NULL;
  649. mem = sg_dma_address(sgl);
  650. len = sg_dma_len(sgl);
  651. axi_block_len = calculate_block_len(chan, mem, len, direction);
  652. if (axi_block_len == 0)
  653. return NULL;
  654. for_each_sg(sgl, sg, sg_len, i)
  655. num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
  656. desc = axi_desc_alloc(num_sgs);
  657. if (unlikely(!desc))
  658. goto err_desc_get;
  659. desc->chan = chan;
  660. desc->length = 0;
  661. chan->direction = direction;
  662. for_each_sg(sgl, sg, sg_len, i) {
  663. mem = sg_dma_address(sg);
  664. len = sg_dma_len(sg);
  665. num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
  666. segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
  667. do {
  668. hw_desc = &desc->hw_desc[loop++];
  669. status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
  670. if (status < 0)
  671. goto err_desc_get;
  672. desc->length += hw_desc->len;
  673. len -= segment_len;
  674. mem += segment_len;
  675. } while (len >= segment_len);
  676. }
  677. /* Set end-of-link to the last link descriptor of list */
  678. set_desc_last(&desc->hw_desc[num_sgs - 1]);
  679. /* Managed transfer list */
  680. do {
  681. hw_desc = &desc->hw_desc[--num_sgs];
  682. write_desc_llp(hw_desc, llp | lms);
  683. llp = hw_desc->llp;
  684. } while (num_sgs);
  685. dw_axi_dma_set_hw_channel(chan, true);
  686. return vchan_tx_prep(&chan->vc, &desc->vd, flags);
  687. err_desc_get:
  688. if (desc)
  689. axi_desc_put(desc);
  690. return NULL;
  691. }
  692. static struct dma_async_tx_descriptor *
  693. dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
  694. dma_addr_t src_adr, size_t len, unsigned long flags)
  695. {
  696. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  697. size_t block_ts, max_block_ts, xfer_len;
  698. struct axi_dma_hw_desc *hw_desc = NULL;
  699. struct axi_dma_desc *desc = NULL;
  700. u32 xfer_width, reg, num;
  701. u64 llp = 0;
  702. u8 lms = 0; /* Select AXI0 master for LLI fetching */
  703. dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
  704. axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
  705. max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
  706. xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
  707. num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
  708. desc = axi_desc_alloc(num);
  709. if (unlikely(!desc))
  710. goto err_desc_get;
  711. desc->chan = chan;
  712. num = 0;
  713. desc->length = 0;
  714. while (len) {
  715. xfer_len = len;
  716. hw_desc = &desc->hw_desc[num];
  717. /*
  718. * Take care for the alignment.
  719. * Actually source and destination widths can be different, but
  720. * make them same to be simpler.
  721. */
  722. xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len);
  723. /*
  724. * block_ts indicates the total number of data of width
  725. * to be transferred in a DMA block transfer.
  726. * BLOCK_TS register should be set to block_ts - 1
  727. */
  728. block_ts = xfer_len >> xfer_width;
  729. if (block_ts > max_block_ts) {
  730. block_ts = max_block_ts;
  731. xfer_len = max_block_ts << xfer_width;
  732. }
  733. hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
  734. if (unlikely(!hw_desc->lli))
  735. goto err_desc_get;
  736. write_desc_sar(hw_desc, src_adr);
  737. write_desc_dar(hw_desc, dst_adr);
  738. hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
  739. reg = CH_CTL_H_LLI_VALID;
  740. if (chan->chip->dw->hdata->restrict_axi_burst_len) {
  741. u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
  742. reg |= (CH_CTL_H_ARLEN_EN |
  743. burst_len << CH_CTL_H_ARLEN_POS |
  744. CH_CTL_H_AWLEN_EN |
  745. burst_len << CH_CTL_H_AWLEN_POS);
  746. }
  747. hw_desc->lli->ctl_hi = cpu_to_le32(reg);
  748. reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
  749. DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
  750. xfer_width << CH_CTL_L_DST_WIDTH_POS |
  751. xfer_width << CH_CTL_L_SRC_WIDTH_POS |
  752. DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
  753. DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
  754. hw_desc->lli->ctl_lo = cpu_to_le32(reg);
  755. set_desc_src_master(hw_desc);
  756. set_desc_dest_master(hw_desc, desc);
  757. hw_desc->len = xfer_len;
  758. desc->length += hw_desc->len;
  759. /* update the length and addresses for the next loop cycle */
  760. len -= xfer_len;
  761. dst_adr += xfer_len;
  762. src_adr += xfer_len;
  763. num++;
  764. }
  765. /* Set end-of-link to the last link descriptor of list */
  766. set_desc_last(&desc->hw_desc[num - 1]);
  767. /* Managed transfer list */
  768. do {
  769. hw_desc = &desc->hw_desc[--num];
  770. write_desc_llp(hw_desc, llp | lms);
  771. llp = hw_desc->llp;
  772. } while (num);
  773. return vchan_tx_prep(&chan->vc, &desc->vd, flags);
  774. err_desc_get:
  775. if (desc)
  776. axi_desc_put(desc);
  777. return NULL;
  778. }
  779. static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
  780. struct dma_slave_config *config)
  781. {
  782. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  783. memcpy(&chan->config, config, sizeof(*config));
  784. return 0;
  785. }
  786. static void axi_chan_dump_lli(struct axi_dma_chan *chan,
  787. struct axi_dma_hw_desc *desc)
  788. {
  789. dev_err(dchan2dev(&chan->vc.chan),
  790. "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
  791. le64_to_cpu(desc->lli->sar),
  792. le64_to_cpu(desc->lli->dar),
  793. le64_to_cpu(desc->lli->llp),
  794. le32_to_cpu(desc->lli->block_ts_lo),
  795. le32_to_cpu(desc->lli->ctl_hi),
  796. le32_to_cpu(desc->lli->ctl_lo));
  797. }
  798. static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
  799. struct axi_dma_desc *desc_head)
  800. {
  801. int count = atomic_read(&chan->descs_allocated);
  802. int i;
  803. for (i = 0; i < count; i++)
  804. axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
  805. }
  806. static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
  807. {
  808. struct virt_dma_desc *vd;
  809. unsigned long flags;
  810. spin_lock_irqsave(&chan->vc.lock, flags);
  811. axi_chan_disable(chan);
  812. /* The bad descriptor currently is in the head of vc list */
  813. vd = vchan_next_desc(&chan->vc);
  814. /* Remove the completed descriptor from issued list */
  815. list_del(&vd->node);
  816. /* WARN about bad descriptor */
  817. dev_err(chan2dev(chan),
  818. "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
  819. axi_chan_name(chan), vd->tx.cookie, status);
  820. axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
  821. vchan_cookie_complete(vd);
  822. /* Try to restart the controller */
  823. axi_chan_start_first_queued(chan);
  824. spin_unlock_irqrestore(&chan->vc.lock, flags);
  825. }
  826. static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
  827. {
  828. int count = atomic_read(&chan->descs_allocated);
  829. struct axi_dma_hw_desc *hw_desc;
  830. struct axi_dma_desc *desc;
  831. struct virt_dma_desc *vd;
  832. unsigned long flags;
  833. u64 llp;
  834. int i;
  835. spin_lock_irqsave(&chan->vc.lock, flags);
  836. if (unlikely(axi_chan_is_hw_enable(chan))) {
  837. dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n",
  838. axi_chan_name(chan));
  839. axi_chan_disable(chan);
  840. }
  841. /* The completed descriptor currently is in the head of vc list */
  842. vd = vchan_next_desc(&chan->vc);
  843. if (chan->cyclic) {
  844. desc = vd_to_axi_desc(vd);
  845. if (desc) {
  846. llp = lo_hi_readq(chan->chan_regs + CH_LLP);
  847. for (i = 0; i < count; i++) {
  848. hw_desc = &desc->hw_desc[i];
  849. if (hw_desc->llp == llp) {
  850. axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
  851. hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
  852. desc->completed_blocks = i;
  853. if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
  854. vchan_cyclic_callback(vd);
  855. break;
  856. }
  857. }
  858. axi_chan_enable(chan);
  859. }
  860. } else {
  861. /* Remove the completed descriptor from issued list before completing */
  862. list_del(&vd->node);
  863. vchan_cookie_complete(vd);
  864. /* Submit queued descriptors after processing the completed ones */
  865. axi_chan_start_first_queued(chan);
  866. }
  867. spin_unlock_irqrestore(&chan->vc.lock, flags);
  868. }
  869. static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
  870. {
  871. struct axi_dma_chip *chip = dev_id;
  872. struct dw_axi_dma *dw = chip->dw;
  873. struct axi_dma_chan *chan;
  874. u32 status, i;
  875. /* Disable DMAC inerrupts. We'll enable them after processing chanels */
  876. axi_dma_irq_disable(chip);
  877. /* Poll, clear and process every chanel interrupt status */
  878. for (i = 0; i < dw->hdata->nr_channels; i++) {
  879. chan = &dw->chan[i];
  880. status = axi_chan_irq_read(chan);
  881. axi_chan_irq_clear(chan, status);
  882. dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
  883. axi_chan_name(chan), i, status);
  884. if (status & DWAXIDMAC_IRQ_ALL_ERR)
  885. axi_chan_handle_err(chan, status);
  886. else if (status & DWAXIDMAC_IRQ_DMA_TRF)
  887. axi_chan_block_xfer_complete(chan);
  888. }
  889. /* Re-enable interrupts */
  890. axi_dma_irq_enable(chip);
  891. return IRQ_HANDLED;
  892. }
  893. static int dma_chan_terminate_all(struct dma_chan *dchan)
  894. {
  895. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  896. u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
  897. unsigned long flags;
  898. u32 val;
  899. int ret;
  900. LIST_HEAD(head);
  901. axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_ALL);
  902. axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
  903. axi_chan_disable(chan);
  904. ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
  905. !(val & chan_active), 1000, 10000);
  906. if (ret == -ETIMEDOUT)
  907. dev_warn(dchan2dev(dchan),
  908. "%s failed to stop\n", axi_chan_name(chan));
  909. if (chan->direction != DMA_MEM_TO_MEM)
  910. dw_axi_dma_set_hw_channel(chan, false);
  911. if (chan->direction == DMA_MEM_TO_DEV)
  912. dw_axi_dma_set_byte_halfword(chan, false);
  913. spin_lock_irqsave(&chan->vc.lock, flags);
  914. vchan_get_all_descriptors(&chan->vc, &head);
  915. chan->cyclic = false;
  916. spin_unlock_irqrestore(&chan->vc.lock, flags);
  917. vchan_dma_desc_free_list(&chan->vc, &head);
  918. dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan));
  919. return 0;
  920. }
  921. static int dma_chan_pause(struct dma_chan *dchan)
  922. {
  923. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  924. unsigned long flags;
  925. unsigned int timeout = 20; /* timeout iterations */
  926. u32 val;
  927. spin_lock_irqsave(&chan->vc.lock, flags);
  928. if (chan->chip->dw->hdata->reg_map_8_channels) {
  929. val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
  930. val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
  931. BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
  932. axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
  933. } else {
  934. val = BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
  935. BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
  936. axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
  937. }
  938. do {
  939. if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
  940. break;
  941. udelay(2);
  942. } while (--timeout);
  943. axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED);
  944. chan->is_paused = true;
  945. spin_unlock_irqrestore(&chan->vc.lock, flags);
  946. return timeout ? 0 : -EAGAIN;
  947. }
  948. /* Called in chan locked context */
  949. static inline void axi_chan_resume(struct axi_dma_chan *chan)
  950. {
  951. u32 val;
  952. val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
  953. if (chan->chip->dw->hdata->reg_map_8_channels) {
  954. val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
  955. val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
  956. axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
  957. } else {
  958. val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
  959. val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
  960. axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
  961. }
  962. chan->is_paused = false;
  963. }
  964. static int dma_chan_resume(struct dma_chan *dchan)
  965. {
  966. struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
  967. unsigned long flags;
  968. spin_lock_irqsave(&chan->vc.lock, flags);
  969. if (chan->is_paused)
  970. axi_chan_resume(chan);
  971. spin_unlock_irqrestore(&chan->vc.lock, flags);
  972. return 0;
  973. }
  974. static int axi_dma_suspend(struct axi_dma_chip *chip)
  975. {
  976. axi_dma_irq_disable(chip);
  977. axi_dma_disable(chip);
  978. clk_disable_unprepare(chip->core_clk);
  979. clk_disable_unprepare(chip->cfgr_clk);
  980. return 0;
  981. }
  982. static int axi_dma_resume(struct axi_dma_chip *chip)
  983. {
  984. int ret;
  985. ret = clk_prepare_enable(chip->cfgr_clk);
  986. if (ret < 0)
  987. return ret;
  988. ret = clk_prepare_enable(chip->core_clk);
  989. if (ret < 0)
  990. return ret;
  991. axi_dma_enable(chip);
  992. axi_dma_irq_enable(chip);
  993. return 0;
  994. }
  995. static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
  996. {
  997. struct axi_dma_chip *chip = dev_get_drvdata(dev);
  998. return axi_dma_suspend(chip);
  999. }
  1000. static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
  1001. {
  1002. struct axi_dma_chip *chip = dev_get_drvdata(dev);
  1003. return axi_dma_resume(chip);
  1004. }
  1005. static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
  1006. struct of_dma *ofdma)
  1007. {
  1008. struct dw_axi_dma *dw = ofdma->of_dma_data;
  1009. struct axi_dma_chan *chan;
  1010. struct dma_chan *dchan;
  1011. dchan = dma_get_any_slave_channel(&dw->dma);
  1012. if (!dchan)
  1013. return NULL;
  1014. chan = dchan_to_axi_dma_chan(dchan);
  1015. chan->hw_handshake_num = dma_spec->args[0];
  1016. return dchan;
  1017. }
  1018. static int parse_device_properties(struct axi_dma_chip *chip)
  1019. {
  1020. struct device *dev = chip->dev;
  1021. u32 tmp, carr[DMAC_MAX_CHANNELS];
  1022. int ret;
  1023. ret = device_property_read_u32(dev, "dma-channels", &tmp);
  1024. if (ret)
  1025. return ret;
  1026. if (tmp == 0 || tmp > DMAC_MAX_CHANNELS)
  1027. return -EINVAL;
  1028. chip->dw->hdata->nr_channels = tmp;
  1029. if (tmp <= DMA_REG_MAP_CH_REF)
  1030. chip->dw->hdata->reg_map_8_channels = true;
  1031. ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
  1032. if (ret)
  1033. return ret;
  1034. if (tmp == 0 || tmp > DMAC_MAX_MASTERS)
  1035. return -EINVAL;
  1036. chip->dw->hdata->nr_masters = tmp;
  1037. ret = device_property_read_u32(dev, "snps,data-width", &tmp);
  1038. if (ret)
  1039. return ret;
  1040. if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX)
  1041. return -EINVAL;
  1042. chip->dw->hdata->m_data_width = tmp;
  1043. ret = device_property_read_u32_array(dev, "snps,block-size", carr,
  1044. chip->dw->hdata->nr_channels);
  1045. if (ret)
  1046. return ret;
  1047. for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
  1048. if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE)
  1049. return -EINVAL;
  1050. chip->dw->hdata->block_size[tmp] = carr[tmp];
  1051. }
  1052. ret = device_property_read_u32_array(dev, "snps,priority", carr,
  1053. chip->dw->hdata->nr_channels);
  1054. if (ret)
  1055. return ret;
  1056. /* Priority value must be programmed within [0:nr_channels-1] range */
  1057. for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
  1058. if (carr[tmp] >= chip->dw->hdata->nr_channels)
  1059. return -EINVAL;
  1060. chip->dw->hdata->priority[tmp] = carr[tmp];
  1061. }
  1062. /* axi-max-burst-len is optional property */
  1063. ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp);
  1064. if (!ret) {
  1065. if (tmp > DWAXIDMAC_ARWLEN_MAX + 1)
  1066. return -EINVAL;
  1067. if (tmp < DWAXIDMAC_ARWLEN_MIN + 1)
  1068. return -EINVAL;
  1069. chip->dw->hdata->restrict_axi_burst_len = true;
  1070. chip->dw->hdata->axi_rw_burst_len = tmp;
  1071. }
  1072. return 0;
  1073. }
  1074. static int dw_probe(struct platform_device *pdev)
  1075. {
  1076. struct device_node *node = pdev->dev.of_node;
  1077. struct axi_dma_chip *chip;
  1078. struct resource *mem;
  1079. struct dw_axi_dma *dw;
  1080. struct dw_axi_dma_hcfg *hdata;
  1081. u32 i;
  1082. int ret;
  1083. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  1084. if (!chip)
  1085. return -ENOMEM;
  1086. dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
  1087. if (!dw)
  1088. return -ENOMEM;
  1089. hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
  1090. if (!hdata)
  1091. return -ENOMEM;
  1092. chip->dw = dw;
  1093. chip->dev = &pdev->dev;
  1094. chip->dw->hdata = hdata;
  1095. spin_lock_init(&chip->lock);
  1096. chip->irq = platform_get_irq(pdev, 0);
  1097. if (chip->irq < 0)
  1098. return chip->irq;
  1099. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1100. chip->regs = devm_ioremap_resource(chip->dev, mem);
  1101. if (IS_ERR(chip->regs))
  1102. return PTR_ERR(chip->regs);
  1103. if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
  1104. chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
  1105. if (IS_ERR(chip->apb_regs))
  1106. return PTR_ERR(chip->apb_regs);
  1107. }
  1108. chip->core_clk = devm_clk_get(chip->dev, "core-clk");
  1109. if (IS_ERR(chip->core_clk))
  1110. return PTR_ERR(chip->core_clk);
  1111. chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
  1112. if (IS_ERR(chip->cfgr_clk))
  1113. return PTR_ERR(chip->cfgr_clk);
  1114. ret = parse_device_properties(chip);
  1115. if (ret)
  1116. return ret;
  1117. dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
  1118. sizeof(*dw->chan), GFP_KERNEL);
  1119. if (!dw->chan)
  1120. return -ENOMEM;
  1121. ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
  1122. IRQF_SHARED, KBUILD_MODNAME, chip);
  1123. if (ret)
  1124. return ret;
  1125. INIT_LIST_HEAD(&dw->dma.channels);
  1126. for (i = 0; i < hdata->nr_channels; i++) {
  1127. struct axi_dma_chan *chan = &dw->chan[i];
  1128. chan->chip = chip;
  1129. chan->id = i;
  1130. chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
  1131. atomic_set(&chan->descs_allocated, 0);
  1132. chan->vc.desc_free = vchan_desc_put;
  1133. vchan_init(&chan->vc, &dw->dma);
  1134. }
  1135. /* Set capabilities */
  1136. dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
  1137. dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
  1138. dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
  1139. /* DMA capabilities */
  1140. dw->dma.chancnt = hdata->nr_channels;
  1141. dw->dma.max_burst = hdata->axi_rw_burst_len;
  1142. dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
  1143. dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
  1144. dw->dma.directions = BIT(DMA_MEM_TO_MEM);
  1145. dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
  1146. dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  1147. dw->dma.dev = chip->dev;
  1148. dw->dma.device_tx_status = dma_chan_tx_status;
  1149. dw->dma.device_issue_pending = dma_chan_issue_pending;
  1150. dw->dma.device_terminate_all = dma_chan_terminate_all;
  1151. dw->dma.device_pause = dma_chan_pause;
  1152. dw->dma.device_resume = dma_chan_resume;
  1153. dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
  1154. dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
  1155. dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
  1156. dw->dma.device_synchronize = dw_axi_dma_synchronize;
  1157. dw->dma.device_config = dw_axi_dma_chan_slave_config;
  1158. dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
  1159. dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
  1160. /*
  1161. * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
  1162. * supported blocks is 1024. Device register width is 4 bytes.
  1163. * Therefore, set constraint to 1024 * 4.
  1164. */
  1165. dw->dma.dev->dma_parms = &dw->dma_parms;
  1166. dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
  1167. platform_set_drvdata(pdev, chip);
  1168. pm_runtime_enable(chip->dev);
  1169. /*
  1170. * We can't just call pm_runtime_get here instead of
  1171. * pm_runtime_get_noresume + axi_dma_resume because we need
  1172. * driver to work also without Runtime PM.
  1173. */
  1174. pm_runtime_get_noresume(chip->dev);
  1175. ret = axi_dma_resume(chip);
  1176. if (ret < 0)
  1177. goto err_pm_disable;
  1178. axi_dma_hw_init(chip);
  1179. pm_runtime_put(chip->dev);
  1180. ret = dmaenginem_async_device_register(&dw->dma);
  1181. if (ret)
  1182. goto err_pm_disable;
  1183. /* Register with OF helpers for DMA lookups */
  1184. ret = of_dma_controller_register(pdev->dev.of_node,
  1185. dw_axi_dma_of_xlate, dw);
  1186. if (ret < 0)
  1187. dev_warn(&pdev->dev,
  1188. "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
  1189. dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
  1190. dw->hdata->nr_channels);
  1191. return 0;
  1192. err_pm_disable:
  1193. pm_runtime_disable(chip->dev);
  1194. return ret;
  1195. }
  1196. static int dw_remove(struct platform_device *pdev)
  1197. {
  1198. struct axi_dma_chip *chip = platform_get_drvdata(pdev);
  1199. struct dw_axi_dma *dw = chip->dw;
  1200. struct axi_dma_chan *chan, *_chan;
  1201. u32 i;
  1202. /* Enable clk before accessing to registers */
  1203. clk_prepare_enable(chip->cfgr_clk);
  1204. clk_prepare_enable(chip->core_clk);
  1205. axi_dma_irq_disable(chip);
  1206. for (i = 0; i < dw->hdata->nr_channels; i++) {
  1207. axi_chan_disable(&chip->dw->chan[i]);
  1208. axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
  1209. }
  1210. axi_dma_disable(chip);
  1211. pm_runtime_disable(chip->dev);
  1212. axi_dma_suspend(chip);
  1213. devm_free_irq(chip->dev, chip->irq, chip);
  1214. of_dma_controller_free(chip->dev->of_node);
  1215. list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
  1216. vc.chan.device_node) {
  1217. list_del(&chan->vc.chan.device_node);
  1218. tasklet_kill(&chan->vc.task);
  1219. }
  1220. return 0;
  1221. }
  1222. static const struct dev_pm_ops dw_axi_dma_pm_ops = {
  1223. SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL)
  1224. };
  1225. static const struct of_device_id dw_dma_of_id_table[] = {
  1226. { .compatible = "snps,axi-dma-1.01a" },
  1227. { .compatible = "intel,kmb-axi-dma" },
  1228. {}
  1229. };
  1230. MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
  1231. static struct platform_driver dw_driver = {
  1232. .probe = dw_probe,
  1233. .remove = dw_remove,
  1234. .driver = {
  1235. .name = KBUILD_MODNAME,
  1236. .of_match_table = dw_dma_of_id_table,
  1237. .pm = &dw_axi_dma_pm_ops,
  1238. },
  1239. };
  1240. module_platform_driver(dw_driver);
  1241. MODULE_LICENSE("GPL v2");
  1242. MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver");
  1243. MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");