coh901318_lli.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * driver/dma/coh901318_lli.c
  4. *
  5. * Copyright (C) 2007-2009 ST-Ericsson
  6. * Support functions for handling lli for dma
  7. * Author: Per Friden <per.friden@stericsson.com>
  8. */
  9. #include <linux/spinlock.h>
  10. #include <linux/memory.h>
  11. #include <linux/gfp.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/dmaengine.h>
  14. #include "coh901318.h"
  15. #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
  16. #define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
  17. #define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
  18. #else
  19. #define DEBUGFS_POOL_COUNTER_RESET(pool)
  20. #define DEBUGFS_POOL_COUNTER_ADD(pool, add)
  21. #endif
  22. static struct coh901318_lli *
  23. coh901318_lli_next(struct coh901318_lli *data)
  24. {
  25. if (data == NULL || data->link_addr == 0)
  26. return NULL;
  27. return (struct coh901318_lli *) data->virt_link_addr;
  28. }
  29. int coh901318_pool_create(struct coh901318_pool *pool,
  30. struct device *dev,
  31. size_t size, size_t align)
  32. {
  33. spin_lock_init(&pool->lock);
  34. pool->dev = dev;
  35. pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
  36. DEBUGFS_POOL_COUNTER_RESET(pool);
  37. return 0;
  38. }
  39. int coh901318_pool_destroy(struct coh901318_pool *pool)
  40. {
  41. dma_pool_destroy(pool->dmapool);
  42. return 0;
  43. }
  44. struct coh901318_lli *
  45. coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
  46. {
  47. int i;
  48. struct coh901318_lli *head;
  49. struct coh901318_lli *lli;
  50. struct coh901318_lli *lli_prev;
  51. dma_addr_t phy;
  52. if (len == 0)
  53. return NULL;
  54. spin_lock(&pool->lock);
  55. head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
  56. if (head == NULL)
  57. goto err;
  58. DEBUGFS_POOL_COUNTER_ADD(pool, 1);
  59. lli = head;
  60. lli->phy_this = phy;
  61. lli->link_addr = 0x00000000;
  62. lli->virt_link_addr = NULL;
  63. for (i = 1; i < len; i++) {
  64. lli_prev = lli;
  65. lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
  66. if (lli == NULL)
  67. goto err_clean_up;
  68. DEBUGFS_POOL_COUNTER_ADD(pool, 1);
  69. lli->phy_this = phy;
  70. lli->link_addr = 0x00000000;
  71. lli->virt_link_addr = NULL;
  72. lli_prev->link_addr = phy;
  73. lli_prev->virt_link_addr = lli;
  74. }
  75. spin_unlock(&pool->lock);
  76. return head;
  77. err:
  78. spin_unlock(&pool->lock);
  79. return NULL;
  80. err_clean_up:
  81. lli_prev->link_addr = 0x00000000U;
  82. spin_unlock(&pool->lock);
  83. coh901318_lli_free(pool, &head);
  84. return NULL;
  85. }
  86. void coh901318_lli_free(struct coh901318_pool *pool,
  87. struct coh901318_lli **lli)
  88. {
  89. struct coh901318_lli *l;
  90. struct coh901318_lli *next;
  91. if (lli == NULL)
  92. return;
  93. l = *lli;
  94. if (l == NULL)
  95. return;
  96. spin_lock(&pool->lock);
  97. while (l->link_addr) {
  98. next = l->virt_link_addr;
  99. dma_pool_free(pool->dmapool, l, l->phy_this);
  100. DEBUGFS_POOL_COUNTER_ADD(pool, -1);
  101. l = next;
  102. }
  103. dma_pool_free(pool->dmapool, l, l->phy_this);
  104. DEBUGFS_POOL_COUNTER_ADD(pool, -1);
  105. spin_unlock(&pool->lock);
  106. *lli = NULL;
  107. }
  108. int
  109. coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
  110. struct coh901318_lli *lli,
  111. dma_addr_t source, unsigned int size,
  112. dma_addr_t destination, u32 ctrl_chained,
  113. u32 ctrl_eom)
  114. {
  115. int s = size;
  116. dma_addr_t src = source;
  117. dma_addr_t dst = destination;
  118. lli->src_addr = src;
  119. lli->dst_addr = dst;
  120. while (lli->link_addr) {
  121. lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
  122. lli->src_addr = src;
  123. lli->dst_addr = dst;
  124. s -= MAX_DMA_PACKET_SIZE;
  125. lli = coh901318_lli_next(lli);
  126. src += MAX_DMA_PACKET_SIZE;
  127. dst += MAX_DMA_PACKET_SIZE;
  128. }
  129. lli->control = ctrl_eom | s;
  130. lli->src_addr = src;
  131. lli->dst_addr = dst;
  132. return 0;
  133. }
  134. int
  135. coh901318_lli_fill_single(struct coh901318_pool *pool,
  136. struct coh901318_lli *lli,
  137. dma_addr_t buf, unsigned int size,
  138. dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
  139. enum dma_transfer_direction dir)
  140. {
  141. int s = size;
  142. dma_addr_t src;
  143. dma_addr_t dst;
  144. if (dir == DMA_MEM_TO_DEV) {
  145. src = buf;
  146. dst = dev_addr;
  147. } else if (dir == DMA_DEV_TO_MEM) {
  148. src = dev_addr;
  149. dst = buf;
  150. } else {
  151. return -EINVAL;
  152. }
  153. while (lli->link_addr) {
  154. size_t block_size = MAX_DMA_PACKET_SIZE;
  155. lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
  156. /* If we are on the next-to-final block and there will
  157. * be less than half a DMA packet left for the last
  158. * block, then we want to make this block a little
  159. * smaller to balance the sizes. This is meant to
  160. * avoid too small transfers if the buffer size is
  161. * (MAX_DMA_PACKET_SIZE*N + 1) */
  162. if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
  163. block_size = MAX_DMA_PACKET_SIZE/2;
  164. s -= block_size;
  165. lli->src_addr = src;
  166. lli->dst_addr = dst;
  167. lli = coh901318_lli_next(lli);
  168. if (dir == DMA_MEM_TO_DEV)
  169. src += block_size;
  170. else if (dir == DMA_DEV_TO_MEM)
  171. dst += block_size;
  172. }
  173. lli->control = ctrl_eom | s;
  174. lli->src_addr = src;
  175. lli->dst_addr = dst;
  176. return 0;
  177. }
  178. int
  179. coh901318_lli_fill_sg(struct coh901318_pool *pool,
  180. struct coh901318_lli *lli,
  181. struct scatterlist *sgl, unsigned int nents,
  182. dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
  183. u32 ctrl_last,
  184. enum dma_transfer_direction dir, u32 ctrl_irq_mask)
  185. {
  186. int i;
  187. struct scatterlist *sg;
  188. u32 ctrl_sg;
  189. dma_addr_t src = 0;
  190. dma_addr_t dst = 0;
  191. u32 bytes_to_transfer;
  192. u32 elem_size;
  193. if (lli == NULL)
  194. goto err;
  195. spin_lock(&pool->lock);
  196. if (dir == DMA_MEM_TO_DEV)
  197. dst = dev_addr;
  198. else if (dir == DMA_DEV_TO_MEM)
  199. src = dev_addr;
  200. else
  201. goto err;
  202. for_each_sg(sgl, sg, nents, i) {
  203. if (sg_is_chain(sg)) {
  204. /* sg continues to the next sg-element don't
  205. * send ctrl_finish until the last
  206. * sg-element in the chain
  207. */
  208. ctrl_sg = ctrl_chained;
  209. } else if (i == nents - 1)
  210. ctrl_sg = ctrl_last;
  211. else
  212. ctrl_sg = ctrl ? ctrl : ctrl_last;
  213. if (dir == DMA_MEM_TO_DEV)
  214. /* increment source address */
  215. src = sg_dma_address(sg);
  216. else
  217. /* increment destination address */
  218. dst = sg_dma_address(sg);
  219. bytes_to_transfer = sg_dma_len(sg);
  220. while (bytes_to_transfer) {
  221. u32 val;
  222. if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
  223. elem_size = MAX_DMA_PACKET_SIZE;
  224. val = ctrl_chained;
  225. } else {
  226. elem_size = bytes_to_transfer;
  227. val = ctrl_sg;
  228. }
  229. lli->control = val | elem_size;
  230. lli->src_addr = src;
  231. lli->dst_addr = dst;
  232. if (dir == DMA_DEV_TO_MEM)
  233. dst += elem_size;
  234. else
  235. src += elem_size;
  236. BUG_ON(lli->link_addr & 3);
  237. bytes_to_transfer -= elem_size;
  238. lli = coh901318_lli_next(lli);
  239. }
  240. }
  241. spin_unlock(&pool->lock);
  242. return 0;
  243. err:
  244. spin_unlock(&pool->lock);
  245. return -EINVAL;
  246. }