bcm2835-dma.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * BCM2835 DMA engine support
  4. *
  5. * Author: Florian Meier <florian.meier@koalo.de>
  6. * Copyright 2013
  7. *
  8. * Based on
  9. * OMAP DMAengine support by Russell King
  10. *
  11. * BCM2708 DMA Driver
  12. * Copyright (C) 2010 Broadcom
  13. *
  14. * Raspberry Pi PCM I2S ALSA Driver
  15. * Copyright (c) by Phil Poole 2013
  16. *
  17. * MARVELL MMP Peripheral DMA Driver
  18. * Copyright 2012 Marvell International Ltd.
  19. */
  20. #include <linux/dmaengine.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/dmapool.h>
  23. #include <linux/err.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/slab.h>
  30. #include <linux/io.h>
  31. #include <linux/spinlock.h>
  32. #include <linux/of.h>
  33. #include <linux/of_dma.h>
  34. #include "virt-dma.h"
  35. #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
  36. #define BCM2835_DMA_CHAN_NAME_SIZE 8
  37. /**
  38. * struct bcm2835_dmadev - BCM2835 DMA controller
  39. * @ddev: DMA device
  40. * @base: base address of register map
  41. * @zero_page: bus address of zero page (to detect transactions copying from
  42. * zero page and avoid accessing memory if so)
  43. */
  44. struct bcm2835_dmadev {
  45. struct dma_device ddev;
  46. void __iomem *base;
  47. dma_addr_t zero_page;
  48. };
  49. struct bcm2835_dma_cb {
  50. uint32_t info;
  51. uint32_t src;
  52. uint32_t dst;
  53. uint32_t length;
  54. uint32_t stride;
  55. uint32_t next;
  56. uint32_t pad[2];
  57. };
  58. struct bcm2835_cb_entry {
  59. struct bcm2835_dma_cb *cb;
  60. dma_addr_t paddr;
  61. };
  62. struct bcm2835_chan {
  63. struct virt_dma_chan vc;
  64. struct dma_slave_config cfg;
  65. unsigned int dreq;
  66. int ch;
  67. struct bcm2835_desc *desc;
  68. struct dma_pool *cb_pool;
  69. void __iomem *chan_base;
  70. int irq_number;
  71. unsigned int irq_flags;
  72. bool is_lite_channel;
  73. };
  74. struct bcm2835_desc {
  75. struct bcm2835_chan *c;
  76. struct virt_dma_desc vd;
  77. enum dma_transfer_direction dir;
  78. unsigned int frames;
  79. size_t size;
  80. bool cyclic;
  81. struct bcm2835_cb_entry cb_list[];
  82. };
  83. #define BCM2835_DMA_CS 0x00
  84. #define BCM2835_DMA_ADDR 0x04
  85. #define BCM2835_DMA_TI 0x08
  86. #define BCM2835_DMA_SOURCE_AD 0x0c
  87. #define BCM2835_DMA_DEST_AD 0x10
  88. #define BCM2835_DMA_LEN 0x14
  89. #define BCM2835_DMA_STRIDE 0x18
  90. #define BCM2835_DMA_NEXTCB 0x1c
  91. #define BCM2835_DMA_DEBUG 0x20
  92. /* DMA CS Control and Status bits */
  93. #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
  94. #define BCM2835_DMA_END BIT(1) /* current CB has ended */
  95. #define BCM2835_DMA_INT BIT(2) /* interrupt status */
  96. #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
  97. #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
  98. #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
  99. #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
  100. * AXI-write to ack
  101. */
  102. #define BCM2835_DMA_ERR BIT(8)
  103. #define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
  104. #define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
  105. /* current value of TI.BCM2835_DMA_WAIT_RESP */
  106. #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
  107. #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
  108. #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
  109. #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
  110. /* Transfer information bits - also bcm2835_cb.info field */
  111. #define BCM2835_DMA_INT_EN BIT(0)
  112. #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
  113. #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
  114. #define BCM2835_DMA_D_INC BIT(4)
  115. #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
  116. #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
  117. #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
  118. #define BCM2835_DMA_S_INC BIT(8)
  119. #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
  120. #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
  121. #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
  122. #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
  123. #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
  124. #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
  125. #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
  126. /* debug register bits */
  127. #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
  128. #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
  129. #define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
  130. #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
  131. #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
  132. #define BCM2835_DMA_DEBUG_ID_SHIFT 16
  133. #define BCM2835_DMA_DEBUG_ID_BITS 9
  134. #define BCM2835_DMA_DEBUG_STATE_SHIFT 16
  135. #define BCM2835_DMA_DEBUG_STATE_BITS 9
  136. #define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
  137. #define BCM2835_DMA_DEBUG_VERSION_BITS 3
  138. #define BCM2835_DMA_DEBUG_LITE BIT(28)
  139. /* shared registers for all dma channels */
  140. #define BCM2835_DMA_INT_STATUS 0xfe0
  141. #define BCM2835_DMA_ENABLE 0xff0
  142. #define BCM2835_DMA_DATA_TYPE_S8 1
  143. #define BCM2835_DMA_DATA_TYPE_S16 2
  144. #define BCM2835_DMA_DATA_TYPE_S32 4
  145. #define BCM2835_DMA_DATA_TYPE_S128 16
  146. /* Valid only for channels 0 - 14, 15 has its own base address */
  147. #define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
  148. #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
  149. /* the max dma length for different channels */
  150. #define MAX_DMA_LEN SZ_1G
  151. #define MAX_LITE_DMA_LEN (SZ_64K - 4)
  152. static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
  153. {
  154. /* lite and normal channels have different max frame length */
  155. return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
  156. }
  157. /* how many frames of max_len size do we need to transfer len bytes */
  158. static inline size_t bcm2835_dma_frames_for_length(size_t len,
  159. size_t max_len)
  160. {
  161. return DIV_ROUND_UP(len, max_len);
  162. }
  163. static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
  164. {
  165. return container_of(d, struct bcm2835_dmadev, ddev);
  166. }
  167. static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
  168. {
  169. return container_of(c, struct bcm2835_chan, vc.chan);
  170. }
  171. static inline struct bcm2835_desc *to_bcm2835_dma_desc(
  172. struct dma_async_tx_descriptor *t)
  173. {
  174. return container_of(t, struct bcm2835_desc, vd.tx);
  175. }
  176. static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
  177. {
  178. size_t i;
  179. for (i = 0; i < desc->frames; i++)
  180. dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
  181. desc->cb_list[i].paddr);
  182. kfree(desc);
  183. }
  184. static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
  185. {
  186. bcm2835_dma_free_cb_chain(
  187. container_of(vd, struct bcm2835_desc, vd));
  188. }
  189. static void bcm2835_dma_create_cb_set_length(
  190. struct bcm2835_chan *chan,
  191. struct bcm2835_dma_cb *control_block,
  192. size_t len,
  193. size_t period_len,
  194. size_t *total_len,
  195. u32 finalextrainfo)
  196. {
  197. size_t max_len = bcm2835_dma_max_frame_length(chan);
  198. /* set the length taking lite-channel limitations into account */
  199. control_block->length = min_t(u32, len, max_len);
  200. /* finished if we have no period_length */
  201. if (!period_len)
  202. return;
  203. /*
  204. * period_len means: that we need to generate
  205. * transfers that are terminating at every
  206. * multiple of period_len - this is typically
  207. * used to set the interrupt flag in info
  208. * which is required during cyclic transfers
  209. */
  210. /* have we filled in period_length yet? */
  211. if (*total_len + control_block->length < period_len) {
  212. /* update number of bytes in this period so far */
  213. *total_len += control_block->length;
  214. return;
  215. }
  216. /* calculate the length that remains to reach period_length */
  217. control_block->length = period_len - *total_len;
  218. /* reset total_length for next period */
  219. *total_len = 0;
  220. /* add extrainfo bits in info */
  221. control_block->info |= finalextrainfo;
  222. }
  223. static inline size_t bcm2835_dma_count_frames_for_sg(
  224. struct bcm2835_chan *c,
  225. struct scatterlist *sgl,
  226. unsigned int sg_len)
  227. {
  228. size_t frames = 0;
  229. struct scatterlist *sgent;
  230. unsigned int i;
  231. size_t plength = bcm2835_dma_max_frame_length(c);
  232. for_each_sg(sgl, sgent, sg_len, i)
  233. frames += bcm2835_dma_frames_for_length(
  234. sg_dma_len(sgent), plength);
  235. return frames;
  236. }
  237. /**
  238. * bcm2835_dma_create_cb_chain - create a control block and fills data in
  239. *
  240. * @chan: the @dma_chan for which we run this
  241. * @direction: the direction in which we transfer
  242. * @cyclic: it is a cyclic transfer
  243. * @info: the default info bits to apply per controlblock
  244. * @frames: number of controlblocks to allocate
  245. * @src: the src address to assign (if the S_INC bit is set
  246. * in @info, then it gets incremented)
  247. * @dst: the dst address to assign (if the D_INC bit is set
  248. * in @info, then it gets incremented)
  249. * @buf_len: the full buffer length (may also be 0)
  250. * @period_len: the period length when to apply @finalextrainfo
  251. * in addition to the last transfer
  252. * this will also break some control-blocks early
  253. * @finalextrainfo: additional bits in last controlblock
  254. * (or when period_len is reached in case of cyclic)
  255. * @gfp: the GFP flag to use for allocation
  256. */
  257. static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
  258. struct dma_chan *chan, enum dma_transfer_direction direction,
  259. bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
  260. dma_addr_t src, dma_addr_t dst, size_t buf_len,
  261. size_t period_len, gfp_t gfp)
  262. {
  263. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  264. size_t len = buf_len, total_len;
  265. size_t frame;
  266. struct bcm2835_desc *d;
  267. struct bcm2835_cb_entry *cb_entry;
  268. struct bcm2835_dma_cb *control_block;
  269. if (!frames)
  270. return NULL;
  271. /* allocate and setup the descriptor. */
  272. d = kzalloc(struct_size(d, cb_list, frames), gfp);
  273. if (!d)
  274. return NULL;
  275. d->c = c;
  276. d->dir = direction;
  277. d->cyclic = cyclic;
  278. /*
  279. * Iterate over all frames, create a control block
  280. * for each frame and link them together.
  281. */
  282. for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
  283. cb_entry = &d->cb_list[frame];
  284. cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
  285. &cb_entry->paddr);
  286. if (!cb_entry->cb)
  287. goto error_cb;
  288. /* fill in the control block */
  289. control_block = cb_entry->cb;
  290. control_block->info = info;
  291. control_block->src = src;
  292. control_block->dst = dst;
  293. control_block->stride = 0;
  294. control_block->next = 0;
  295. /* set up length in control_block if requested */
  296. if (buf_len) {
  297. /* calculate length honoring period_length */
  298. bcm2835_dma_create_cb_set_length(
  299. c, control_block,
  300. len, period_len, &total_len,
  301. cyclic ? finalextrainfo : 0);
  302. /* calculate new remaining length */
  303. len -= control_block->length;
  304. }
  305. /* link this the last controlblock */
  306. if (frame)
  307. d->cb_list[frame - 1].cb->next = cb_entry->paddr;
  308. /* update src and dst and length */
  309. if (src && (info & BCM2835_DMA_S_INC))
  310. src += control_block->length;
  311. if (dst && (info & BCM2835_DMA_D_INC))
  312. dst += control_block->length;
  313. /* Length of total transfer */
  314. d->size += control_block->length;
  315. }
  316. /* the last frame requires extra flags */
  317. d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
  318. /* detect a size missmatch */
  319. if (buf_len && (d->size != buf_len))
  320. goto error_cb;
  321. return d;
  322. error_cb:
  323. bcm2835_dma_free_cb_chain(d);
  324. return NULL;
  325. }
  326. static void bcm2835_dma_fill_cb_chain_with_sg(
  327. struct dma_chan *chan,
  328. enum dma_transfer_direction direction,
  329. struct bcm2835_cb_entry *cb,
  330. struct scatterlist *sgl,
  331. unsigned int sg_len)
  332. {
  333. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  334. size_t len, max_len;
  335. unsigned int i;
  336. dma_addr_t addr;
  337. struct scatterlist *sgent;
  338. max_len = bcm2835_dma_max_frame_length(c);
  339. for_each_sg(sgl, sgent, sg_len, i) {
  340. for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
  341. len > 0;
  342. addr += cb->cb->length, len -= cb->cb->length, cb++) {
  343. if (direction == DMA_DEV_TO_MEM)
  344. cb->cb->dst = addr;
  345. else
  346. cb->cb->src = addr;
  347. cb->cb->length = min(len, max_len);
  348. }
  349. }
  350. }
  351. static void bcm2835_dma_abort(struct bcm2835_chan *c)
  352. {
  353. void __iomem *chan_base = c->chan_base;
  354. long int timeout = 10000;
  355. /*
  356. * A zero control block address means the channel is idle.
  357. * (The ACTIVE flag in the CS register is not a reliable indicator.)
  358. */
  359. if (!readl(chan_base + BCM2835_DMA_ADDR))
  360. return;
  361. /* Write 0 to the active bit - Pause the DMA */
  362. writel(0, chan_base + BCM2835_DMA_CS);
  363. /* Wait for any current AXI transfer to complete */
  364. while ((readl(chan_base + BCM2835_DMA_CS) &
  365. BCM2835_DMA_WAITING_FOR_WRITES) && --timeout)
  366. cpu_relax();
  367. /* Peripheral might be stuck and fail to signal AXI write responses */
  368. if (!timeout)
  369. dev_err(c->vc.chan.device->dev,
  370. "failed to complete outstanding writes\n");
  371. writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
  372. }
  373. static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
  374. {
  375. struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
  376. struct bcm2835_desc *d;
  377. if (!vd) {
  378. c->desc = NULL;
  379. return;
  380. }
  381. list_del(&vd->node);
  382. c->desc = d = to_bcm2835_dma_desc(&vd->tx);
  383. writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
  384. writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
  385. }
  386. static irqreturn_t bcm2835_dma_callback(int irq, void *data)
  387. {
  388. struct bcm2835_chan *c = data;
  389. struct bcm2835_desc *d;
  390. unsigned long flags;
  391. /* check the shared interrupt */
  392. if (c->irq_flags & IRQF_SHARED) {
  393. /* check if the interrupt is enabled */
  394. flags = readl(c->chan_base + BCM2835_DMA_CS);
  395. /* if not set then we are not the reason for the irq */
  396. if (!(flags & BCM2835_DMA_INT))
  397. return IRQ_NONE;
  398. }
  399. spin_lock_irqsave(&c->vc.lock, flags);
  400. /*
  401. * Clear the INT flag to receive further interrupts. Keep the channel
  402. * active in case the descriptor is cyclic or in case the client has
  403. * already terminated the descriptor and issued a new one. (May happen
  404. * if this IRQ handler is threaded.) If the channel is finished, it
  405. * will remain idle despite the ACTIVE flag being set.
  406. */
  407. writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,
  408. c->chan_base + BCM2835_DMA_CS);
  409. d = c->desc;
  410. if (d) {
  411. if (d->cyclic) {
  412. /* call the cyclic callback */
  413. vchan_cyclic_callback(&d->vd);
  414. } else if (!readl(c->chan_base + BCM2835_DMA_ADDR)) {
  415. vchan_cookie_complete(&c->desc->vd);
  416. bcm2835_dma_start_desc(c);
  417. }
  418. }
  419. spin_unlock_irqrestore(&c->vc.lock, flags);
  420. return IRQ_HANDLED;
  421. }
  422. static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
  423. {
  424. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  425. struct device *dev = c->vc.chan.device->dev;
  426. dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
  427. /*
  428. * Control blocks are 256 bit in length and must start at a 256 bit
  429. * (32 byte) aligned address (BCM2835 ARM Peripherals, sec. 4.2.1.1).
  430. */
  431. c->cb_pool = dma_pool_create(dev_name(dev), dev,
  432. sizeof(struct bcm2835_dma_cb), 32, 0);
  433. if (!c->cb_pool) {
  434. dev_err(dev, "unable to allocate descriptor pool\n");
  435. return -ENOMEM;
  436. }
  437. return request_irq(c->irq_number, bcm2835_dma_callback,
  438. c->irq_flags, "DMA IRQ", c);
  439. }
  440. static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
  441. {
  442. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  443. vchan_free_chan_resources(&c->vc);
  444. free_irq(c->irq_number, c);
  445. dma_pool_destroy(c->cb_pool);
  446. dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
  447. }
  448. static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
  449. {
  450. return d->size;
  451. }
  452. static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
  453. {
  454. unsigned int i;
  455. size_t size;
  456. for (size = i = 0; i < d->frames; i++) {
  457. struct bcm2835_dma_cb *control_block = d->cb_list[i].cb;
  458. size_t this_size = control_block->length;
  459. dma_addr_t dma;
  460. if (d->dir == DMA_DEV_TO_MEM)
  461. dma = control_block->dst;
  462. else
  463. dma = control_block->src;
  464. if (size)
  465. size += this_size;
  466. else if (addr >= dma && addr < dma + this_size)
  467. size += dma + this_size - addr;
  468. }
  469. return size;
  470. }
  471. static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
  472. dma_cookie_t cookie, struct dma_tx_state *txstate)
  473. {
  474. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  475. struct virt_dma_desc *vd;
  476. enum dma_status ret;
  477. unsigned long flags;
  478. ret = dma_cookie_status(chan, cookie, txstate);
  479. if (ret == DMA_COMPLETE || !txstate)
  480. return ret;
  481. spin_lock_irqsave(&c->vc.lock, flags);
  482. vd = vchan_find_desc(&c->vc, cookie);
  483. if (vd) {
  484. txstate->residue =
  485. bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
  486. } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
  487. struct bcm2835_desc *d = c->desc;
  488. dma_addr_t pos;
  489. if (d->dir == DMA_MEM_TO_DEV)
  490. pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
  491. else if (d->dir == DMA_DEV_TO_MEM)
  492. pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
  493. else
  494. pos = 0;
  495. txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
  496. } else {
  497. txstate->residue = 0;
  498. }
  499. spin_unlock_irqrestore(&c->vc.lock, flags);
  500. return ret;
  501. }
  502. static void bcm2835_dma_issue_pending(struct dma_chan *chan)
  503. {
  504. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  505. unsigned long flags;
  506. spin_lock_irqsave(&c->vc.lock, flags);
  507. if (vchan_issue_pending(&c->vc) && !c->desc)
  508. bcm2835_dma_start_desc(c);
  509. spin_unlock_irqrestore(&c->vc.lock, flags);
  510. }
  511. static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
  512. struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
  513. size_t len, unsigned long flags)
  514. {
  515. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  516. struct bcm2835_desc *d;
  517. u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
  518. u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
  519. size_t max_len = bcm2835_dma_max_frame_length(c);
  520. size_t frames;
  521. /* if src, dst or len is not given return with an error */
  522. if (!src || !dst || !len)
  523. return NULL;
  524. /* calculate number of frames */
  525. frames = bcm2835_dma_frames_for_length(len, max_len);
  526. /* allocate the CB chain - this also fills in the pointers */
  527. d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
  528. info, extra, frames,
  529. src, dst, len, 0, GFP_KERNEL);
  530. if (!d)
  531. return NULL;
  532. return vchan_tx_prep(&c->vc, &d->vd, flags);
  533. }
  534. static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
  535. struct dma_chan *chan,
  536. struct scatterlist *sgl, unsigned int sg_len,
  537. enum dma_transfer_direction direction,
  538. unsigned long flags, void *context)
  539. {
  540. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  541. struct bcm2835_desc *d;
  542. dma_addr_t src = 0, dst = 0;
  543. u32 info = BCM2835_DMA_WAIT_RESP;
  544. u32 extra = BCM2835_DMA_INT_EN;
  545. size_t frames;
  546. if (!is_slave_direction(direction)) {
  547. dev_err(chan->device->dev,
  548. "%s: bad direction?\n", __func__);
  549. return NULL;
  550. }
  551. if (c->dreq != 0)
  552. info |= BCM2835_DMA_PER_MAP(c->dreq);
  553. if (direction == DMA_DEV_TO_MEM) {
  554. if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
  555. return NULL;
  556. src = c->cfg.src_addr;
  557. info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
  558. } else {
  559. if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
  560. return NULL;
  561. dst = c->cfg.dst_addr;
  562. info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
  563. }
  564. /* count frames in sg list */
  565. frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
  566. /* allocate the CB chain */
  567. d = bcm2835_dma_create_cb_chain(chan, direction, false,
  568. info, extra,
  569. frames, src, dst, 0, 0,
  570. GFP_NOWAIT);
  571. if (!d)
  572. return NULL;
  573. /* fill in frames with scatterlist pointers */
  574. bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
  575. sgl, sg_len);
  576. return vchan_tx_prep(&c->vc, &d->vd, flags);
  577. }
  578. static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
  579. struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  580. size_t period_len, enum dma_transfer_direction direction,
  581. unsigned long flags)
  582. {
  583. struct bcm2835_dmadev *od = to_bcm2835_dma_dev(chan->device);
  584. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  585. struct bcm2835_desc *d;
  586. dma_addr_t src, dst;
  587. u32 info = BCM2835_DMA_WAIT_RESP;
  588. u32 extra = 0;
  589. size_t max_len = bcm2835_dma_max_frame_length(c);
  590. size_t frames;
  591. /* Grab configuration */
  592. if (!is_slave_direction(direction)) {
  593. dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
  594. return NULL;
  595. }
  596. if (!buf_len) {
  597. dev_err(chan->device->dev,
  598. "%s: bad buffer length (= 0)\n", __func__);
  599. return NULL;
  600. }
  601. if (flags & DMA_PREP_INTERRUPT)
  602. extra |= BCM2835_DMA_INT_EN;
  603. else
  604. period_len = buf_len;
  605. /*
  606. * warn if buf_len is not a multiple of period_len - this may leed
  607. * to unexpected latencies for interrupts and thus audiable clicks
  608. */
  609. if (buf_len % period_len)
  610. dev_warn_once(chan->device->dev,
  611. "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
  612. __func__, buf_len, period_len);
  613. /* Setup DREQ channel */
  614. if (c->dreq != 0)
  615. info |= BCM2835_DMA_PER_MAP(c->dreq);
  616. if (direction == DMA_DEV_TO_MEM) {
  617. if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
  618. return NULL;
  619. src = c->cfg.src_addr;
  620. dst = buf_addr;
  621. info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
  622. } else {
  623. if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
  624. return NULL;
  625. dst = c->cfg.dst_addr;
  626. src = buf_addr;
  627. info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
  628. /* non-lite channels can write zeroes w/o accessing memory */
  629. if (buf_addr == od->zero_page && !c->is_lite_channel)
  630. info |= BCM2835_DMA_S_IGNORE;
  631. }
  632. /* calculate number of frames */
  633. frames = /* number of periods */
  634. DIV_ROUND_UP(buf_len, period_len) *
  635. /* number of frames per period */
  636. bcm2835_dma_frames_for_length(period_len, max_len);
  637. /*
  638. * allocate the CB chain
  639. * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
  640. * implementation calls prep_dma_cyclic with interrupts disabled.
  641. */
  642. d = bcm2835_dma_create_cb_chain(chan, direction, true,
  643. info, extra,
  644. frames, src, dst, buf_len,
  645. period_len, GFP_NOWAIT);
  646. if (!d)
  647. return NULL;
  648. /* wrap around into a loop */
  649. d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
  650. return vchan_tx_prep(&c->vc, &d->vd, flags);
  651. }
  652. static int bcm2835_dma_slave_config(struct dma_chan *chan,
  653. struct dma_slave_config *cfg)
  654. {
  655. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  656. c->cfg = *cfg;
  657. return 0;
  658. }
  659. static int bcm2835_dma_terminate_all(struct dma_chan *chan)
  660. {
  661. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  662. unsigned long flags;
  663. LIST_HEAD(head);
  664. spin_lock_irqsave(&c->vc.lock, flags);
  665. /* stop DMA activity */
  666. if (c->desc) {
  667. vchan_terminate_vdesc(&c->desc->vd);
  668. c->desc = NULL;
  669. bcm2835_dma_abort(c);
  670. }
  671. vchan_get_all_descriptors(&c->vc, &head);
  672. spin_unlock_irqrestore(&c->vc.lock, flags);
  673. vchan_dma_desc_free_list(&c->vc, &head);
  674. return 0;
  675. }
  676. static void bcm2835_dma_synchronize(struct dma_chan *chan)
  677. {
  678. struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  679. vchan_synchronize(&c->vc);
  680. }
  681. static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
  682. int irq, unsigned int irq_flags)
  683. {
  684. struct bcm2835_chan *c;
  685. c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
  686. if (!c)
  687. return -ENOMEM;
  688. c->vc.desc_free = bcm2835_dma_desc_free;
  689. vchan_init(&c->vc, &d->ddev);
  690. c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
  691. c->ch = chan_id;
  692. c->irq_number = irq;
  693. c->irq_flags = irq_flags;
  694. /* check in DEBUG register if this is a LITE channel */
  695. if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
  696. BCM2835_DMA_DEBUG_LITE)
  697. c->is_lite_channel = true;
  698. return 0;
  699. }
  700. static void bcm2835_dma_free(struct bcm2835_dmadev *od)
  701. {
  702. struct bcm2835_chan *c, *next;
  703. list_for_each_entry_safe(c, next, &od->ddev.channels,
  704. vc.chan.device_node) {
  705. list_del(&c->vc.chan.device_node);
  706. tasklet_kill(&c->vc.task);
  707. }
  708. dma_unmap_page_attrs(od->ddev.dev, od->zero_page, PAGE_SIZE,
  709. DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
  710. }
  711. static const struct of_device_id bcm2835_dma_of_match[] = {
  712. { .compatible = "brcm,bcm2835-dma", },
  713. {},
  714. };
  715. MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
  716. static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
  717. struct of_dma *ofdma)
  718. {
  719. struct bcm2835_dmadev *d = ofdma->of_dma_data;
  720. struct dma_chan *chan;
  721. chan = dma_get_any_slave_channel(&d->ddev);
  722. if (!chan)
  723. return NULL;
  724. /* Set DREQ from param */
  725. to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
  726. return chan;
  727. }
  728. static int bcm2835_dma_probe(struct platform_device *pdev)
  729. {
  730. struct bcm2835_dmadev *od;
  731. struct resource *res;
  732. void __iomem *base;
  733. int rc;
  734. int i, j;
  735. int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1];
  736. int irq_flags;
  737. uint32_t chans_available;
  738. char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
  739. if (!pdev->dev.dma_mask)
  740. pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
  741. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  742. if (rc) {
  743. dev_err(&pdev->dev, "Unable to set DMA mask\n");
  744. return rc;
  745. }
  746. od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
  747. if (!od)
  748. return -ENOMEM;
  749. dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
  750. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  751. base = devm_ioremap_resource(&pdev->dev, res);
  752. if (IS_ERR(base))
  753. return PTR_ERR(base);
  754. od->base = base;
  755. dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
  756. dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
  757. dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
  758. dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
  759. od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
  760. od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
  761. od->ddev.device_tx_status = bcm2835_dma_tx_status;
  762. od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
  763. od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
  764. od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
  765. od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
  766. od->ddev.device_config = bcm2835_dma_slave_config;
  767. od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
  768. od->ddev.device_synchronize = bcm2835_dma_synchronize;
  769. od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  770. od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
  771. od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
  772. BIT(DMA_MEM_TO_MEM);
  773. od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  774. od->ddev.descriptor_reuse = true;
  775. od->ddev.dev = &pdev->dev;
  776. INIT_LIST_HEAD(&od->ddev.channels);
  777. platform_set_drvdata(pdev, od);
  778. od->zero_page = dma_map_page_attrs(od->ddev.dev, ZERO_PAGE(0), 0,
  779. PAGE_SIZE, DMA_TO_DEVICE,
  780. DMA_ATTR_SKIP_CPU_SYNC);
  781. if (dma_mapping_error(od->ddev.dev, od->zero_page)) {
  782. dev_err(&pdev->dev, "Failed to map zero page\n");
  783. return -ENOMEM;
  784. }
  785. /* Request DMA channel mask from device tree */
  786. if (of_property_read_u32(pdev->dev.of_node,
  787. "brcm,dma-channel-mask",
  788. &chans_available)) {
  789. dev_err(&pdev->dev, "Failed to get channel mask\n");
  790. rc = -EINVAL;
  791. goto err_no_dma;
  792. }
  793. /* get irqs for each channel that we support */
  794. for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
  795. /* skip masked out channels */
  796. if (!(chans_available & (1 << i))) {
  797. irq[i] = -1;
  798. continue;
  799. }
  800. /* get the named irq */
  801. snprintf(chan_name, sizeof(chan_name), "dma%i", i);
  802. irq[i] = platform_get_irq_byname(pdev, chan_name);
  803. if (irq[i] >= 0)
  804. continue;
  805. /* legacy device tree case handling */
  806. dev_warn_once(&pdev->dev,
  807. "missing interrupt-names property in device tree - legacy interpretation is used\n");
  808. /*
  809. * in case of channel >= 11
  810. * use the 11th interrupt and that is shared
  811. */
  812. irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
  813. }
  814. /* get irqs for each channel */
  815. for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
  816. /* skip channels without irq */
  817. if (irq[i] < 0)
  818. continue;
  819. /* check if there are other channels that also use this irq */
  820. irq_flags = 0;
  821. for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
  822. if ((i != j) && (irq[j] == irq[i])) {
  823. irq_flags = IRQF_SHARED;
  824. break;
  825. }
  826. /* initialize the channel */
  827. rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
  828. if (rc)
  829. goto err_no_dma;
  830. }
  831. dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
  832. /* Device-tree DMA controller registration */
  833. rc = of_dma_controller_register(pdev->dev.of_node,
  834. bcm2835_dma_xlate, od);
  835. if (rc) {
  836. dev_err(&pdev->dev, "Failed to register DMA controller\n");
  837. goto err_no_dma;
  838. }
  839. rc = dma_async_device_register(&od->ddev);
  840. if (rc) {
  841. dev_err(&pdev->dev,
  842. "Failed to register slave DMA engine device: %d\n", rc);
  843. goto err_no_dma;
  844. }
  845. dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
  846. return 0;
  847. err_no_dma:
  848. bcm2835_dma_free(od);
  849. return rc;
  850. }
  851. static int bcm2835_dma_remove(struct platform_device *pdev)
  852. {
  853. struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
  854. dma_async_device_unregister(&od->ddev);
  855. bcm2835_dma_free(od);
  856. return 0;
  857. }
  858. static struct platform_driver bcm2835_dma_driver = {
  859. .probe = bcm2835_dma_probe,
  860. .remove = bcm2835_dma_remove,
  861. .driver = {
  862. .name = "bcm2835-dma",
  863. .of_match_table = of_match_ptr(bcm2835_dma_of_match),
  864. },
  865. };
  866. module_platform_driver(bcm2835_dma_driver);
  867. MODULE_ALIAS("platform:bcm2835-dma");
  868. MODULE_DESCRIPTION("BCM2835 DMA engine driver");
  869. MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
  870. MODULE_LICENSE("GPL");