at_hdmac.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
  4. *
  5. * Copyright (C) 2008 Atmel Corporation
  6. *
  7. * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
  8. * The only Atmel DMA Controller that is not covered by this driver is the one
  9. * found on AT91SAM9263.
  10. */
  11. #include <dt-bindings/dma/at91.h>
  12. #include <linux/clk.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmapool.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of_dma.h>
  23. #include "at_hdmac_regs.h"
  24. #include "dmaengine.h"
  25. /*
  26. * Glossary
  27. * --------
  28. *
  29. * at_hdmac : Name of the ATmel AHB DMA Controller
  30. * at_dma_ / atdma : ATmel DMA controller entity related
  31. * atc_ / atchan : ATmel DMA Channel entity related
  32. */
  33. #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
  34. #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
  35. |ATC_DIF(AT_DMA_MEM_IF))
  36. #define ATC_DMA_BUSWIDTHS\
  37. (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
  38. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
  39. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
  40. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
  41. #define ATC_MAX_DSCR_TRIALS 10
  42. /*
  43. * Initial number of descriptors to allocate for each channel. This could
  44. * be increased during dma usage.
  45. */
  46. static unsigned int init_nr_desc_per_channel = 64;
  47. module_param(init_nr_desc_per_channel, uint, 0644);
  48. MODULE_PARM_DESC(init_nr_desc_per_channel,
  49. "initial descriptors per channel (default: 64)");
  50. /* prototypes */
  51. static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
  52. static void atc_issue_pending(struct dma_chan *chan);
  53. /*----------------------------------------------------------------------*/
  54. static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
  55. size_t len)
  56. {
  57. unsigned int width;
  58. if (!((src | dst | len) & 3))
  59. width = 2;
  60. else if (!((src | dst | len) & 1))
  61. width = 1;
  62. else
  63. width = 0;
  64. return width;
  65. }
  66. static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
  67. {
  68. return list_first_entry(&atchan->active_list,
  69. struct at_desc, desc_node);
  70. }
  71. static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
  72. {
  73. return list_first_entry(&atchan->queue,
  74. struct at_desc, desc_node);
  75. }
  76. /**
  77. * atc_alloc_descriptor - allocate and return an initialized descriptor
  78. * @chan: the channel to allocate descriptors for
  79. * @gfp_flags: GFP allocation flags
  80. *
  81. * Note: The ack-bit is positioned in the descriptor flag at creation time
  82. * to make initial allocation more convenient. This bit will be cleared
  83. * and control will be given to client at usage time (during
  84. * preparation functions).
  85. */
  86. static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
  87. gfp_t gfp_flags)
  88. {
  89. struct at_desc *desc = NULL;
  90. struct at_dma *atdma = to_at_dma(chan->device);
  91. dma_addr_t phys;
  92. desc = dma_pool_zalloc(atdma->dma_desc_pool, gfp_flags, &phys);
  93. if (desc) {
  94. INIT_LIST_HEAD(&desc->tx_list);
  95. dma_async_tx_descriptor_init(&desc->txd, chan);
  96. /* txd.flags will be overwritten in prep functions */
  97. desc->txd.flags = DMA_CTRL_ACK;
  98. desc->txd.tx_submit = atc_tx_submit;
  99. desc->txd.phys = phys;
  100. }
  101. return desc;
  102. }
  103. /**
  104. * atc_desc_get - get an unused descriptor from free_list
  105. * @atchan: channel we want a new descriptor for
  106. */
  107. static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
  108. {
  109. struct at_desc *desc, *_desc;
  110. struct at_desc *ret = NULL;
  111. unsigned long flags;
  112. unsigned int i = 0;
  113. spin_lock_irqsave(&atchan->lock, flags);
  114. list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
  115. i++;
  116. if (async_tx_test_ack(&desc->txd)) {
  117. list_del(&desc->desc_node);
  118. ret = desc;
  119. break;
  120. }
  121. dev_dbg(chan2dev(&atchan->chan_common),
  122. "desc %p not ACKed\n", desc);
  123. }
  124. spin_unlock_irqrestore(&atchan->lock, flags);
  125. dev_vdbg(chan2dev(&atchan->chan_common),
  126. "scanned %u descriptors on freelist\n", i);
  127. /* no more descriptor available in initial pool: create one more */
  128. if (!ret)
  129. ret = atc_alloc_descriptor(&atchan->chan_common, GFP_NOWAIT);
  130. return ret;
  131. }
  132. /**
  133. * atc_desc_put - move a descriptor, including any children, to the free list
  134. * @atchan: channel we work on
  135. * @desc: descriptor, at the head of a chain, to move to free list
  136. */
  137. static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
  138. {
  139. if (desc) {
  140. struct at_desc *child;
  141. unsigned long flags;
  142. spin_lock_irqsave(&atchan->lock, flags);
  143. list_for_each_entry(child, &desc->tx_list, desc_node)
  144. dev_vdbg(chan2dev(&atchan->chan_common),
  145. "moving child desc %p to freelist\n",
  146. child);
  147. list_splice_init(&desc->tx_list, &atchan->free_list);
  148. dev_vdbg(chan2dev(&atchan->chan_common),
  149. "moving desc %p to freelist\n", desc);
  150. list_add(&desc->desc_node, &atchan->free_list);
  151. spin_unlock_irqrestore(&atchan->lock, flags);
  152. }
  153. }
  154. /**
  155. * atc_desc_chain - build chain adding a descriptor
  156. * @first: address of first descriptor of the chain
  157. * @prev: address of previous descriptor of the chain
  158. * @desc: descriptor to queue
  159. *
  160. * Called from prep_* functions
  161. */
  162. static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
  163. struct at_desc *desc)
  164. {
  165. if (!(*first)) {
  166. *first = desc;
  167. } else {
  168. /* inform the HW lli about chaining */
  169. (*prev)->lli.dscr = desc->txd.phys;
  170. /* insert the link descriptor to the LD ring */
  171. list_add_tail(&desc->desc_node,
  172. &(*first)->tx_list);
  173. }
  174. *prev = desc;
  175. }
  176. /**
  177. * atc_dostart - starts the DMA engine for real
  178. * @atchan: the channel we want to start
  179. * @first: first descriptor in the list we want to begin with
  180. *
  181. * Called with atchan->lock held and bh disabled
  182. */
  183. static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
  184. {
  185. struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
  186. /* ASSERT: channel is idle */
  187. if (atc_chan_is_enabled(atchan)) {
  188. dev_err(chan2dev(&atchan->chan_common),
  189. "BUG: Attempted to start non-idle channel\n");
  190. dev_err(chan2dev(&atchan->chan_common),
  191. " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
  192. channel_readl(atchan, SADDR),
  193. channel_readl(atchan, DADDR),
  194. channel_readl(atchan, CTRLA),
  195. channel_readl(atchan, CTRLB),
  196. channel_readl(atchan, DSCR));
  197. /* The tasklet will hopefully advance the queue... */
  198. return;
  199. }
  200. vdbg_dump_regs(atchan);
  201. channel_writel(atchan, SADDR, 0);
  202. channel_writel(atchan, DADDR, 0);
  203. channel_writel(atchan, CTRLA, 0);
  204. channel_writel(atchan, CTRLB, 0);
  205. channel_writel(atchan, DSCR, first->txd.phys);
  206. channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) |
  207. ATC_SPIP_BOUNDARY(first->boundary));
  208. channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
  209. ATC_DPIP_BOUNDARY(first->boundary));
  210. dma_writel(atdma, CHER, atchan->mask);
  211. vdbg_dump_regs(atchan);
  212. }
  213. /*
  214. * atc_get_desc_by_cookie - get the descriptor of a cookie
  215. * @atchan: the DMA channel
  216. * @cookie: the cookie to get the descriptor for
  217. */
  218. static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan,
  219. dma_cookie_t cookie)
  220. {
  221. struct at_desc *desc, *_desc;
  222. list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) {
  223. if (desc->txd.cookie == cookie)
  224. return desc;
  225. }
  226. list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
  227. if (desc->txd.cookie == cookie)
  228. return desc;
  229. }
  230. return NULL;
  231. }
  232. /**
  233. * atc_calc_bytes_left - calculates the number of bytes left according to the
  234. * value read from CTRLA.
  235. *
  236. * @current_len: the number of bytes left before reading CTRLA
  237. * @ctrla: the value of CTRLA
  238. */
  239. static inline int atc_calc_bytes_left(int current_len, u32 ctrla)
  240. {
  241. u32 btsize = (ctrla & ATC_BTSIZE_MAX);
  242. u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla);
  243. /*
  244. * According to the datasheet, when reading the Control A Register
  245. * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
  246. * number of transfers completed on the Source Interface.
  247. * So btsize is always a number of source width transfers.
  248. */
  249. return current_len - (btsize << src_width);
  250. }
  251. /**
  252. * atc_get_bytes_left - get the number of bytes residue for a cookie
  253. * @chan: DMA channel
  254. * @cookie: transaction identifier to check status of
  255. */
  256. static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
  257. {
  258. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  259. struct at_desc *desc_first = atc_first_active(atchan);
  260. struct at_desc *desc;
  261. int ret;
  262. u32 ctrla, dscr, trials;
  263. /*
  264. * If the cookie doesn't match to the currently running transfer then
  265. * we can return the total length of the associated DMA transfer,
  266. * because it is still queued.
  267. */
  268. desc = atc_get_desc_by_cookie(atchan, cookie);
  269. if (desc == NULL)
  270. return -EINVAL;
  271. else if (desc != desc_first)
  272. return desc->total_len;
  273. /* cookie matches to the currently running transfer */
  274. ret = desc_first->total_len;
  275. if (desc_first->lli.dscr) {
  276. /* hardware linked list transfer */
  277. /*
  278. * Calculate the residue by removing the length of the child
  279. * descriptors already transferred from the total length.
  280. * To get the current child descriptor we can use the value of
  281. * the channel's DSCR register and compare it against the value
  282. * of the hardware linked list structure of each child
  283. * descriptor.
  284. *
  285. * The CTRLA register provides us with the amount of data
  286. * already read from the source for the current child
  287. * descriptor. So we can compute a more accurate residue by also
  288. * removing the number of bytes corresponding to this amount of
  289. * data.
  290. *
  291. * However, the DSCR and CTRLA registers cannot be read both
  292. * atomically. Hence a race condition may occur: the first read
  293. * register may refer to one child descriptor whereas the second
  294. * read may refer to a later child descriptor in the list
  295. * because of the DMA transfer progression inbetween the two
  296. * reads.
  297. *
  298. * One solution could have been to pause the DMA transfer, read
  299. * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
  300. * this approach presents some drawbacks:
  301. * - If the DMA transfer is paused, RX overruns or TX underruns
  302. * are more likey to occur depending on the system latency.
  303. * Taking the USART driver as an example, it uses a cyclic DMA
  304. * transfer to read data from the Receive Holding Register
  305. * (RHR) to avoid RX overruns since the RHR is not protected
  306. * by any FIFO on most Atmel SoCs. So pausing the DMA transfer
  307. * to compute the residue would break the USART driver design.
  308. * - The atc_pause() function masks interrupts but we'd rather
  309. * avoid to do so for system latency purpose.
  310. *
  311. * Then we'd rather use another solution: the DSCR is read a
  312. * first time, the CTRLA is read in turn, next the DSCR is read
  313. * a second time. If the two consecutive read values of the DSCR
  314. * are the same then we assume both refers to the very same
  315. * child descriptor as well as the CTRLA value read inbetween
  316. * does. For cyclic tranfers, the assumption is that a full loop
  317. * is "not so fast".
  318. * If the two DSCR values are different, we read again the CTRLA
  319. * then the DSCR till two consecutive read values from DSCR are
  320. * equal or till the maxium trials is reach.
  321. * This algorithm is very unlikely not to find a stable value for
  322. * DSCR.
  323. */
  324. dscr = channel_readl(atchan, DSCR);
  325. rmb(); /* ensure DSCR is read before CTRLA */
  326. ctrla = channel_readl(atchan, CTRLA);
  327. for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {
  328. u32 new_dscr;
  329. rmb(); /* ensure DSCR is read after CTRLA */
  330. new_dscr = channel_readl(atchan, DSCR);
  331. /*
  332. * If the DSCR register value has not changed inside the
  333. * DMA controller since the previous read, we assume
  334. * that both the dscr and ctrla values refers to the
  335. * very same descriptor.
  336. */
  337. if (likely(new_dscr == dscr))
  338. break;
  339. /*
  340. * DSCR has changed inside the DMA controller, so the
  341. * previouly read value of CTRLA may refer to an already
  342. * processed descriptor hence could be outdated.
  343. * We need to update ctrla to match the current
  344. * descriptor.
  345. */
  346. dscr = new_dscr;
  347. rmb(); /* ensure DSCR is read before CTRLA */
  348. ctrla = channel_readl(atchan, CTRLA);
  349. }
  350. if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))
  351. return -ETIMEDOUT;
  352. /* for the first descriptor we can be more accurate */
  353. if (desc_first->lli.dscr == dscr)
  354. return atc_calc_bytes_left(ret, ctrla);
  355. ret -= desc_first->len;
  356. list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
  357. if (desc->lli.dscr == dscr)
  358. break;
  359. ret -= desc->len;
  360. }
  361. /*
  362. * For the current descriptor in the chain we can calculate
  363. * the remaining bytes using the channel's register.
  364. */
  365. ret = atc_calc_bytes_left(ret, ctrla);
  366. } else {
  367. /* single transfer */
  368. ctrla = channel_readl(atchan, CTRLA);
  369. ret = atc_calc_bytes_left(ret, ctrla);
  370. }
  371. return ret;
  372. }
  373. /**
  374. * atc_chain_complete - finish work for one transaction chain
  375. * @atchan: channel we work on
  376. * @desc: descriptor at the head of the chain we want do complete
  377. */
  378. static void
  379. atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
  380. {
  381. struct dma_async_tx_descriptor *txd = &desc->txd;
  382. struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
  383. unsigned long flags;
  384. dev_vdbg(chan2dev(&atchan->chan_common),
  385. "descriptor %u complete\n", txd->cookie);
  386. spin_lock_irqsave(&atchan->lock, flags);
  387. /* mark the descriptor as complete for non cyclic cases only */
  388. if (!atc_chan_is_cyclic(atchan))
  389. dma_cookie_complete(txd);
  390. /* If the transfer was a memset, free our temporary buffer */
  391. if (desc->memset_buffer) {
  392. dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
  393. desc->memset_paddr);
  394. desc->memset_buffer = false;
  395. }
  396. /* move children to free_list */
  397. list_splice_init(&desc->tx_list, &atchan->free_list);
  398. /* move myself to free_list */
  399. list_move(&desc->desc_node, &atchan->free_list);
  400. spin_unlock_irqrestore(&atchan->lock, flags);
  401. dma_descriptor_unmap(txd);
  402. /* for cyclic transfers,
  403. * no need to replay callback function while stopping */
  404. if (!atc_chan_is_cyclic(atchan))
  405. dmaengine_desc_get_callback_invoke(txd, NULL);
  406. dma_run_dependencies(txd);
  407. }
  408. /**
  409. * atc_complete_all - finish work for all transactions
  410. * @atchan: channel to complete transactions for
  411. *
  412. * Eventually submit queued descriptors if any
  413. *
  414. * Assume channel is idle while calling this function
  415. * Called with atchan->lock held and bh disabled
  416. */
  417. static void atc_complete_all(struct at_dma_chan *atchan)
  418. {
  419. struct at_desc *desc, *_desc;
  420. LIST_HEAD(list);
  421. unsigned long flags;
  422. dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
  423. spin_lock_irqsave(&atchan->lock, flags);
  424. /*
  425. * Submit queued descriptors ASAP, i.e. before we go through
  426. * the completed ones.
  427. */
  428. if (!list_empty(&atchan->queue))
  429. atc_dostart(atchan, atc_first_queued(atchan));
  430. /* empty active_list now it is completed */
  431. list_splice_init(&atchan->active_list, &list);
  432. /* empty queue list by moving descriptors (if any) to active_list */
  433. list_splice_init(&atchan->queue, &atchan->active_list);
  434. spin_unlock_irqrestore(&atchan->lock, flags);
  435. list_for_each_entry_safe(desc, _desc, &list, desc_node)
  436. atc_chain_complete(atchan, desc);
  437. }
  438. /**
  439. * atc_advance_work - at the end of a transaction, move forward
  440. * @atchan: channel where the transaction ended
  441. */
  442. static void atc_advance_work(struct at_dma_chan *atchan)
  443. {
  444. unsigned long flags;
  445. int ret;
  446. dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
  447. spin_lock_irqsave(&atchan->lock, flags);
  448. ret = atc_chan_is_enabled(atchan);
  449. spin_unlock_irqrestore(&atchan->lock, flags);
  450. if (ret)
  451. return;
  452. if (list_empty(&atchan->active_list) ||
  453. list_is_singular(&atchan->active_list))
  454. return atc_complete_all(atchan);
  455. atc_chain_complete(atchan, atc_first_active(atchan));
  456. /* advance work */
  457. spin_lock_irqsave(&atchan->lock, flags);
  458. atc_dostart(atchan, atc_first_active(atchan));
  459. spin_unlock_irqrestore(&atchan->lock, flags);
  460. }
  461. /**
  462. * atc_handle_error - handle errors reported by DMA controller
  463. * @atchan: channel where error occurs
  464. */
  465. static void atc_handle_error(struct at_dma_chan *atchan)
  466. {
  467. struct at_desc *bad_desc;
  468. struct at_desc *child;
  469. unsigned long flags;
  470. spin_lock_irqsave(&atchan->lock, flags);
  471. /*
  472. * The descriptor currently at the head of the active list is
  473. * broked. Since we don't have any way to report errors, we'll
  474. * just have to scream loudly and try to carry on.
  475. */
  476. bad_desc = atc_first_active(atchan);
  477. list_del_init(&bad_desc->desc_node);
  478. /* As we are stopped, take advantage to push queued descriptors
  479. * in active_list */
  480. list_splice_init(&atchan->queue, atchan->active_list.prev);
  481. /* Try to restart the controller */
  482. if (!list_empty(&atchan->active_list))
  483. atc_dostart(atchan, atc_first_active(atchan));
  484. /*
  485. * KERN_CRITICAL may seem harsh, but since this only happens
  486. * when someone submits a bad physical address in a
  487. * descriptor, we should consider ourselves lucky that the
  488. * controller flagged an error instead of scribbling over
  489. * random memory locations.
  490. */
  491. dev_crit(chan2dev(&atchan->chan_common),
  492. "Bad descriptor submitted for DMA!\n");
  493. dev_crit(chan2dev(&atchan->chan_common),
  494. " cookie: %d\n", bad_desc->txd.cookie);
  495. atc_dump_lli(atchan, &bad_desc->lli);
  496. list_for_each_entry(child, &bad_desc->tx_list, desc_node)
  497. atc_dump_lli(atchan, &child->lli);
  498. spin_unlock_irqrestore(&atchan->lock, flags);
  499. /* Pretend the descriptor completed successfully */
  500. atc_chain_complete(atchan, bad_desc);
  501. }
  502. /**
  503. * atc_handle_cyclic - at the end of a period, run callback function
  504. * @atchan: channel used for cyclic operations
  505. */
  506. static void atc_handle_cyclic(struct at_dma_chan *atchan)
  507. {
  508. struct at_desc *first = atc_first_active(atchan);
  509. struct dma_async_tx_descriptor *txd = &first->txd;
  510. dev_vdbg(chan2dev(&atchan->chan_common),
  511. "new cyclic period llp 0x%08x\n",
  512. channel_readl(atchan, DSCR));
  513. dmaengine_desc_get_callback_invoke(txd, NULL);
  514. }
  515. /*-- IRQ & Tasklet ---------------------------------------------------*/
  516. static void atc_tasklet(struct tasklet_struct *t)
  517. {
  518. struct at_dma_chan *atchan = from_tasklet(atchan, t, tasklet);
  519. if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
  520. return atc_handle_error(atchan);
  521. if (atc_chan_is_cyclic(atchan))
  522. return atc_handle_cyclic(atchan);
  523. atc_advance_work(atchan);
  524. }
  525. static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
  526. {
  527. struct at_dma *atdma = (struct at_dma *)dev_id;
  528. struct at_dma_chan *atchan;
  529. int i;
  530. u32 status, pending, imr;
  531. int ret = IRQ_NONE;
  532. do {
  533. imr = dma_readl(atdma, EBCIMR);
  534. status = dma_readl(atdma, EBCISR);
  535. pending = status & imr;
  536. if (!pending)
  537. break;
  538. dev_vdbg(atdma->dma_common.dev,
  539. "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
  540. status, imr, pending);
  541. for (i = 0; i < atdma->dma_common.chancnt; i++) {
  542. atchan = &atdma->chan[i];
  543. if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
  544. if (pending & AT_DMA_ERR(i)) {
  545. /* Disable channel on AHB error */
  546. dma_writel(atdma, CHDR,
  547. AT_DMA_RES(i) | atchan->mask);
  548. /* Give information to tasklet */
  549. set_bit(ATC_IS_ERROR, &atchan->status);
  550. }
  551. tasklet_schedule(&atchan->tasklet);
  552. ret = IRQ_HANDLED;
  553. }
  554. }
  555. } while (pending);
  556. return ret;
  557. }
  558. /*-- DMA Engine API --------------------------------------------------*/
  559. /**
  560. * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
  561. * @tx: descriptor at the head of the transaction chain
  562. *
  563. * Queue chain if DMA engine is working already
  564. *
  565. * Cookie increment and adding to active_list or queue must be atomic
  566. */
  567. static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
  568. {
  569. struct at_desc *desc = txd_to_at_desc(tx);
  570. struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
  571. dma_cookie_t cookie;
  572. unsigned long flags;
  573. spin_lock_irqsave(&atchan->lock, flags);
  574. cookie = dma_cookie_assign(tx);
  575. if (list_empty(&atchan->active_list)) {
  576. dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
  577. desc->txd.cookie);
  578. atc_dostart(atchan, desc);
  579. list_add_tail(&desc->desc_node, &atchan->active_list);
  580. } else {
  581. dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
  582. desc->txd.cookie);
  583. list_add_tail(&desc->desc_node, &atchan->queue);
  584. }
  585. spin_unlock_irqrestore(&atchan->lock, flags);
  586. return cookie;
  587. }
  588. /**
  589. * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
  590. * @chan: the channel to prepare operation on
  591. * @xt: Interleaved transfer template
  592. * @flags: tx descriptor status flags
  593. */
  594. static struct dma_async_tx_descriptor *
  595. atc_prep_dma_interleaved(struct dma_chan *chan,
  596. struct dma_interleaved_template *xt,
  597. unsigned long flags)
  598. {
  599. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  600. struct data_chunk *first;
  601. struct at_desc *desc = NULL;
  602. size_t xfer_count;
  603. unsigned int dwidth;
  604. u32 ctrla;
  605. u32 ctrlb;
  606. size_t len = 0;
  607. int i;
  608. if (unlikely(!xt || xt->numf != 1 || !xt->frame_size))
  609. return NULL;
  610. first = xt->sgl;
  611. dev_info(chan2dev(chan),
  612. "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
  613. __func__, &xt->src_start, &xt->dst_start, xt->numf,
  614. xt->frame_size, flags);
  615. /*
  616. * The controller can only "skip" X bytes every Y bytes, so we
  617. * need to make sure we are given a template that fit that
  618. * description, ie a template with chunks that always have the
  619. * same size, with the same ICGs.
  620. */
  621. for (i = 0; i < xt->frame_size; i++) {
  622. struct data_chunk *chunk = xt->sgl + i;
  623. if ((chunk->size != xt->sgl->size) ||
  624. (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) ||
  625. (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) {
  626. dev_err(chan2dev(chan),
  627. "%s: the controller can transfer only identical chunks\n",
  628. __func__);
  629. return NULL;
  630. }
  631. len += chunk->size;
  632. }
  633. dwidth = atc_get_xfer_width(xt->src_start,
  634. xt->dst_start, len);
  635. xfer_count = len >> dwidth;
  636. if (xfer_count > ATC_BTSIZE_MAX) {
  637. dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
  638. return NULL;
  639. }
  640. ctrla = ATC_SRC_WIDTH(dwidth) |
  641. ATC_DST_WIDTH(dwidth);
  642. ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
  643. | ATC_SRC_ADDR_MODE_INCR
  644. | ATC_DST_ADDR_MODE_INCR
  645. | ATC_SRC_PIP
  646. | ATC_DST_PIP
  647. | ATC_FC_MEM2MEM;
  648. /* create the transfer */
  649. desc = atc_desc_get(atchan);
  650. if (!desc) {
  651. dev_err(chan2dev(chan),
  652. "%s: couldn't allocate our descriptor\n", __func__);
  653. return NULL;
  654. }
  655. desc->lli.saddr = xt->src_start;
  656. desc->lli.daddr = xt->dst_start;
  657. desc->lli.ctrla = ctrla | xfer_count;
  658. desc->lli.ctrlb = ctrlb;
  659. desc->boundary = first->size >> dwidth;
  660. desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1;
  661. desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1;
  662. desc->txd.cookie = -EBUSY;
  663. desc->total_len = desc->len = len;
  664. /* set end-of-link to the last link descriptor of list*/
  665. set_desc_eol(desc);
  666. desc->txd.flags = flags; /* client is in control of this ack */
  667. return &desc->txd;
  668. }
  669. /**
  670. * atc_prep_dma_memcpy - prepare a memcpy operation
  671. * @chan: the channel to prepare operation on
  672. * @dest: operation virtual destination address
  673. * @src: operation virtual source address
  674. * @len: operation length
  675. * @flags: tx descriptor status flags
  676. */
  677. static struct dma_async_tx_descriptor *
  678. atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  679. size_t len, unsigned long flags)
  680. {
  681. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  682. struct at_desc *desc = NULL;
  683. struct at_desc *first = NULL;
  684. struct at_desc *prev = NULL;
  685. size_t xfer_count;
  686. size_t offset;
  687. unsigned int src_width;
  688. unsigned int dst_width;
  689. u32 ctrla;
  690. u32 ctrlb;
  691. dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n",
  692. &dest, &src, len, flags);
  693. if (unlikely(!len)) {
  694. dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
  695. return NULL;
  696. }
  697. ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
  698. | ATC_SRC_ADDR_MODE_INCR
  699. | ATC_DST_ADDR_MODE_INCR
  700. | ATC_FC_MEM2MEM;
  701. /*
  702. * We can be a lot more clever here, but this should take care
  703. * of the most common optimization.
  704. */
  705. src_width = dst_width = atc_get_xfer_width(src, dest, len);
  706. ctrla = ATC_SRC_WIDTH(src_width) |
  707. ATC_DST_WIDTH(dst_width);
  708. for (offset = 0; offset < len; offset += xfer_count << src_width) {
  709. xfer_count = min_t(size_t, (len - offset) >> src_width,
  710. ATC_BTSIZE_MAX);
  711. desc = atc_desc_get(atchan);
  712. if (!desc)
  713. goto err_desc_get;
  714. desc->lli.saddr = src + offset;
  715. desc->lli.daddr = dest + offset;
  716. desc->lli.ctrla = ctrla | xfer_count;
  717. desc->lli.ctrlb = ctrlb;
  718. desc->txd.cookie = 0;
  719. desc->len = xfer_count << src_width;
  720. atc_desc_chain(&first, &prev, desc);
  721. }
  722. /* First descriptor of the chain embedds additional information */
  723. first->txd.cookie = -EBUSY;
  724. first->total_len = len;
  725. /* set end-of-link to the last link descriptor of list*/
  726. set_desc_eol(desc);
  727. first->txd.flags = flags; /* client is in control of this ack */
  728. return &first->txd;
  729. err_desc_get:
  730. atc_desc_put(atchan, first);
  731. return NULL;
  732. }
  733. static struct at_desc *atc_create_memset_desc(struct dma_chan *chan,
  734. dma_addr_t psrc,
  735. dma_addr_t pdst,
  736. size_t len)
  737. {
  738. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  739. struct at_desc *desc;
  740. size_t xfer_count;
  741. u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2);
  742. u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
  743. ATC_SRC_ADDR_MODE_FIXED |
  744. ATC_DST_ADDR_MODE_INCR |
  745. ATC_FC_MEM2MEM;
  746. xfer_count = len >> 2;
  747. if (xfer_count > ATC_BTSIZE_MAX) {
  748. dev_err(chan2dev(chan), "%s: buffer is too big\n",
  749. __func__);
  750. return NULL;
  751. }
  752. desc = atc_desc_get(atchan);
  753. if (!desc) {
  754. dev_err(chan2dev(chan), "%s: can't get a descriptor\n",
  755. __func__);
  756. return NULL;
  757. }
  758. desc->lli.saddr = psrc;
  759. desc->lli.daddr = pdst;
  760. desc->lli.ctrla = ctrla | xfer_count;
  761. desc->lli.ctrlb = ctrlb;
  762. desc->txd.cookie = 0;
  763. desc->len = len;
  764. return desc;
  765. }
  766. /**
  767. * atc_prep_dma_memset - prepare a memcpy operation
  768. * @chan: the channel to prepare operation on
  769. * @dest: operation virtual destination address
  770. * @value: value to set memory buffer to
  771. * @len: operation length
  772. * @flags: tx descriptor status flags
  773. */
  774. static struct dma_async_tx_descriptor *
  775. atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
  776. size_t len, unsigned long flags)
  777. {
  778. struct at_dma *atdma = to_at_dma(chan->device);
  779. struct at_desc *desc;
  780. void __iomem *vaddr;
  781. dma_addr_t paddr;
  782. dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__,
  783. &dest, value, len, flags);
  784. if (unlikely(!len)) {
  785. dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
  786. return NULL;
  787. }
  788. if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
  789. dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n",
  790. __func__);
  791. return NULL;
  792. }
  793. vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr);
  794. if (!vaddr) {
  795. dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
  796. __func__);
  797. return NULL;
  798. }
  799. *(u32*)vaddr = value;
  800. desc = atc_create_memset_desc(chan, paddr, dest, len);
  801. if (!desc) {
  802. dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n",
  803. __func__);
  804. goto err_free_buffer;
  805. }
  806. desc->memset_paddr = paddr;
  807. desc->memset_vaddr = vaddr;
  808. desc->memset_buffer = true;
  809. desc->txd.cookie = -EBUSY;
  810. desc->total_len = len;
  811. /* set end-of-link on the descriptor */
  812. set_desc_eol(desc);
  813. desc->txd.flags = flags;
  814. return &desc->txd;
  815. err_free_buffer:
  816. dma_pool_free(atdma->memset_pool, vaddr, paddr);
  817. return NULL;
  818. }
  819. static struct dma_async_tx_descriptor *
  820. atc_prep_dma_memset_sg(struct dma_chan *chan,
  821. struct scatterlist *sgl,
  822. unsigned int sg_len, int value,
  823. unsigned long flags)
  824. {
  825. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  826. struct at_dma *atdma = to_at_dma(chan->device);
  827. struct at_desc *desc = NULL, *first = NULL, *prev = NULL;
  828. struct scatterlist *sg;
  829. void __iomem *vaddr;
  830. dma_addr_t paddr;
  831. size_t total_len = 0;
  832. int i;
  833. dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__,
  834. value, sg_len, flags);
  835. if (unlikely(!sgl || !sg_len)) {
  836. dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n",
  837. __func__);
  838. return NULL;
  839. }
  840. vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr);
  841. if (!vaddr) {
  842. dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
  843. __func__);
  844. return NULL;
  845. }
  846. *(u32*)vaddr = value;
  847. for_each_sg(sgl, sg, sg_len, i) {
  848. dma_addr_t dest = sg_dma_address(sg);
  849. size_t len = sg_dma_len(sg);
  850. dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n",
  851. __func__, &dest, len);
  852. if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
  853. dev_err(chan2dev(chan), "%s: buffer is not aligned\n",
  854. __func__);
  855. goto err_put_desc;
  856. }
  857. desc = atc_create_memset_desc(chan, paddr, dest, len);
  858. if (!desc)
  859. goto err_put_desc;
  860. atc_desc_chain(&first, &prev, desc);
  861. total_len += len;
  862. }
  863. /*
  864. * Only set the buffer pointers on the last descriptor to
  865. * avoid free'ing while we have our transfer still going
  866. */
  867. desc->memset_paddr = paddr;
  868. desc->memset_vaddr = vaddr;
  869. desc->memset_buffer = true;
  870. first->txd.cookie = -EBUSY;
  871. first->total_len = total_len;
  872. /* set end-of-link on the descriptor */
  873. set_desc_eol(desc);
  874. first->txd.flags = flags;
  875. return &first->txd;
  876. err_put_desc:
  877. atc_desc_put(atchan, first);
  878. return NULL;
  879. }
  880. /**
  881. * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
  882. * @chan: DMA channel
  883. * @sgl: scatterlist to transfer to/from
  884. * @sg_len: number of entries in @scatterlist
  885. * @direction: DMA direction
  886. * @flags: tx descriptor status flags
  887. * @context: transaction context (ignored)
  888. */
  889. static struct dma_async_tx_descriptor *
  890. atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  891. unsigned int sg_len, enum dma_transfer_direction direction,
  892. unsigned long flags, void *context)
  893. {
  894. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  895. struct at_dma_slave *atslave = chan->private;
  896. struct dma_slave_config *sconfig = &atchan->dma_sconfig;
  897. struct at_desc *first = NULL;
  898. struct at_desc *prev = NULL;
  899. u32 ctrla;
  900. u32 ctrlb;
  901. dma_addr_t reg;
  902. unsigned int reg_width;
  903. unsigned int mem_width;
  904. unsigned int i;
  905. struct scatterlist *sg;
  906. size_t total_len = 0;
  907. dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
  908. sg_len,
  909. direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
  910. flags);
  911. if (unlikely(!atslave || !sg_len)) {
  912. dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
  913. return NULL;
  914. }
  915. ctrla = ATC_SCSIZE(sconfig->src_maxburst)
  916. | ATC_DCSIZE(sconfig->dst_maxburst);
  917. ctrlb = ATC_IEN;
  918. switch (direction) {
  919. case DMA_MEM_TO_DEV:
  920. reg_width = convert_buswidth(sconfig->dst_addr_width);
  921. ctrla |= ATC_DST_WIDTH(reg_width);
  922. ctrlb |= ATC_DST_ADDR_MODE_FIXED
  923. | ATC_SRC_ADDR_MODE_INCR
  924. | ATC_FC_MEM2PER
  925. | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
  926. reg = sconfig->dst_addr;
  927. for_each_sg(sgl, sg, sg_len, i) {
  928. struct at_desc *desc;
  929. u32 len;
  930. u32 mem;
  931. desc = atc_desc_get(atchan);
  932. if (!desc)
  933. goto err_desc_get;
  934. mem = sg_dma_address(sg);
  935. len = sg_dma_len(sg);
  936. if (unlikely(!len)) {
  937. dev_dbg(chan2dev(chan),
  938. "prep_slave_sg: sg(%d) data length is zero\n", i);
  939. goto err;
  940. }
  941. mem_width = 2;
  942. if (unlikely(mem & 3 || len & 3))
  943. mem_width = 0;
  944. desc->lli.saddr = mem;
  945. desc->lli.daddr = reg;
  946. desc->lli.ctrla = ctrla
  947. | ATC_SRC_WIDTH(mem_width)
  948. | len >> mem_width;
  949. desc->lli.ctrlb = ctrlb;
  950. desc->len = len;
  951. atc_desc_chain(&first, &prev, desc);
  952. total_len += len;
  953. }
  954. break;
  955. case DMA_DEV_TO_MEM:
  956. reg_width = convert_buswidth(sconfig->src_addr_width);
  957. ctrla |= ATC_SRC_WIDTH(reg_width);
  958. ctrlb |= ATC_DST_ADDR_MODE_INCR
  959. | ATC_SRC_ADDR_MODE_FIXED
  960. | ATC_FC_PER2MEM
  961. | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
  962. reg = sconfig->src_addr;
  963. for_each_sg(sgl, sg, sg_len, i) {
  964. struct at_desc *desc;
  965. u32 len;
  966. u32 mem;
  967. desc = atc_desc_get(atchan);
  968. if (!desc)
  969. goto err_desc_get;
  970. mem = sg_dma_address(sg);
  971. len = sg_dma_len(sg);
  972. if (unlikely(!len)) {
  973. dev_dbg(chan2dev(chan),
  974. "prep_slave_sg: sg(%d) data length is zero\n", i);
  975. goto err;
  976. }
  977. mem_width = 2;
  978. if (unlikely(mem & 3 || len & 3))
  979. mem_width = 0;
  980. desc->lli.saddr = reg;
  981. desc->lli.daddr = mem;
  982. desc->lli.ctrla = ctrla
  983. | ATC_DST_WIDTH(mem_width)
  984. | len >> reg_width;
  985. desc->lli.ctrlb = ctrlb;
  986. desc->len = len;
  987. atc_desc_chain(&first, &prev, desc);
  988. total_len += len;
  989. }
  990. break;
  991. default:
  992. return NULL;
  993. }
  994. /* set end-of-link to the last link descriptor of list*/
  995. set_desc_eol(prev);
  996. /* First descriptor of the chain embedds additional information */
  997. first->txd.cookie = -EBUSY;
  998. first->total_len = total_len;
  999. /* first link descriptor of list is responsible of flags */
  1000. first->txd.flags = flags; /* client is in control of this ack */
  1001. return &first->txd;
  1002. err_desc_get:
  1003. dev_err(chan2dev(chan), "not enough descriptors available\n");
  1004. err:
  1005. atc_desc_put(atchan, first);
  1006. return NULL;
  1007. }
  1008. /*
  1009. * atc_dma_cyclic_check_values
  1010. * Check for too big/unaligned periods and unaligned DMA buffer
  1011. */
  1012. static int
  1013. atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
  1014. size_t period_len)
  1015. {
  1016. if (period_len > (ATC_BTSIZE_MAX << reg_width))
  1017. goto err_out;
  1018. if (unlikely(period_len & ((1 << reg_width) - 1)))
  1019. goto err_out;
  1020. if (unlikely(buf_addr & ((1 << reg_width) - 1)))
  1021. goto err_out;
  1022. return 0;
  1023. err_out:
  1024. return -EINVAL;
  1025. }
  1026. /*
  1027. * atc_dma_cyclic_fill_desc - Fill one period descriptor
  1028. */
  1029. static int
  1030. atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
  1031. unsigned int period_index, dma_addr_t buf_addr,
  1032. unsigned int reg_width, size_t period_len,
  1033. enum dma_transfer_direction direction)
  1034. {
  1035. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1036. struct dma_slave_config *sconfig = &atchan->dma_sconfig;
  1037. u32 ctrla;
  1038. /* prepare common CRTLA value */
  1039. ctrla = ATC_SCSIZE(sconfig->src_maxburst)
  1040. | ATC_DCSIZE(sconfig->dst_maxburst)
  1041. | ATC_DST_WIDTH(reg_width)
  1042. | ATC_SRC_WIDTH(reg_width)
  1043. | period_len >> reg_width;
  1044. switch (direction) {
  1045. case DMA_MEM_TO_DEV:
  1046. desc->lli.saddr = buf_addr + (period_len * period_index);
  1047. desc->lli.daddr = sconfig->dst_addr;
  1048. desc->lli.ctrla = ctrla;
  1049. desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
  1050. | ATC_SRC_ADDR_MODE_INCR
  1051. | ATC_FC_MEM2PER
  1052. | ATC_SIF(atchan->mem_if)
  1053. | ATC_DIF(atchan->per_if);
  1054. desc->len = period_len;
  1055. break;
  1056. case DMA_DEV_TO_MEM:
  1057. desc->lli.saddr = sconfig->src_addr;
  1058. desc->lli.daddr = buf_addr + (period_len * period_index);
  1059. desc->lli.ctrla = ctrla;
  1060. desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
  1061. | ATC_SRC_ADDR_MODE_FIXED
  1062. | ATC_FC_PER2MEM
  1063. | ATC_SIF(atchan->per_if)
  1064. | ATC_DIF(atchan->mem_if);
  1065. desc->len = period_len;
  1066. break;
  1067. default:
  1068. return -EINVAL;
  1069. }
  1070. return 0;
  1071. }
  1072. /**
  1073. * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
  1074. * @chan: the DMA channel to prepare
  1075. * @buf_addr: physical DMA address where the buffer starts
  1076. * @buf_len: total number of bytes for the entire buffer
  1077. * @period_len: number of bytes for each period
  1078. * @direction: transfer direction, to or from device
  1079. * @flags: tx descriptor status flags
  1080. */
  1081. static struct dma_async_tx_descriptor *
  1082. atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  1083. size_t period_len, enum dma_transfer_direction direction,
  1084. unsigned long flags)
  1085. {
  1086. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1087. struct at_dma_slave *atslave = chan->private;
  1088. struct dma_slave_config *sconfig = &atchan->dma_sconfig;
  1089. struct at_desc *first = NULL;
  1090. struct at_desc *prev = NULL;
  1091. unsigned long was_cyclic;
  1092. unsigned int reg_width;
  1093. unsigned int periods = buf_len / period_len;
  1094. unsigned int i;
  1095. dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%d/%d)\n",
  1096. direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
  1097. &buf_addr,
  1098. periods, buf_len, period_len);
  1099. if (unlikely(!atslave || !buf_len || !period_len)) {
  1100. dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
  1101. return NULL;
  1102. }
  1103. was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
  1104. if (was_cyclic) {
  1105. dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
  1106. return NULL;
  1107. }
  1108. if (unlikely(!is_slave_direction(direction)))
  1109. goto err_out;
  1110. if (direction == DMA_MEM_TO_DEV)
  1111. reg_width = convert_buswidth(sconfig->dst_addr_width);
  1112. else
  1113. reg_width = convert_buswidth(sconfig->src_addr_width);
  1114. /* Check for too big/unaligned periods and unaligned DMA buffer */
  1115. if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
  1116. goto err_out;
  1117. /* build cyclic linked list */
  1118. for (i = 0; i < periods; i++) {
  1119. struct at_desc *desc;
  1120. desc = atc_desc_get(atchan);
  1121. if (!desc)
  1122. goto err_desc_get;
  1123. if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
  1124. reg_width, period_len, direction))
  1125. goto err_desc_get;
  1126. atc_desc_chain(&first, &prev, desc);
  1127. }
  1128. /* lets make a cyclic list */
  1129. prev->lli.dscr = first->txd.phys;
  1130. /* First descriptor of the chain embedds additional information */
  1131. first->txd.cookie = -EBUSY;
  1132. first->total_len = buf_len;
  1133. return &first->txd;
  1134. err_desc_get:
  1135. dev_err(chan2dev(chan), "not enough descriptors available\n");
  1136. atc_desc_put(atchan, first);
  1137. err_out:
  1138. clear_bit(ATC_IS_CYCLIC, &atchan->status);
  1139. return NULL;
  1140. }
  1141. static int atc_config(struct dma_chan *chan,
  1142. struct dma_slave_config *sconfig)
  1143. {
  1144. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1145. dev_vdbg(chan2dev(chan), "%s\n", __func__);
  1146. /* Check if it is chan is configured for slave transfers */
  1147. if (!chan->private)
  1148. return -EINVAL;
  1149. memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
  1150. convert_burst(&atchan->dma_sconfig.src_maxburst);
  1151. convert_burst(&atchan->dma_sconfig.dst_maxburst);
  1152. return 0;
  1153. }
  1154. static int atc_pause(struct dma_chan *chan)
  1155. {
  1156. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1157. struct at_dma *atdma = to_at_dma(chan->device);
  1158. int chan_id = atchan->chan_common.chan_id;
  1159. unsigned long flags;
  1160. dev_vdbg(chan2dev(chan), "%s\n", __func__);
  1161. spin_lock_irqsave(&atchan->lock, flags);
  1162. dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
  1163. set_bit(ATC_IS_PAUSED, &atchan->status);
  1164. spin_unlock_irqrestore(&atchan->lock, flags);
  1165. return 0;
  1166. }
  1167. static int atc_resume(struct dma_chan *chan)
  1168. {
  1169. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1170. struct at_dma *atdma = to_at_dma(chan->device);
  1171. int chan_id = atchan->chan_common.chan_id;
  1172. unsigned long flags;
  1173. dev_vdbg(chan2dev(chan), "%s\n", __func__);
  1174. if (!atc_chan_is_paused(atchan))
  1175. return 0;
  1176. spin_lock_irqsave(&atchan->lock, flags);
  1177. dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
  1178. clear_bit(ATC_IS_PAUSED, &atchan->status);
  1179. spin_unlock_irqrestore(&atchan->lock, flags);
  1180. return 0;
  1181. }
  1182. static int atc_terminate_all(struct dma_chan *chan)
  1183. {
  1184. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1185. struct at_dma *atdma = to_at_dma(chan->device);
  1186. int chan_id = atchan->chan_common.chan_id;
  1187. struct at_desc *desc, *_desc;
  1188. unsigned long flags;
  1189. LIST_HEAD(list);
  1190. dev_vdbg(chan2dev(chan), "%s\n", __func__);
  1191. /*
  1192. * This is only called when something went wrong elsewhere, so
  1193. * we don't really care about the data. Just disable the
  1194. * channel. We still have to poll the channel enable bit due
  1195. * to AHB/HSB limitations.
  1196. */
  1197. spin_lock_irqsave(&atchan->lock, flags);
  1198. /* disabling channel: must also remove suspend state */
  1199. dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
  1200. /* confirm that this channel is disabled */
  1201. while (dma_readl(atdma, CHSR) & atchan->mask)
  1202. cpu_relax();
  1203. /* active_list entries will end up before queued entries */
  1204. list_splice_init(&atchan->queue, &list);
  1205. list_splice_init(&atchan->active_list, &list);
  1206. spin_unlock_irqrestore(&atchan->lock, flags);
  1207. /* Flush all pending and queued descriptors */
  1208. list_for_each_entry_safe(desc, _desc, &list, desc_node)
  1209. atc_chain_complete(atchan, desc);
  1210. clear_bit(ATC_IS_PAUSED, &atchan->status);
  1211. /* if channel dedicated to cyclic operations, free it */
  1212. clear_bit(ATC_IS_CYCLIC, &atchan->status);
  1213. return 0;
  1214. }
  1215. /**
  1216. * atc_tx_status - poll for transaction completion
  1217. * @chan: DMA channel
  1218. * @cookie: transaction identifier to check status of
  1219. * @txstate: if not %NULL updated with transaction state
  1220. *
  1221. * If @txstate is passed in, upon return it reflect the driver
  1222. * internal state and can be used with dma_async_is_complete() to check
  1223. * the status of multiple cookies without re-checking hardware state.
  1224. */
  1225. static enum dma_status
  1226. atc_tx_status(struct dma_chan *chan,
  1227. dma_cookie_t cookie,
  1228. struct dma_tx_state *txstate)
  1229. {
  1230. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1231. unsigned long flags;
  1232. enum dma_status ret;
  1233. int bytes = 0;
  1234. ret = dma_cookie_status(chan, cookie, txstate);
  1235. if (ret == DMA_COMPLETE)
  1236. return ret;
  1237. /*
  1238. * There's no point calculating the residue if there's
  1239. * no txstate to store the value.
  1240. */
  1241. if (!txstate)
  1242. return DMA_ERROR;
  1243. spin_lock_irqsave(&atchan->lock, flags);
  1244. /* Get number of bytes left in the active transactions */
  1245. bytes = atc_get_bytes_left(chan, cookie);
  1246. spin_unlock_irqrestore(&atchan->lock, flags);
  1247. if (unlikely(bytes < 0)) {
  1248. dev_vdbg(chan2dev(chan), "get residual bytes error\n");
  1249. return DMA_ERROR;
  1250. } else {
  1251. dma_set_residue(txstate, bytes);
  1252. }
  1253. dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
  1254. ret, cookie, bytes);
  1255. return ret;
  1256. }
  1257. /**
  1258. * atc_issue_pending - try to finish work
  1259. * @chan: target DMA channel
  1260. */
  1261. static void atc_issue_pending(struct dma_chan *chan)
  1262. {
  1263. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1264. dev_vdbg(chan2dev(chan), "issue_pending\n");
  1265. /* Not needed for cyclic transfers */
  1266. if (atc_chan_is_cyclic(atchan))
  1267. return;
  1268. atc_advance_work(atchan);
  1269. }
  1270. /**
  1271. * atc_alloc_chan_resources - allocate resources for DMA channel
  1272. * @chan: allocate descriptor resources for this channel
  1273. *
  1274. * return - the number of allocated descriptors
  1275. */
  1276. static int atc_alloc_chan_resources(struct dma_chan *chan)
  1277. {
  1278. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1279. struct at_dma *atdma = to_at_dma(chan->device);
  1280. struct at_desc *desc;
  1281. struct at_dma_slave *atslave;
  1282. int i;
  1283. u32 cfg;
  1284. dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
  1285. /* ASSERT: channel is idle */
  1286. if (atc_chan_is_enabled(atchan)) {
  1287. dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
  1288. return -EIO;
  1289. }
  1290. if (!list_empty(&atchan->free_list)) {
  1291. dev_dbg(chan2dev(chan), "can't allocate channel resources (channel not freed from a previous use)\n");
  1292. return -EIO;
  1293. }
  1294. cfg = ATC_DEFAULT_CFG;
  1295. atslave = chan->private;
  1296. if (atslave) {
  1297. /*
  1298. * We need controller-specific data to set up slave
  1299. * transfers.
  1300. */
  1301. BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
  1302. /* if cfg configuration specified take it instead of default */
  1303. if (atslave->cfg)
  1304. cfg = atslave->cfg;
  1305. }
  1306. /* Allocate initial pool of descriptors */
  1307. for (i = 0; i < init_nr_desc_per_channel; i++) {
  1308. desc = atc_alloc_descriptor(chan, GFP_KERNEL);
  1309. if (!desc) {
  1310. dev_err(atdma->dma_common.dev,
  1311. "Only %d initial descriptors\n", i);
  1312. break;
  1313. }
  1314. list_add_tail(&desc->desc_node, &atchan->free_list);
  1315. }
  1316. dma_cookie_init(chan);
  1317. /* channel parameters */
  1318. channel_writel(atchan, CFG, cfg);
  1319. dev_dbg(chan2dev(chan),
  1320. "alloc_chan_resources: allocated %d descriptors\n", i);
  1321. return i;
  1322. }
  1323. /**
  1324. * atc_free_chan_resources - free all channel resources
  1325. * @chan: DMA channel
  1326. */
  1327. static void atc_free_chan_resources(struct dma_chan *chan)
  1328. {
  1329. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1330. struct at_dma *atdma = to_at_dma(chan->device);
  1331. struct at_desc *desc, *_desc;
  1332. LIST_HEAD(list);
  1333. /* ASSERT: channel is idle */
  1334. BUG_ON(!list_empty(&atchan->active_list));
  1335. BUG_ON(!list_empty(&atchan->queue));
  1336. BUG_ON(atc_chan_is_enabled(atchan));
  1337. list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
  1338. dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
  1339. list_del(&desc->desc_node);
  1340. /* free link descriptor */
  1341. dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
  1342. }
  1343. list_splice_init(&atchan->free_list, &list);
  1344. atchan->status = 0;
  1345. /*
  1346. * Free atslave allocated in at_dma_xlate()
  1347. */
  1348. kfree(chan->private);
  1349. chan->private = NULL;
  1350. dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
  1351. }
  1352. #ifdef CONFIG_OF
  1353. static bool at_dma_filter(struct dma_chan *chan, void *slave)
  1354. {
  1355. struct at_dma_slave *atslave = slave;
  1356. if (atslave->dma_dev == chan->device->dev) {
  1357. chan->private = atslave;
  1358. return true;
  1359. } else {
  1360. return false;
  1361. }
  1362. }
  1363. static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
  1364. struct of_dma *of_dma)
  1365. {
  1366. struct dma_chan *chan;
  1367. struct at_dma_chan *atchan;
  1368. struct at_dma_slave *atslave;
  1369. dma_cap_mask_t mask;
  1370. unsigned int per_id;
  1371. struct platform_device *dmac_pdev;
  1372. if (dma_spec->args_count != 2)
  1373. return NULL;
  1374. dmac_pdev = of_find_device_by_node(dma_spec->np);
  1375. if (!dmac_pdev)
  1376. return NULL;
  1377. dma_cap_zero(mask);
  1378. dma_cap_set(DMA_SLAVE, mask);
  1379. atslave = kmalloc(sizeof(*atslave), GFP_KERNEL);
  1380. if (!atslave) {
  1381. put_device(&dmac_pdev->dev);
  1382. return NULL;
  1383. }
  1384. atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
  1385. /*
  1386. * We can fill both SRC_PER and DST_PER, one of these fields will be
  1387. * ignored depending on DMA transfer direction.
  1388. */
  1389. per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
  1390. atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
  1391. | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
  1392. /*
  1393. * We have to translate the value we get from the device tree since
  1394. * the half FIFO configuration value had to be 0 to keep backward
  1395. * compatibility.
  1396. */
  1397. switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
  1398. case AT91_DMA_CFG_FIFOCFG_ALAP:
  1399. atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
  1400. break;
  1401. case AT91_DMA_CFG_FIFOCFG_ASAP:
  1402. atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
  1403. break;
  1404. case AT91_DMA_CFG_FIFOCFG_HALF:
  1405. default:
  1406. atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
  1407. }
  1408. atslave->dma_dev = &dmac_pdev->dev;
  1409. chan = dma_request_channel(mask, at_dma_filter, atslave);
  1410. if (!chan) {
  1411. put_device(&dmac_pdev->dev);
  1412. kfree(atslave);
  1413. return NULL;
  1414. }
  1415. atchan = to_at_dma_chan(chan);
  1416. atchan->per_if = dma_spec->args[0] & 0xff;
  1417. atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
  1418. return chan;
  1419. }
  1420. #else
  1421. static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
  1422. struct of_dma *of_dma)
  1423. {
  1424. return NULL;
  1425. }
  1426. #endif
  1427. /*-- Module Management -----------------------------------------------*/
  1428. /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
  1429. static struct at_dma_platform_data at91sam9rl_config = {
  1430. .nr_channels = 2,
  1431. };
  1432. static struct at_dma_platform_data at91sam9g45_config = {
  1433. .nr_channels = 8,
  1434. };
  1435. #if defined(CONFIG_OF)
  1436. static const struct of_device_id atmel_dma_dt_ids[] = {
  1437. {
  1438. .compatible = "atmel,at91sam9rl-dma",
  1439. .data = &at91sam9rl_config,
  1440. }, {
  1441. .compatible = "atmel,at91sam9g45-dma",
  1442. .data = &at91sam9g45_config,
  1443. }, {
  1444. /* sentinel */
  1445. }
  1446. };
  1447. MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
  1448. #endif
  1449. static const struct platform_device_id atdma_devtypes[] = {
  1450. {
  1451. .name = "at91sam9rl_dma",
  1452. .driver_data = (unsigned long) &at91sam9rl_config,
  1453. }, {
  1454. .name = "at91sam9g45_dma",
  1455. .driver_data = (unsigned long) &at91sam9g45_config,
  1456. }, {
  1457. /* sentinel */
  1458. }
  1459. };
  1460. static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
  1461. struct platform_device *pdev)
  1462. {
  1463. if (pdev->dev.of_node) {
  1464. const struct of_device_id *match;
  1465. match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
  1466. if (match == NULL)
  1467. return NULL;
  1468. return match->data;
  1469. }
  1470. return (struct at_dma_platform_data *)
  1471. platform_get_device_id(pdev)->driver_data;
  1472. }
  1473. /**
  1474. * at_dma_off - disable DMA controller
  1475. * @atdma: the Atmel HDAMC device
  1476. */
  1477. static void at_dma_off(struct at_dma *atdma)
  1478. {
  1479. dma_writel(atdma, EN, 0);
  1480. /* disable all interrupts */
  1481. dma_writel(atdma, EBCIDR, -1L);
  1482. /* confirm that all channels are disabled */
  1483. while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
  1484. cpu_relax();
  1485. }
  1486. static int __init at_dma_probe(struct platform_device *pdev)
  1487. {
  1488. struct resource *io;
  1489. struct at_dma *atdma;
  1490. size_t size;
  1491. int irq;
  1492. int err;
  1493. int i;
  1494. const struct at_dma_platform_data *plat_dat;
  1495. /* setup platform data for each SoC */
  1496. dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
  1497. dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask);
  1498. dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
  1499. dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask);
  1500. dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask);
  1501. dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask);
  1502. dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
  1503. /* get DMA parameters from controller type */
  1504. plat_dat = at_dma_get_driver_data(pdev);
  1505. if (!plat_dat)
  1506. return -ENODEV;
  1507. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1508. if (!io)
  1509. return -EINVAL;
  1510. irq = platform_get_irq(pdev, 0);
  1511. if (irq < 0)
  1512. return irq;
  1513. size = sizeof(struct at_dma);
  1514. size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
  1515. atdma = kzalloc(size, GFP_KERNEL);
  1516. if (!atdma)
  1517. return -ENOMEM;
  1518. /* discover transaction capabilities */
  1519. atdma->dma_common.cap_mask = plat_dat->cap_mask;
  1520. atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
  1521. size = resource_size(io);
  1522. if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
  1523. err = -EBUSY;
  1524. goto err_kfree;
  1525. }
  1526. atdma->regs = ioremap(io->start, size);
  1527. if (!atdma->regs) {
  1528. err = -ENOMEM;
  1529. goto err_release_r;
  1530. }
  1531. atdma->clk = clk_get(&pdev->dev, "dma_clk");
  1532. if (IS_ERR(atdma->clk)) {
  1533. err = PTR_ERR(atdma->clk);
  1534. goto err_clk;
  1535. }
  1536. err = clk_prepare_enable(atdma->clk);
  1537. if (err)
  1538. goto err_clk_prepare;
  1539. /* force dma off, just in case */
  1540. at_dma_off(atdma);
  1541. err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
  1542. if (err)
  1543. goto err_irq;
  1544. platform_set_drvdata(pdev, atdma);
  1545. /* create a pool of consistent memory blocks for hardware descriptors */
  1546. atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
  1547. &pdev->dev, sizeof(struct at_desc),
  1548. 4 /* word alignment */, 0);
  1549. if (!atdma->dma_desc_pool) {
  1550. dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
  1551. err = -ENOMEM;
  1552. goto err_desc_pool_create;
  1553. }
  1554. /* create a pool of consistent memory blocks for memset blocks */
  1555. atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool",
  1556. &pdev->dev, sizeof(int), 4, 0);
  1557. if (!atdma->memset_pool) {
  1558. dev_err(&pdev->dev, "No memory for memset dma pool\n");
  1559. err = -ENOMEM;
  1560. goto err_memset_pool_create;
  1561. }
  1562. /* clear any pending interrupt */
  1563. while (dma_readl(atdma, EBCISR))
  1564. cpu_relax();
  1565. /* initialize channels related values */
  1566. INIT_LIST_HEAD(&atdma->dma_common.channels);
  1567. for (i = 0; i < plat_dat->nr_channels; i++) {
  1568. struct at_dma_chan *atchan = &atdma->chan[i];
  1569. atchan->mem_if = AT_DMA_MEM_IF;
  1570. atchan->per_if = AT_DMA_PER_IF;
  1571. atchan->chan_common.device = &atdma->dma_common;
  1572. dma_cookie_init(&atchan->chan_common);
  1573. list_add_tail(&atchan->chan_common.device_node,
  1574. &atdma->dma_common.channels);
  1575. atchan->ch_regs = atdma->regs + ch_regs(i);
  1576. spin_lock_init(&atchan->lock);
  1577. atchan->mask = 1 << i;
  1578. INIT_LIST_HEAD(&atchan->active_list);
  1579. INIT_LIST_HEAD(&atchan->queue);
  1580. INIT_LIST_HEAD(&atchan->free_list);
  1581. tasklet_setup(&atchan->tasklet, atc_tasklet);
  1582. atc_enable_chan_irq(atdma, i);
  1583. }
  1584. /* set base routines */
  1585. atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
  1586. atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
  1587. atdma->dma_common.device_tx_status = atc_tx_status;
  1588. atdma->dma_common.device_issue_pending = atc_issue_pending;
  1589. atdma->dma_common.dev = &pdev->dev;
  1590. /* set prep routines based on capability */
  1591. if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask))
  1592. atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved;
  1593. if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
  1594. atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
  1595. if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) {
  1596. atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset;
  1597. atdma->dma_common.device_prep_dma_memset_sg = atc_prep_dma_memset_sg;
  1598. atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES;
  1599. }
  1600. if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
  1601. atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
  1602. /* controller can do slave DMA: can trigger cyclic transfers */
  1603. dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
  1604. atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
  1605. atdma->dma_common.device_config = atc_config;
  1606. atdma->dma_common.device_pause = atc_pause;
  1607. atdma->dma_common.device_resume = atc_resume;
  1608. atdma->dma_common.device_terminate_all = atc_terminate_all;
  1609. atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS;
  1610. atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS;
  1611. atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  1612. atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  1613. }
  1614. dma_writel(atdma, EN, AT_DMA_ENABLE);
  1615. dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
  1616. dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
  1617. dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask) ? "set " : "",
  1618. dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
  1619. plat_dat->nr_channels);
  1620. dma_async_device_register(&atdma->dma_common);
  1621. /*
  1622. * Do not return an error if the dmac node is not present in order to
  1623. * not break the existing way of requesting channel with
  1624. * dma_request_channel().
  1625. */
  1626. if (pdev->dev.of_node) {
  1627. err = of_dma_controller_register(pdev->dev.of_node,
  1628. at_dma_xlate, atdma);
  1629. if (err) {
  1630. dev_err(&pdev->dev, "could not register of_dma_controller\n");
  1631. goto err_of_dma_controller_register;
  1632. }
  1633. }
  1634. return 0;
  1635. err_of_dma_controller_register:
  1636. dma_async_device_unregister(&atdma->dma_common);
  1637. dma_pool_destroy(atdma->memset_pool);
  1638. err_memset_pool_create:
  1639. dma_pool_destroy(atdma->dma_desc_pool);
  1640. err_desc_pool_create:
  1641. free_irq(platform_get_irq(pdev, 0), atdma);
  1642. err_irq:
  1643. clk_disable_unprepare(atdma->clk);
  1644. err_clk_prepare:
  1645. clk_put(atdma->clk);
  1646. err_clk:
  1647. iounmap(atdma->regs);
  1648. atdma->regs = NULL;
  1649. err_release_r:
  1650. release_mem_region(io->start, size);
  1651. err_kfree:
  1652. kfree(atdma);
  1653. return err;
  1654. }
  1655. static int at_dma_remove(struct platform_device *pdev)
  1656. {
  1657. struct at_dma *atdma = platform_get_drvdata(pdev);
  1658. struct dma_chan *chan, *_chan;
  1659. struct resource *io;
  1660. at_dma_off(atdma);
  1661. if (pdev->dev.of_node)
  1662. of_dma_controller_free(pdev->dev.of_node);
  1663. dma_async_device_unregister(&atdma->dma_common);
  1664. dma_pool_destroy(atdma->memset_pool);
  1665. dma_pool_destroy(atdma->dma_desc_pool);
  1666. free_irq(platform_get_irq(pdev, 0), atdma);
  1667. list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
  1668. device_node) {
  1669. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1670. /* Disable interrupts */
  1671. atc_disable_chan_irq(atdma, chan->chan_id);
  1672. tasklet_kill(&atchan->tasklet);
  1673. list_del(&chan->device_node);
  1674. }
  1675. clk_disable_unprepare(atdma->clk);
  1676. clk_put(atdma->clk);
  1677. iounmap(atdma->regs);
  1678. atdma->regs = NULL;
  1679. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1680. release_mem_region(io->start, resource_size(io));
  1681. kfree(atdma);
  1682. return 0;
  1683. }
  1684. static void at_dma_shutdown(struct platform_device *pdev)
  1685. {
  1686. struct at_dma *atdma = platform_get_drvdata(pdev);
  1687. at_dma_off(platform_get_drvdata(pdev));
  1688. clk_disable_unprepare(atdma->clk);
  1689. }
  1690. static int at_dma_prepare(struct device *dev)
  1691. {
  1692. struct at_dma *atdma = dev_get_drvdata(dev);
  1693. struct dma_chan *chan, *_chan;
  1694. list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
  1695. device_node) {
  1696. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1697. /* wait for transaction completion (except in cyclic case) */
  1698. if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
  1699. return -EAGAIN;
  1700. }
  1701. return 0;
  1702. }
  1703. static void atc_suspend_cyclic(struct at_dma_chan *atchan)
  1704. {
  1705. struct dma_chan *chan = &atchan->chan_common;
  1706. /* Channel should be paused by user
  1707. * do it anyway even if it is not done already */
  1708. if (!atc_chan_is_paused(atchan)) {
  1709. dev_warn(chan2dev(chan),
  1710. "cyclic channel not paused, should be done by channel user\n");
  1711. atc_pause(chan);
  1712. }
  1713. /* now preserve additional data for cyclic operations */
  1714. /* next descriptor address in the cyclic list */
  1715. atchan->save_dscr = channel_readl(atchan, DSCR);
  1716. vdbg_dump_regs(atchan);
  1717. }
  1718. static int at_dma_suspend_noirq(struct device *dev)
  1719. {
  1720. struct at_dma *atdma = dev_get_drvdata(dev);
  1721. struct dma_chan *chan, *_chan;
  1722. /* preserve data */
  1723. list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
  1724. device_node) {
  1725. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1726. if (atc_chan_is_cyclic(atchan))
  1727. atc_suspend_cyclic(atchan);
  1728. atchan->save_cfg = channel_readl(atchan, CFG);
  1729. }
  1730. atdma->save_imr = dma_readl(atdma, EBCIMR);
  1731. /* disable DMA controller */
  1732. at_dma_off(atdma);
  1733. clk_disable_unprepare(atdma->clk);
  1734. return 0;
  1735. }
  1736. static void atc_resume_cyclic(struct at_dma_chan *atchan)
  1737. {
  1738. struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
  1739. /* restore channel status for cyclic descriptors list:
  1740. * next descriptor in the cyclic list at the time of suspend */
  1741. channel_writel(atchan, SADDR, 0);
  1742. channel_writel(atchan, DADDR, 0);
  1743. channel_writel(atchan, CTRLA, 0);
  1744. channel_writel(atchan, CTRLB, 0);
  1745. channel_writel(atchan, DSCR, atchan->save_dscr);
  1746. dma_writel(atdma, CHER, atchan->mask);
  1747. /* channel pause status should be removed by channel user
  1748. * We cannot take the initiative to do it here */
  1749. vdbg_dump_regs(atchan);
  1750. }
  1751. static int at_dma_resume_noirq(struct device *dev)
  1752. {
  1753. struct at_dma *atdma = dev_get_drvdata(dev);
  1754. struct dma_chan *chan, *_chan;
  1755. /* bring back DMA controller */
  1756. clk_prepare_enable(atdma->clk);
  1757. dma_writel(atdma, EN, AT_DMA_ENABLE);
  1758. /* clear any pending interrupt */
  1759. while (dma_readl(atdma, EBCISR))
  1760. cpu_relax();
  1761. /* restore saved data */
  1762. dma_writel(atdma, EBCIER, atdma->save_imr);
  1763. list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
  1764. device_node) {
  1765. struct at_dma_chan *atchan = to_at_dma_chan(chan);
  1766. channel_writel(atchan, CFG, atchan->save_cfg);
  1767. if (atc_chan_is_cyclic(atchan))
  1768. atc_resume_cyclic(atchan);
  1769. }
  1770. return 0;
  1771. }
  1772. static const struct dev_pm_ops at_dma_dev_pm_ops = {
  1773. .prepare = at_dma_prepare,
  1774. .suspend_noirq = at_dma_suspend_noirq,
  1775. .resume_noirq = at_dma_resume_noirq,
  1776. };
  1777. static struct platform_driver at_dma_driver = {
  1778. .remove = at_dma_remove,
  1779. .shutdown = at_dma_shutdown,
  1780. .id_table = atdma_devtypes,
  1781. .driver = {
  1782. .name = "at_hdmac",
  1783. .pm = &at_dma_dev_pm_ops,
  1784. .of_match_table = of_match_ptr(atmel_dma_dt_ids),
  1785. },
  1786. };
  1787. static int __init at_dma_init(void)
  1788. {
  1789. return platform_driver_probe(&at_dma_driver, at_dma_probe);
  1790. }
  1791. subsys_initcall(at_dma_init);
  1792. static void __exit at_dma_exit(void)
  1793. {
  1794. platform_driver_unregister(&at_dma_driver);
  1795. }
  1796. module_exit(at_dma_exit);
  1797. MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
  1798. MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
  1799. MODULE_LICENSE("GPL");
  1800. MODULE_ALIAS("platform:at_hdmac");